DE3370247D1 - Sidewall isolation for gate of field effect transistor and process for the formation thereof - Google Patents
Sidewall isolation for gate of field effect transistor and process for the formation thereofInfo
- Publication number
- DE3370247D1 DE3370247D1 DE8383110954T DE3370247T DE3370247D1 DE 3370247 D1 DE3370247 D1 DE 3370247D1 DE 8383110954 T DE8383110954 T DE 8383110954T DE 3370247 T DE3370247 T DE 3370247T DE 3370247 D1 DE3370247 D1 DE 3370247D1
- Authority
- DE
- Germany
- Prior art keywords
- gate
- formation
- field effect
- effect transistor
- sidewall isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 230000005669 field effect Effects 0.000 title 1
- 238000002955 isolation Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US44754382A | 1982-12-07 | 1982-12-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3370247D1 true DE3370247D1 (en) | 1987-04-16 |
Family
ID=23776779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383110954T Expired DE3370247D1 (en) | 1982-12-07 | 1983-11-03 | Sidewall isolation for gate of field effect transistor and process for the formation thereof |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0111706B1 (de) |
JP (1) | JPS59106172A (de) |
DE (1) | DE3370247D1 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4757361A (en) * | 1986-07-23 | 1988-07-12 | International Business Machines Corporation | Amorphous thin film transistor device |
GB2214349B (en) * | 1988-01-19 | 1991-06-26 | Standard Microsyst Smc | Process for fabricating mos devices |
US4912061A (en) * | 1988-04-04 | 1990-03-27 | Digital Equipment Corporation | Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer |
US4981810A (en) * | 1990-02-16 | 1991-01-01 | Micron Technology, Inc. | Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers |
FR2663157B1 (fr) * | 1990-06-12 | 1992-08-07 | Thomson Csf | Procede d'autoalignement des contacts metalliques sur un dispositif semiconducteur et semiconducteur autoaligne. |
US5435888A (en) * | 1993-12-06 | 1995-07-25 | Sgs-Thomson Microelectronics, Inc. | Enhanced planarization technique for an integrated circuit |
US6284584B1 (en) | 1993-12-17 | 2001-09-04 | Stmicroelectronics, Inc. | Method of masking for periphery salicidation of active regions |
US5439846A (en) * | 1993-12-17 | 1995-08-08 | Sgs-Thomson Microelectronics, Inc. | Self-aligned method for forming contact with zero offset to gate |
US6107194A (en) * | 1993-12-17 | 2000-08-22 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit |
US5512518A (en) * | 1994-06-06 | 1996-04-30 | Motorola, Inc. | Method of manufacture of multilayer dielectric on a III-V substrate |
US6080672A (en) | 1997-08-20 | 2000-06-27 | Micron Technology, Inc. | Self-aligned contact formation for semiconductor devices |
KR100236101B1 (ko) * | 1997-09-29 | 1999-12-15 | 김영환 | 반도체 소자 및 제조 방법 |
KR100239422B1 (ko) * | 1997-10-28 | 2000-01-15 | 김영환 | 반도체 소자 및 제조 방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5928992B2 (ja) * | 1975-02-14 | 1984-07-17 | 日本電信電話株式会社 | Mosトランジスタおよびその製造方法 |
US4287661A (en) * | 1980-03-26 | 1981-09-08 | International Business Machines Corporation | Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation |
FR2481005A1 (fr) * | 1980-04-17 | 1981-10-23 | Western Electric Co | Procede de fabrication de transistors a effet de champ a canal court |
US4330931A (en) * | 1981-02-03 | 1982-05-25 | Intel Corporation | Process for forming metal plated regions and lines in MOS circuits |
-
1983
- 1983-07-14 JP JP58127055A patent/JPS59106172A/ja active Granted
- 1983-11-03 DE DE8383110954T patent/DE3370247D1/de not_active Expired
- 1983-11-03 EP EP83110954A patent/EP0111706B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS59106172A (ja) | 1984-06-19 |
EP0111706A1 (de) | 1984-06-27 |
EP0111706B1 (de) | 1987-03-11 |
JPH0512867B2 (de) | 1993-02-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |