DE3370247D1 - Sidewall isolation for gate of field effect transistor and process for the formation thereof - Google Patents

Sidewall isolation for gate of field effect transistor and process for the formation thereof

Info

Publication number
DE3370247D1
DE3370247D1 DE8383110954T DE3370247T DE3370247D1 DE 3370247 D1 DE3370247 D1 DE 3370247D1 DE 8383110954 T DE8383110954 T DE 8383110954T DE 3370247 T DE3370247 T DE 3370247T DE 3370247 D1 DE3370247 D1 DE 3370247D1
Authority
DE
Germany
Prior art keywords
gate
formation
field effect
effect transistor
sidewall isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383110954T
Other languages
German (de)
English (en)
Inventor
Subramanian Srikanteswara Iyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3370247D1 publication Critical patent/DE3370247D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
DE8383110954T 1982-12-07 1983-11-03 Sidewall isolation for gate of field effect transistor and process for the formation thereof Expired DE3370247D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US44754382A 1982-12-07 1982-12-07

Publications (1)

Publication Number Publication Date
DE3370247D1 true DE3370247D1 (en) 1987-04-16

Family

ID=23776779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383110954T Expired DE3370247D1 (en) 1982-12-07 1983-11-03 Sidewall isolation for gate of field effect transistor and process for the formation thereof

Country Status (3)

Country Link
EP (1) EP0111706B1 (enExample)
JP (1) JPS59106172A (enExample)
DE (1) DE3370247D1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757361A (en) * 1986-07-23 1988-07-12 International Business Machines Corporation Amorphous thin film transistor device
GB2214349B (en) * 1988-01-19 1991-06-26 Standard Microsyst Smc Process for fabricating mos devices
US4912061A (en) * 1988-04-04 1990-03-27 Digital Equipment Corporation Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers
FR2663157B1 (fr) * 1990-06-12 1992-08-07 Thomson Csf Procede d'autoalignement des contacts metalliques sur un dispositif semiconducteur et semiconducteur autoaligne.
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5439846A (en) * 1993-12-17 1995-08-08 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US5512518A (en) * 1994-06-06 1996-04-30 Motorola, Inc. Method of manufacture of multilayer dielectric on a III-V substrate
US6080672A (en) 1997-08-20 2000-06-27 Micron Technology, Inc. Self-aligned contact formation for semiconductor devices
KR100236101B1 (ko) * 1997-09-29 1999-12-15 김영환 반도체 소자 및 제조 방법
KR100239422B1 (ko) * 1997-10-28 2000-01-15 김영환 반도체 소자 및 제조 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5928992B2 (ja) * 1975-02-14 1984-07-17 日本電信電話株式会社 Ｍｏｓトランジスタおよびその製造方法
US4287661A (en) * 1980-03-26 1981-09-08 International Business Machines Corporation Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
FR2481005A1 (fr) * 1980-04-17 1981-10-23 Western Electric Co Procede de fabrication de transistors a effet de champ a canal court
US4330931A (en) * 1981-02-03 1982-05-25 Intel Corporation Process for forming metal plated regions and lines in MOS circuits

Also Published As

Publication number Publication date
JPH0512867B2 (enExample) 1993-02-19
JPS59106172A (ja) 1984-06-19
EP0111706A1 (en) 1984-06-27
EP0111706B1 (en) 1987-03-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee