JPH0479424U - - Google Patents

Info

Publication number
JPH0479424U
JPH0479424U JP1990122541U JP12254190U JPH0479424U JP H0479424 U JPH0479424 U JP H0479424U JP 1990122541 U JP1990122541 U JP 1990122541U JP 12254190 U JP12254190 U JP 12254190U JP H0479424 U JPH0479424 U JP H0479424U
Authority
JP
Japan
Prior art keywords
gate electrode
source
soi
drain
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990122541U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990122541U priority Critical patent/JPH0479424U/ja
Priority to KR1019910018498A priority patent/KR100238699B1/ko
Publication of JPH0479424U publication Critical patent/JPH0479424U/ja
Priority to US08/213,815 priority patent/US5395772A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Description

【図面の簡単な説明】
第１図、第２図は本考案ＳＯＩＭＯＳトランジ
スタの一つの実施例を説明するためのもので、第
１図は断面図、第２図Ａ乃至Ｃは第１図に示した
ＳＯＩＭＯＳトランジスタの製造方法を工程順に
示す断面図、第３図乃至第５図は第１乃至第３の
従来例を示す断面図である。 符号の説明、９……基板、１０……絶縁膜、１
１……ＳＯＩ層、１２……ソース、１３……ドレ
イン、１４，１５……低不純物濃度領域、１７…
…ゲート電極。

Claims (1)

  1. 【実用新案登録請求の範囲】 ＳＯＩ層上のゲート電極をマスクとして該ＳＯ
    Ｉ層に不純物をドープすることにより形成された
    ソース及びドレインの内側に、該ソース及びドレ
    インからの横方向不純物拡散によりゲート電極下
    に延びた低不純物濃度領域を有する ことを特徴とするＳＯＩＭＯＳトランジスタ。
JP1990122541U 1990-11-23 1990-11-23 Pending JPH0479424U (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1990122541U JPH0479424U (ja) 1990-11-23 1990-11-23
KR1019910018498A KR100238699B1 (ko) 1990-11-23 1991-10-21 Soimos트랜지스터
US08/213,815 US5395772A (en) 1990-11-23 1994-03-17 SOI type MOS transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990122541U JPH0479424U (ja) 1990-11-23 1990-11-23

Publications (1)

Publication Number Publication Date
JPH0479424U true JPH0479424U (ja) 1992-07-10

Family

ID=14838427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990122541U Pending JPH0479424U (ja) 1990-11-23 1990-11-23

Country Status (3)

Country Link
US (1) US5395772A (ja)
JP (1) JPH0479424U (ja)
KR (1) KR100238699B1 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777763B1 (en) * 1993-10-01 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
US5472894A (en) * 1994-08-23 1995-12-05 United Microelectronics Corp. Method of fabricating lightly doped drain transistor device
US5705405A (en) * 1994-09-30 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of making the film transistor with all-around gate electrode
US5744372A (en) * 1995-04-12 1998-04-28 National Semiconductor Corporation Fabrication of complementary field-effect transistors each having multi-part channel
US5891782A (en) * 1997-08-21 1999-04-06 Sharp Microelectronics Technology, Inc. Method for fabricating an asymmetric channel doped MOS structure
US6049230A (en) * 1998-03-06 2000-04-11 International Business Machines Corporation Silicon on insulator domino logic circuits
US5917199A (en) * 1998-05-15 1999-06-29 Ois Optical Imaging Systems, Inc. Solid state imager including TFTS with variably doped contact layer system for reducing TFT leakage current and increasing mobility and method of making same
CN100442521C (zh) * 2000-08-17 2008-12-10 株式会社东芝 半导体存储装置
KR101827848B1 (ko) * 2010-10-22 2018-03-23 삼성디스플레이 주식회사 박막 트랜지스터 및 이를 구비한 표시 장치

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142566A (ja) * 1982-02-19 1983-08-24 Seiko Epson Corp 薄膜半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900001267B1 (ko) * 1983-11-30 1990-03-05 후지쓰 가부시끼가이샤 Soi형 반도체 장치의 제조방법
US4939558A (en) * 1985-09-27 1990-07-03 Texas Instruments Incorporated EEPROM memory cell and driving circuitry
JP2551127B2 (ja) * 1989-01-07 1996-11-06 三菱電機株式会社 Ｍｉｓ型半導体装置およびその製造方法
US5170232A (en) * 1989-08-24 1992-12-08 Nec Corporation MOS field-effect transistor with sidewall spacers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142566A (ja) * 1982-02-19 1983-08-24 Seiko Epson Corp 薄膜半導体装置

Also Published As

Publication number Publication date
US5395772A (en) 1995-03-07
KR920010955A (ko) 1992-06-27
KR100238699B1 (ko) 2000-01-15

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