JPH0451053B2 - - Google Patents
Info
- Publication number
- JPH0451053B2 JPH0451053B2 JP60501929A JP50192985A JPH0451053B2 JP H0451053 B2 JPH0451053 B2 JP H0451053B2 JP 60501929 A JP60501929 A JP 60501929A JP 50192985 A JP50192985 A JP 50192985A JP H0451053 B2 JPH0451053 B2 JP H0451053B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- paddle
- lead frame
- power
- cross
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002184 metal Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229920002799 BoPET Polymers 0.000 description 1
- 239000005041 Mylar™ Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49589—Capacitor integral with or on the leadframe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12033—Gunn diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/616,823 US4612564A (en) | 1984-06-04 | 1984-06-04 | Plastic integrated circuit package |
| US616823 | 1984-06-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61502295A JPS61502295A (ja) | 1986-10-09 |
| JPH0451053B2 true JPH0451053B2 (h) | 1992-08-18 |
Family
ID=24471079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60501929A Granted JPS61502295A (ja) | 1984-06-04 | 1985-04-22 | 集積回路パッケ−ジ |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4612564A (h) |
| EP (1) | EP0183724B1 (h) |
| JP (1) | JPS61502295A (h) |
| CA (1) | CA1222331A (h) |
| DE (1) | DE3572087D1 (h) |
| WO (1) | WO1985005735A1 (h) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06105721B2 (ja) * | 1985-03-25 | 1994-12-21 | 日立超エル・エス・アイエンジニアリング株式会社 | 半導体装置 |
| US5234866A (en) * | 1985-03-25 | 1993-08-10 | Hitachi, Ltd. | Semiconductor device and process for producing the same, and lead frame used in said process |
| JP2567870B2 (ja) | 1987-09-17 | 1996-12-25 | 株式会社日立製作所 | 半導体記憶装置 |
| US5365113A (en) * | 1987-06-30 | 1994-11-15 | Hitachi, Ltd. | Semiconductor device |
| JP2763004B2 (ja) * | 1987-10-20 | 1998-06-11 | 株式会社 日立製作所 | 半導体装置 |
| US4937656A (en) * | 1988-04-22 | 1990-06-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US4924291A (en) * | 1988-10-24 | 1990-05-08 | Motorola Inc. | Flagless semiconductor package |
| US5115298A (en) * | 1990-01-26 | 1992-05-19 | Texas Instruments Incorporated | Packaged integrated circuit with encapsulated electronic devices |
| JP2538717B2 (ja) * | 1990-04-27 | 1996-10-02 | 株式会社東芝 | 樹脂封止型半導体装置 |
| JPH0760838B2 (ja) * | 1990-11-13 | 1995-06-28 | 株式会社東芝 | 半導体装置 |
| US5276352A (en) * | 1990-11-15 | 1994-01-04 | Kabushiki Kaisha Toshiba | Resin sealed semiconductor device having power source by-pass connecting line |
| JPH04352436A (ja) * | 1991-05-30 | 1992-12-07 | Fujitsu Ltd | 半導体装置 |
| KR100276781B1 (ko) * | 1992-02-03 | 2001-01-15 | 비센트 비. 인그라시아 | 리드-온-칩 반도체장치 및 그 제조방법 |
| US5389577A (en) * | 1992-08-31 | 1995-02-14 | Sgs-Thomson Microelectronics, Inc. | Leadframe for integrated circuits |
| EP0595021A1 (en) * | 1992-10-28 | 1994-05-04 | International Business Machines Corporation | Improved lead frame package for electronic devices |
| TW276357B (h) * | 1993-03-22 | 1996-05-21 | Motorola Inc | |
| US5327008A (en) * | 1993-03-22 | 1994-07-05 | Motorola Inc. | Semiconductor device having universal low-stress die support and method for making the same |
| US5714792A (en) * | 1994-09-30 | 1998-02-03 | Motorola, Inc. | Semiconductor device having a reduced die support area and method for making the same |
| US5750423A (en) * | 1995-08-25 | 1998-05-12 | Dai-Ichi Seiko Co., Ltd. | Method for encapsulation of semiconductor devices with resin and leadframe therefor |
| US5907769A (en) | 1996-12-30 | 1999-05-25 | Micron Technology, Inc. | Leads under chip in conventional IC package |
| AU7706198A (en) * | 1997-05-30 | 1998-12-30 | Micron Technology, Inc. | 256 meg dynamic random access memory |
| US6201186B1 (en) | 1998-06-29 | 2001-03-13 | Motorola, Inc. | Electronic component assembly and method of making the same |
| SG112799A1 (en) | 2000-10-09 | 2005-07-28 | St Assembly Test Services Ltd | Leaded semiconductor packages and method of trimming and singulating such packages |
| US6686258B2 (en) | 2000-11-02 | 2004-02-03 | St Assembly Test Services Ltd. | Method of trimming and singulating leaded semiconductor packages |
| JP3920629B2 (ja) * | 2001-11-15 | 2007-05-30 | 三洋電機株式会社 | 半導体装置 |
| US7489488B2 (en) * | 2005-10-19 | 2009-02-10 | Littelfuse, Inc. | Integrated circuit providing overvoltage protection for low voltage lines |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54140465A (en) * | 1978-04-24 | 1979-10-31 | Hitachi Ltd | Lead frame |
| US4346396A (en) * | 1979-03-12 | 1982-08-24 | Western Electric Co., Inc. | Electronic device assembly and methods of making same |
| JPS5753947A (en) * | 1980-09-17 | 1982-03-31 | Hitachi Ltd | Transistor and electronic device containing it |
| GB2091035B (en) * | 1981-01-12 | 1985-01-09 | Avx Corp | Integrated circuit device and sub-assembly |
| JPS5827353A (ja) * | 1981-08-11 | 1983-02-18 | Toshiba Corp | 半導体装置用リ−ドフレ−ム |
| US4417266A (en) * | 1981-08-14 | 1983-11-22 | Amp Incorporated | Power and ground plane structure for chip carrier |
-
1984
- 1984-06-04 US US06/616,823 patent/US4612564A/en not_active Expired - Lifetime
-
1985
- 1985-04-22 EP EP85902347A patent/EP0183724B1/en not_active Expired
- 1985-04-22 DE DE8585902347T patent/DE3572087D1/de not_active Expired
- 1985-04-22 WO PCT/US1985/000743 patent/WO1985005735A1/en active IP Right Grant
- 1985-04-22 JP JP60501929A patent/JPS61502295A/ja active Granted
- 1985-04-30 CA CA000480385A patent/CA1222331A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0183724B1 (en) | 1989-08-02 |
| JPS61502295A (ja) | 1986-10-09 |
| WO1985005735A1 (en) | 1985-12-19 |
| US4612564A (en) | 1986-09-16 |
| CA1222331A (en) | 1987-05-26 |
| EP0183724A1 (en) | 1986-06-11 |
| DE3572087D1 (en) | 1989-09-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |