JPH0446014B2 - - Google Patents

Info

Publication number
JPH0446014B2
JPH0446014B2 JP57157007A JP15700782A JPH0446014B2 JP H0446014 B2 JPH0446014 B2 JP H0446014B2 JP 57157007 A JP57157007 A JP 57157007A JP 15700782 A JP15700782 A JP 15700782A JP H0446014 B2 JPH0446014 B2 JP H0446014B2
Authority
JP
Japan
Prior art keywords
mos
fet
logic
setting circuit
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57157007A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5945720A (ja
Inventor
Hideji Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57157007A priority Critical patent/JPS5945720A/ja
Publication of JPS5945720A publication Critical patent/JPS5945720A/ja
Publication of JPH0446014B2 publication Critical patent/JPH0446014B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
JP57157007A 1982-09-09 1982-09-09 Ｃｍｏｓ論理回路 Granted JPS5945720A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57157007A JPS5945720A (ja) 1982-09-09 1982-09-09 Ｃｍｏｓ論理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57157007A JPS5945720A (ja) 1982-09-09 1982-09-09 Ｃｍｏｓ論理回路

Publications (2)

Publication Number Publication Date
JPS5945720A JPS5945720A (ja) 1984-03-14
JPH0446014B2 true JPH0446014B2 (enEXAMPLES) 1992-07-28

Family

ID=15640136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57157007A Granted JPS5945720A (ja) 1982-09-09 1982-09-09 Ｃｍｏｓ論理回路

Country Status (1)

Country Link
JP (1) JPS5945720A (enEXAMPLES)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293426A (ja) * 1986-06-12 1987-12-21 Matsushita Electric Ind Co Ltd 一致検出回路
EP0322885A3 (en) * 1987-12-28 1989-08-30 Kabushiki Kaisha Toshiba Determination circuit for data coincidence
KR100919567B1 (ko) * 2002-12-27 2009-10-01 주식회사 하이닉스반도체 배타적 오아게이트 회로

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56198Y2 (enEXAMPLES) * 1976-09-16 1981-01-07

Also Published As

Publication number Publication date
JPS5945720A (ja) 1984-03-14

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