JPH0374508B2 - - Google Patents

Info

Publication number
JPH0374508B2
JPH0374508B2 JP61062981A JP6298186A JPH0374508B2 JP H0374508 B2 JPH0374508 B2 JP H0374508B2 JP 61062981 A JP61062981 A JP 61062981A JP 6298186 A JP6298186 A JP 6298186A JP H0374508 B2 JPH0374508 B2 JP H0374508B2
Authority
JP
Japan
Prior art keywords
forming
contact pad
post
substrate
dimensional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61062981A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62219954A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP61062981A priority Critical patent/JPS62219954A/ja
Priority to KR1019870002514A priority patent/KR900008647B1/ko
Priority to DE8787104091T priority patent/DE3778944D1/de
Priority to EP87104091A priority patent/EP0238089B1/en
Publication of JPS62219954A publication Critical patent/JPS62219954A/ja
Priority to US07/325,122 priority patent/US4939568A/en
Publication of JPH0374508B2 publication Critical patent/JPH0374508B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP61062981A 1986-03-20 1986-03-20 三次元ｉｃの製造方法 Granted JPS62219954A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP61062981A JPS62219954A (ja) 1986-03-20 1986-03-20 三次元ｉｃの製造方法
KR1019870002514A KR900008647B1 (ko) 1986-03-20 1987-03-19 3차원 집적회로와 그의 제조방법
DE8787104091T DE3778944D1 (de) 1986-03-20 1987-03-20 Dreidimensionale integrierte schaltung und deren herstellungsverfahren.
EP87104091A EP0238089B1 (en) 1986-03-20 1987-03-20 Three-dimensional integrated circuit and manufacturing method therefor
US07/325,122 US4939568A (en) 1986-03-20 1989-03-17 Three-dimensional integrated circuit and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61062981A JPS62219954A (ja) 1986-03-20 1986-03-20 三次元ｉｃの製造方法

Publications (2)

Publication Number Publication Date
JPS62219954A JPS62219954A (ja) 1987-09-28
JPH0374508B2 true JPH0374508B2 (https=) 1991-11-27

Family

ID=13216045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61062981A Granted JPS62219954A (ja) 1986-03-20 1986-03-20 三次元ｉｃの製造方法

Country Status (1)

Country Link
JP (1) JPS62219954A (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817177B2 (ja) * 1987-11-16 1996-02-21 日産自動車株式会社 半導体装置
JPH01189141A (ja) * 1988-01-25 1989-07-28 Nec Corp 半導体装置
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
WO1998019337A1 (en) 1996-10-29 1998-05-07 Trusi Technologies, Llc Integrated circuits and methods for their fabrication
JP4126747B2 (ja) * 1998-02-27 2008-07-30 セイコーエプソン株式会社 ３次元デバイスの製造方法
JP4085459B2 (ja) * 1998-03-02 2008-05-14 セイコーエプソン株式会社 ３次元デバイスの製造方法
ATE537558T1 (de) * 2001-10-01 2011-12-15 Electro Scient Ind Inc Bearbeiten von substraten, insbesondere von halbleitersubstraten
JP4190211B2 (ja) * 2002-06-05 2008-12-03 株式会社東京精密 基板加工方法および基板加工装置
JP3690407B2 (ja) 2003-07-31 2005-08-31 セイコーエプソン株式会社 半導体装置の製造方法
JP5072210B2 (ja) * 2004-10-05 2012-11-14 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20080200011A1 (en) * 2006-10-06 2008-08-21 Pillalamarri Sunil K High-temperature, spin-on, bonding compositions for temporary wafer bonding using sliding approach
SG156550A1 (en) * 2008-05-06 2009-11-26 Gautham Viswanadam Wafer level integration module with interconnects
FR3082663B1 (fr) * 2018-06-14 2022-01-07 Aledia Dispositif optoelectronique

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607149A (ja) * 1983-06-24 1985-01-14 Nec Corp 半導体装置の製造方法
JPS6098654A (ja) * 1983-11-02 1985-06-01 Nec Corp 半導体装置の製造方法
JPS60235446A (ja) * 1984-05-09 1985-11-22 Nec Corp 半導体装置とその製造方法

Also Published As

Publication number Publication date
JPS62219954A (ja) 1987-09-28

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