JPH0353662B2 - - Google Patents

Info

Publication number
JPH0353662B2
JPH0353662B2 JP59190339A JP19033984A JPH0353662B2 JP H0353662 B2 JPH0353662 B2 JP H0353662B2 JP 59190339 A JP59190339 A JP 59190339A JP 19033984 A JP19033984 A JP 19033984A JP H0353662 B2 JPH0353662 B2 JP H0353662B2
Authority
JP
Japan
Prior art keywords
input
output
byte
data
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59190339A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6182261A (ja
Inventor
Katsuhiko Shioya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19033984A priority Critical patent/JPS6182261A/ja
Publication of JPS6182261A publication Critical patent/JPS6182261A/ja
Publication of JPH0353662B2 publication Critical patent/JPH0353662B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP19033984A 1984-09-11 1984-09-11 入出力システム Granted JPS6182261A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19033984A JPS6182261A (ja) 1984-09-11 1984-09-11 入出力システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19033984A JPS6182261A (ja) 1984-09-11 1984-09-11 入出力システム

Publications (2)

Publication Number Publication Date
JPS6182261A JPS6182261A (ja) 1986-04-25
JPH0353662B2 true JPH0353662B2 (enExample) 1991-08-15

Family

ID=16256547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19033984A Granted JPS6182261A (ja) 1984-09-11 1984-09-11 入出力システム

Country Status (1)

Country Link
JP (1) JPS6182261A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6466766A (en) * 1987-09-08 1989-03-13 Nec Corp Output data production/output system for asynchronous output

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5913768B2 (ja) * 1979-04-04 1984-03-31 富士通株式会社 チャネル転送制御方式

Also Published As

Publication number Publication date
JPS6182261A (ja) 1986-04-25

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