JPH0351096B2 - - Google Patents
Info
- Publication number
- JPH0351096B2 JPH0351096B2 JP58249507A JP24950783A JPH0351096B2 JP H0351096 B2 JPH0351096 B2 JP H0351096B2 JP 58249507 A JP58249507 A JP 58249507A JP 24950783 A JP24950783 A JP 24950783A JP H0351096 B2 JPH0351096 B2 JP H0351096B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- bonding
- wire
- chip
- head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H10W72/50—
-
- H10W72/07532—
-
- H10W72/536—
-
- H10W72/5363—
-
- H10W72/5445—
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- H10W72/5473—
-
- H10W72/884—
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- H10W72/932—
-
- H10W90/754—
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58249507A JPS60143639A (ja) | 1983-12-29 | 1983-12-29 | 集積回路装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58249507A JPS60143639A (ja) | 1983-12-29 | 1983-12-29 | 集積回路装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60143639A JPS60143639A (ja) | 1985-07-29 |
| JPH0351096B2 true JPH0351096B2 (enExample) | 1991-08-05 |
Family
ID=17193990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58249507A Granted JPS60143639A (ja) | 1983-12-29 | 1983-12-29 | 集積回路装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60143639A (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5239747A (en) * | 1991-09-18 | 1993-08-31 | Sgs-Thomson Microelectronics, Inc. | Method of forming integrated circuit devices |
| US5340772A (en) * | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die |
| US5461544A (en) * | 1993-03-05 | 1995-10-24 | Sgs-Thomson Microelectronics, Inc. | Structure and method for connecting leads from multiple chips |
| KR0156622B1 (ko) * | 1995-04-27 | 1998-10-15 | 문정환 | 반도체 패키지,리드프레임 및 제조방법 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5111342Y2 (enExample) * | 1971-12-29 | 1976-03-26 | ||
| JPS5420315B2 (enExample) * | 1974-07-15 | 1979-07-21 | ||
| JPS52120549U (enExample) * | 1975-10-20 | 1977-09-13 | ||
| JPS5794946U (enExample) * | 1980-12-03 | 1982-06-11 | ||
| JPS5881181A (ja) * | 1981-11-06 | 1983-05-16 | Matsushita Electric Ind Co Ltd | 感熱記録ヘツド |
-
1983
- 1983-12-29 JP JP58249507A patent/JPS60143639A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60143639A (ja) | 1985-07-29 |
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