JPH0340949B2 - - Google Patents

Info

Publication number
JPH0340949B2
JPH0340949B2 JP57111021A JP11102182A JPH0340949B2 JP H0340949 B2 JPH0340949 B2 JP H0340949B2 JP 57111021 A JP57111021 A JP 57111021A JP 11102182 A JP11102182 A JP 11102182A JP H0340949 B2 JPH0340949 B2 JP H0340949B2
Authority
JP
Japan
Prior art keywords
chip
adhesive
tape
protective film
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57111021A
Other languages
English (en)
Japanese (ja)
Other versions
JPS592353A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP57111021A priority Critical patent/JPS592353A/ja
Publication of JPS592353A publication Critical patent/JPS592353A/ja
Publication of JPH0340949B2 publication Critical patent/JPH0340949B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP57111021A 1982-06-28 1982-06-28 半導体装置の製造方法 Granted JPS592353A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57111021A JPS592353A (ja) 1982-06-28 1982-06-28 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57111021A JPS592353A (ja) 1982-06-28 1982-06-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS592353A JPS592353A (ja) 1984-01-07
JPH0340949B2 true JPH0340949B2 (enrdf_load_stackoverflow) 1991-06-20

Family

ID=14550376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57111021A Granted JPS592353A (ja) 1982-06-28 1982-06-28 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS592353A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121956A (ja) * 1982-12-28 1984-07-14 Tomoegawa Paper Co Ltd 耐熱性接着シ−ト

Also Published As

Publication number Publication date
JPS592353A (ja) 1984-01-07

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