JPH0216057B2 - - Google Patents

Info

Publication number
JPH0216057B2
JPH0216057B2 JP55183075A JP18307580A JPH0216057B2 JP H0216057 B2 JPH0216057 B2 JP H0216057B2 JP 55183075 A JP55183075 A JP 55183075A JP 18307580 A JP18307580 A JP 18307580A JP H0216057 B2 JPH0216057 B2 JP H0216057B2
Authority
JP
Japan
Prior art keywords
point
transistor
during
power supply
standby period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55183075A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57106228A (en
Inventor
Tomio Nakano
Yoshihiro Takemae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55183075A priority Critical patent/JPS57106228A/ja
Priority to US06/331,476 priority patent/US4443714A/en
Priority to DE8181306074T priority patent/DE3170062D1/de
Priority to IE3068/81A priority patent/IE52382B1/en
Priority to EP81306074A priority patent/EP0055136B1/en
Publication of JPS57106228A publication Critical patent/JPS57106228A/ja
Publication of JPH0216057B2 publication Critical patent/JPH0216057B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
JP55183075A 1980-12-24 1980-12-24 Semiconductor circuit Granted JPS57106228A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55183075A JPS57106228A (en) 1980-12-24 1980-12-24 Semiconductor circuit
US06/331,476 US4443714A (en) 1980-12-24 1981-12-16 Semiconductor buffer circuit having compensation for power source fluctuation
DE8181306074T DE3170062D1 (en) 1980-12-24 1981-12-23 A semiconductor buffer circuit
IE3068/81A IE52382B1 (en) 1980-12-24 1981-12-23 A semiconductor buffer circuit
EP81306074A EP0055136B1 (en) 1980-12-24 1981-12-23 A semiconductor buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55183075A JPS57106228A (en) 1980-12-24 1980-12-24 Semiconductor circuit

Publications (2)

Publication Number Publication Date
JPS57106228A JPS57106228A (en) 1982-07-02
JPH0216057B2 true JPH0216057B2 (US08197722-20120612-C00042.png) 1990-04-16

Family

ID=16129309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55183075A Granted JPS57106228A (en) 1980-12-24 1980-12-24 Semiconductor circuit

Country Status (5)

Country Link
US (1) US4443714A (US08197722-20120612-C00042.png)
EP (1) EP0055136B1 (US08197722-20120612-C00042.png)
JP (1) JPS57106228A (US08197722-20120612-C00042.png)
DE (1) DE3170062D1 (US08197722-20120612-C00042.png)
IE (1) IE52382B1 (US08197722-20120612-C00042.png)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133589A (en) * 1981-02-12 1982-08-18 Fujitsu Ltd Semiconductor circuit
JPS599735A (ja) * 1982-07-07 1984-01-19 Mitsubishi Electric Corp クロツク発生回路
JPS5958920A (ja) * 1982-09-28 1984-04-04 Fujitsu Ltd バツフア回路
JPS60111391A (ja) * 1983-11-21 1985-06-17 Nec Corp 半導体出力回路
JPS60140924A (ja) * 1983-12-27 1985-07-25 Nec Corp 半導体回路
US4642492A (en) * 1984-10-25 1987-02-10 Digital Equipment Corporation Multiple phase clock buffer module with non-saturated pull-up transistor to avoid hot electron effects
US4797573A (en) * 1984-11-21 1989-01-10 Nec Corporation Output circuit with improved timing control circuit
JP2548908B2 (ja) * 1985-04-13 1996-10-30 富士通株式会社 昇圧回路
JPS62159917A (ja) * 1986-01-08 1987-07-15 Toshiba Corp 集積回路におけるインバ−タ回路
JPH02161813A (ja) * 1988-12-14 1990-06-21 Nec Corp Ｒｓ２３２ｃラインドライバｉｃ
DE3904901A1 (de) * 1989-02-17 1990-08-23 Texas Instruments Deutschland Integrierte gegentakt-ausgangsstufe
KR0170511B1 (ko) * 1995-11-09 1999-03-30 김광호 모스 트랜지스터 구동용 차지펌프회로
US6788108B2 (en) 2001-07-30 2004-09-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7834668B2 (en) 2005-10-07 2010-11-16 Nxp B.V. Single threshold and single conductivity type amplifier/buffer
JP5665299B2 (ja) 2008-10-31 2015-02-04 三菱電機株式会社 シフトレジスタ回路
JP5188382B2 (ja) 2008-12-25 2013-04-24 三菱電機株式会社 シフトレジスタ回路
JP6628837B2 (ja) * 2018-06-15 2020-01-15 株式会社半導体エネルギー研究所 電子機器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5194746A (US08197722-20120612-C00042.png) * 1975-02-19 1976-08-19

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909631A (en) * 1973-08-02 1975-09-30 Texas Instruments Inc Pre-charge voltage generating system
US3927334A (en) * 1974-04-11 1975-12-16 Electronic Arrays MOSFET bistrap buffer
US4061999A (en) * 1975-12-29 1977-12-06 Mostek Corporation Dynamic random access memory system
US4061933A (en) * 1975-12-29 1977-12-06 Mostek Corporation Clock generator and delay stage
DE2641693C2 (de) * 1976-09-16 1978-11-16 Siemens Ag, 1000 Berlin Und 8000 Muenchen Decodierschaltung mit MOS-Transistoren
JPS54965A (en) * 1977-06-06 1979-01-06 Hitachi Ltd Voltage clamp circuit
JPS5513566A (en) * 1978-07-17 1980-01-30 Hitachi Ltd Mis field effect semiconductor circuit device
US4317051A (en) * 1979-10-09 1982-02-23 Bell Telephone Laboratories, Incorporated Clock generator (buffer) circuit
EP0060246A1 (en) * 1980-09-10 1982-09-22 Mostek Corporation Delay stage for a clock generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5194746A (US08197722-20120612-C00042.png) * 1975-02-19 1976-08-19

Also Published As

Publication number Publication date
EP0055136A3 (en) 1982-08-11
DE3170062D1 (en) 1985-05-23
EP0055136B1 (en) 1985-04-17
IE52382B1 (en) 1987-10-14
IE813068L (en) 1982-06-24
US4443714A (en) 1984-04-17
JPS57106228A (en) 1982-07-02
EP0055136A2 (en) 1982-06-30

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