JPH0212751B2 - - Google Patents

Info

Publication number
JPH0212751B2
JPH0212751B2 JP59177761A JP17776184A JPH0212751B2 JP H0212751 B2 JPH0212751 B2 JP H0212751B2 JP 59177761 A JP59177761 A JP 59177761A JP 17776184 A JP17776184 A JP 17776184A JP H0212751 B2 JPH0212751 B2 JP H0212751B2
Authority
JP
Japan
Prior art keywords
board
substrate
multilayer
product size
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59177761A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6154938A (ja
Inventor
Toshiro Kodama
Kyuzo Mitsui
Nobuo Sakuragi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59177761A priority Critical patent/JPS6154938A/ja
Publication of JPS6154938A publication Critical patent/JPS6154938A/ja
Publication of JPH0212751B2 publication Critical patent/JPH0212751B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP59177761A 1984-08-27 1984-08-27 多層プリント板の製造方法 Granted JPS6154938A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59177761A JPS6154938A (ja) 1984-08-27 1984-08-27 多層プリント板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59177761A JPS6154938A (ja) 1984-08-27 1984-08-27 多層プリント板の製造方法

Publications (2)

Publication Number Publication Date
JPS6154938A JPS6154938A (ja) 1986-03-19
JPH0212751B2 true JPH0212751B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-03-26

Family

ID=16036665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59177761A Granted JPS6154938A (ja) 1984-08-27 1984-08-27 多層プリント板の製造方法

Country Status (1)

Country Link
JP (1) JPS6154938A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6248099A (ja) * 1985-08-28 1987-03-02 富士通株式会社 中間層基板
JP2561658B2 (ja) * 1987-02-23 1996-12-11 日立化成工業株式会社 多層印刷配線板の製造方法
JPH01147896A (ja) * 1987-12-03 1989-06-09 Aica Kogyo Co Ltd 多層印刷回路板の製法
JPH02234494A (ja) * 1989-03-07 1990-09-17 Fujitsu Ltd 銅板入り多層プリント基板の製造方法
JPH0783179B2 (ja) * 1989-12-14 1995-09-06 日本電気株式会社 多層印刷配線板の製造方法
JPH05145235A (ja) * 1991-11-20 1993-06-11 Nippon Avionics Co Ltd 多層プリント配線板の製造方法および積層基板
JP3038282B2 (ja) * 1993-04-12 2000-05-08 株式会社日立製作所 スロットル弁開閉装置

Also Published As

Publication number Publication date
JPS6154938A (ja) 1986-03-19

Similar Documents

Publication Publication Date Title
US5578796A (en) Apparatus for laminating and circuitizing substrates having openings therein
TW201424501A (zh) 封裝結構及其製作方法
US4884170A (en) Multilayer printed circuit board and method of producing the same
US5281556A (en) Process for manufacturing a multi-layer lead frame having a ground plane and a power supply plane
US7172925B2 (en) Method for manufacturing printed wiring board
JPH0212751B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
HK1001936B (en) Lead frame assembly process
JPH04278598A (ja) 多層印刷配線板の製造方法
JP2003318309A (ja) キャビティ付き多層セラミック基板の製造方法
JP3736450B2 (ja) 回路基板の製造方法
JP3111590B2 (ja) 多層回路の製造方法
US6607939B2 (en) Method of making a multi-layer interconnect
JPS5841800B2 (ja) セラミック多層基板の形成方法
US20240155765A1 (en) Electronic component embedded substrate and manufacturing method therefor
JP3058045B2 (ja) 多層プリント配線板の製造方法
JP3749201B2 (ja) プリント配線板の製造方法
JPH08162769A (ja) 多層プリント基板の製造方法
JP2004214273A (ja) 片面積層配線基板の製造方法
JPH0545079B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS60241294A (ja) 多層印刷配線板の製造方法
JPH04211195A (ja) セラミック多層配線基板の製造方法
JPH01258495A (ja) セラミック多層基板の製造方法
JP2004152964A (ja) 多層配線基板の製造方法
JP2004241425A (ja) 多数個取り配線基板
JP2025024840A (ja) 電子部品内蔵プリント配線板およびその製造方法