JPH0146955B2 - - Google Patents

Info

Publication number
JPH0146955B2
JPH0146955B2 JP56031750A JP3175081A JPH0146955B2 JP H0146955 B2 JPH0146955 B2 JP H0146955B2 JP 56031750 A JP56031750 A JP 56031750A JP 3175081 A JP3175081 A JP 3175081A JP H0146955 B2 JPH0146955 B2 JP H0146955B2
Authority
JP
Japan
Prior art keywords
clock
refresh
input circuit
input
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56031750A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57147193A (en
Inventor
Yoshihiro Takemae
Shigeki Nozaki
Katsuhiko Kabashima
Seiji Emoto
Tsutomu Mezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56031750A priority Critical patent/JPS57147193A/ja
Priority to US06/354,499 priority patent/US4451908A/en
Priority to IE492/82A priority patent/IE54166B1/en
Priority to DE8282301141T priority patent/DE3278924D1/de
Priority to EP82301141A priority patent/EP0060108B1/en
Publication of JPS57147193A publication Critical patent/JPS57147193A/ja
Publication of JPH0146955B2 publication Critical patent/JPH0146955B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP56031750A 1981-03-05 1981-03-05 Address buffer Granted JPS57147193A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56031750A JPS57147193A (en) 1981-03-05 1981-03-05 Address buffer
US06/354,499 US4451908A (en) 1981-03-05 1982-03-03 Address Buffer
IE492/82A IE54166B1 (en) 1981-03-05 1982-03-04 Address buffer
DE8282301141T DE3278924D1 (en) 1981-03-05 1982-03-05 Address buffer
EP82301141A EP0060108B1 (en) 1981-03-05 1982-03-05 Address buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56031750A JPS57147193A (en) 1981-03-05 1981-03-05 Address buffer

Publications (2)

Publication Number Publication Date
JPS57147193A JPS57147193A (en) 1982-09-10
JPH0146955B2 true JPH0146955B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-10-11

Family

ID=12339691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56031750A Granted JPS57147193A (en) 1981-03-05 1981-03-05 Address buffer

Country Status (5)

Country Link
US (1) US4451908A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0060108B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS57147193A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3278924D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IE (1) IE54166B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151893A (ja) * 1984-01-18 1985-08-09 Nec Corp 半導体メモリ回路
JPH0612614B2 (ja) * 1986-06-06 1994-02-16 日本電気株式会社 半導体集積回路
JPS63157397A (ja) * 1986-12-22 1988-06-30 Matsushita Electronics Corp 半導体メモリ
JPH07101553B2 (ja) * 1989-02-15 1995-11-01 三菱電機株式会社 バッファ回路およびその動作方法
JP2547268B2 (ja) * 1990-03-14 1996-10-23 シャープ株式会社 半導体記憶装置の内部アドレス決定装置
KR100353544B1 (en) 2000-12-27 2002-09-27 Hynix Semiconductor Inc Circuit for generating internal supply voltage of semiconductor memory device
KR100390238B1 (ko) 2001-05-18 2003-07-07 주식회사 하이닉스반도체 뱅크 어드레스를 이용한 반도체 메모리 소자의 어드레스제어 장치

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3737879A (en) * 1972-01-05 1973-06-05 Mos Technology Inc Self-refreshing memory
US4207618A (en) * 1978-06-26 1980-06-10 Texas Instruments Incorporated On-chip refresh for dynamic memory
WO1981003567A1 (en) * 1980-06-02 1981-12-10 Mostek Corp Semiconductor memory for use in conjunction with error detection and correction circuit

Also Published As

Publication number Publication date
IE820492L (en) 1982-09-05
JPS57147193A (en) 1982-09-10
EP0060108A3 (en) 1985-09-18
US4451908A (en) 1984-05-29
DE3278924D1 (en) 1988-09-22
EP0060108B1 (en) 1988-08-17
IE54166B1 (en) 1989-07-05
EP0060108A2 (en) 1982-09-15

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