JPH01104730U - - Google Patents
Info
- Publication number
- JPH01104730U JPH01104730U JP1987201351U JP20135187U JPH01104730U JP H01104730 U JPH01104730 U JP H01104730U JP 1987201351 U JP1987201351 U JP 1987201351U JP 20135187 U JP20135187 U JP 20135187U JP H01104730 U JPH01104730 U JP H01104730U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- antistatic
- semiconductor device
- sealed semiconductor
- antistatic member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の樹脂封止半導体装置の斜視図
、第２図は本考案の帯電防止部材の構成図、第３
図は従来の樹脂封止半導体装置の構成図、第４図
は本考案の第２実施例を示す樹脂封止半導体装置
の製造状態を示す図である。 １０……半導体素子パツケージ、１１……リー
ド、１２……捺印用開口部、１３……上部帯電防
止部材、１４……下部帯電防止部材、１５，１６
……短手方向の側面部、１７……封止樹脂、２０
……金型、２１……上部帯電防止部材の成形部、
２２……下部帯電防止部材の成形部、２３，２４
……ゲート、２５，２６……ランナ。
、第２図は本考案の帯電防止部材の構成図、第３
図は従来の樹脂封止半導体装置の構成図、第４図
は本考案の第２実施例を示す樹脂封止半導体装置
の製造状態を示す図である。 １０……半導体素子パツケージ、１１……リー
ド、１２……捺印用開口部、１３……上部帯電防
止部材、１４……下部帯電防止部材、１５，１６
……短手方向の側面部、１７……封止樹脂、２０
……金型、２１……上部帯電防止部材の成形部、
２２……下部帯電防止部材の成形部、２３，２４
……ゲート、２５，２６……ランナ。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 半導体素子パツケージの少なくとも上部面
及び下部面に帯電防止手段を施してなる樹脂封止
半導体装置において、 前記帯電防止手段は繊維状導電体を含む帯電防
止部材からなり、該帯電防止部材の上部面には捺
印用開孔部を具備することを特徴とする樹脂封止
半導体装置。 (2) 前記帯電防止部材は半導体素子パツケージ
に接着により形成してなる実用新案登録請求の範
囲第１項記載の樹脂封止半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987201351U JPH01104730U (ja) | 1987-12-28 | 1987-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987201351U JPH01104730U (ja) | 1987-12-28 | 1987-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01104730U true JPH01104730U (ja) | 1989-07-14 |
Family
ID=31491715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987201351U Pending JPH01104730U (ja) | 1987-12-28 | 1987-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01104730U (ja) |
-
1987
- 1987-12-28 JP JP1987201351U patent/JPH01104730U/ja active Pending