JP7408885B2 - リードフレーム - Google Patents

リードフレーム Download PDF

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Publication number
JP7408885B2
JP7408885B2 JP2020014013A JP2020014013A JP7408885B2 JP 7408885 B2 JP7408885 B2 JP 7408885B2 JP 2020014013 A JP2020014013 A JP 2020014013A JP 2020014013 A JP2020014013 A JP 2020014013A JP 7408885 B2 JP7408885 B2 JP 7408885B2
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JP
Japan
Prior art keywords
plating layer
external connection
lead frame
region
lead
Prior art date
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JP2020014013A
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English (en)
Japanese (ja)
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JP2021120991A (ja
Inventor
覚史 久保田
直樹 渡邊
Original Assignee
長華科技股▲ふん▼有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 長華科技股▲ふん▼有限公司 filed Critical 長華科技股▲ふん▼有限公司
Priority to JP2020014013A priority Critical patent/JP7408885B2/ja
Priority to TW110102581A priority patent/TWI811617B/zh
Priority to CN202110118804.1A priority patent/CN113270387A/zh
Publication of JP2021120991A publication Critical patent/JP2021120991A/ja
Application granted granted Critical
Publication of JP7408885B2 publication Critical patent/JP7408885B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2020014013A 2020-01-30 2020-01-30 リードフレーム Active JP7408885B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2020014013A JP7408885B2 (ja) 2020-01-30 2020-01-30 リードフレーム
TW110102581A TWI811617B (zh) 2020-01-30 2021-01-22 引線框架
CN202110118804.1A CN113270387A (zh) 2020-01-30 2021-01-28 引线框架

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020014013A JP7408885B2 (ja) 2020-01-30 2020-01-30 リードフレーム

Publications (2)

Publication Number Publication Date
JP2021120991A JP2021120991A (ja) 2021-08-19
JP7408885B2 true JP7408885B2 (ja) 2024-01-09

Family

ID=77228031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020014013A Active JP7408885B2 (ja) 2020-01-30 2020-01-30 リードフレーム

Country Status (3)

Country Link
JP (1) JP7408885B2 (zh)
CN (1) CN113270387A (zh)
TW (1) TWI811617B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015145651A1 (ja) 2014-03-27 2015-10-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
WO2018126038A1 (en) 2016-12-30 2018-07-05 Texas Instruments Incorporated Packaged semiconductor device with a particle roughened surface
JP2018139263A (ja) 2017-02-24 2018-09-06 株式会社東芝 半導体パッケージおよびその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6169842U (zh) * 1984-10-13 1986-05-13
JPH04254366A (ja) * 1991-01-30 1992-09-09 Ibiden Co Ltd 両面金属箔張フィルム基材及びこれを主材とする電子部品搭載用フィルムキャリア並びにこれらの製造方法
JPH11251505A (ja) * 1998-03-04 1999-09-17 Matsushita Electron Corp 半導体装置及びその製造方法
JP4372508B2 (ja) * 2003-10-06 2009-11-25 ローム株式会社 リードフレームの製造方法およびそれを用いた半導体装置の製造方法、ならびに半導体装置ならびにそれを備えた携帯機器および電子装置
TWI397964B (zh) * 2011-01-19 2013-06-01 Unisem Mauritius Holdings Ltd 部分圖案化之引線框架及其在半導體封裝中製作與使用的方法
JP6841550B2 (ja) * 2017-05-29 2021-03-10 大口マテリアル株式会社 リードフレーム及びその製造方法
JP6927634B2 (ja) * 2017-09-20 2021-09-01 大口マテリアル株式会社 半導体素子搭載用基板及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015145651A1 (ja) 2014-03-27 2015-10-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
WO2018126038A1 (en) 2016-12-30 2018-07-05 Texas Instruments Incorporated Packaged semiconductor device with a particle roughened surface
JP2018139263A (ja) 2017-02-24 2018-09-06 株式会社東芝 半導体パッケージおよびその製造方法

Also Published As

Publication number Publication date
JP2021120991A (ja) 2021-08-19
CN113270387A (zh) 2021-08-17
TWI811617B (zh) 2023-08-11
TW202129862A (zh) 2021-08-01

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