JP7339819B2 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JP7339819B2 JP7339819B2 JP2019161250A JP2019161250A JP7339819B2 JP 7339819 B2 JP7339819 B2 JP 7339819B2 JP 2019161250 A JP2019161250 A JP 2019161250A JP 2019161250 A JP2019161250 A JP 2019161250A JP 7339819 B2 JP7339819 B2 JP 7339819B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
- H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
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- H10D64/00—Electrodes of devices having potential barriers
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- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
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- H10D8/00—Diodes
- H10D8/60—Schottky-barrier diodes
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
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- H10P30/00—Ion implantation into wafers, substrates or parts of devices
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- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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- H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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- H10P30/00—Ion implantation into wafers, substrates or parts of devices
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- H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
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- H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
- H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
- H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
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- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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- H10P50/64—Wet etching of semiconductor materials
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- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
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- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Plasma & Fusion (AREA)
- Mechanical Engineering (AREA)
- Dicing (AREA)
- Electromagnetism (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Laser Beam Processing (AREA)
- Drying Of Semiconductors (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019161250A JP7339819B2 (ja) | 2019-09-04 | 2019-09-04 | 半導体装置の製造方法および半導体装置 |
| CN202010106493.2A CN112542382B (zh) | 2019-09-04 | 2020-02-21 | 半导体装置的制造方法以及半导体装置 |
| US16/802,670 US11342426B2 (en) | 2019-09-04 | 2020-02-27 | Semiconductor device and method of manufacturing same |
| US17/725,124 US11887858B2 (en) | 2019-09-04 | 2022-04-20 | Semiconductor device and method of manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019161250A JP7339819B2 (ja) | 2019-09-04 | 2019-09-04 | 半導体装置の製造方法および半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021040068A JP2021040068A (ja) | 2021-03-11 |
| JP2021040068A5 JP2021040068A5 (https=) | 2021-10-07 |
| JP7339819B2 true JP7339819B2 (ja) | 2023-09-06 |
Family
ID=74681746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019161250A Active JP7339819B2 (ja) | 2019-09-04 | 2019-09-04 | 半導体装置の製造方法および半導体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US11342426B2 (https=) |
| JP (1) | JP7339819B2 (https=) |
| CN (1) | CN112542382B (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022044894A (ja) * | 2020-09-08 | 2022-03-18 | ソニーセミコンダクタソリューションズ株式会社 | 半導体チップ、製造方法 |
| CN116344614A (zh) * | 2021-12-22 | 2023-06-27 | 株式会社东芝 | 半导体装置及其制造方法 |
| JP2023110631A (ja) * | 2022-01-28 | 2023-08-09 | ラピスセミコンダクタ株式会社 | 半導体ウェハ及び半導体装置の製造方法 |
| DE102024209060A1 (de) | 2024-09-20 | 2026-03-26 | Infineon Technologies Ag | Electronic component separated from wafer by back side groove and groove extension |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2009105211A (ja) | 2007-10-23 | 2009-05-14 | Disco Abrasive Syst Ltd | ウエーハの分割方法 |
| US20120306056A1 (en) | 2011-06-03 | 2012-12-06 | Nxp B.V. | Semiconductor wafer and method of producing the same |
| US20140264768A1 (en) | 2013-03-15 | 2014-09-18 | Nxp B. V. | Die Preparation for Wafer-Level Chip Scale Package (WLCSP) |
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| US3838501A (en) * | 1973-02-09 | 1974-10-01 | Honeywell Inf Systems | Method in microcircuit package assembly providing nonabrasive, electrically passive edges on integrated circuit chips |
| JPH05102300A (ja) | 1991-10-07 | 1993-04-23 | Mitsubishi Electric Corp | 半導体装置 |
| JPH05166926A (ja) * | 1991-12-12 | 1993-07-02 | Hitachi Ltd | 半導体基板ダイシング法 |
| JPH06275583A (ja) * | 1993-03-24 | 1994-09-30 | Disco Abrasive Syst Ltd | 面取り半導体チップ及びその面取り加工方法 |
| JPH09141646A (ja) * | 1995-11-21 | 1997-06-03 | Sony Corp | 基板加工方法 |
| US6271102B1 (en) * | 1998-02-27 | 2001-08-07 | International Business Machines Corporation | Method and system for dicing wafers, and semiconductor structures incorporating the products thereof |
| JP2004111606A (ja) | 2002-09-18 | 2004-04-08 | Tokyo Seimitsu Co Ltd | ウェーハの加工方法 |
| US6998694B2 (en) * | 2003-08-05 | 2006-02-14 | Shye-Lin Wu | High switching speed two mask Schottky diode with high field breakdown |
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| JP2006086516A (ja) * | 2004-08-20 | 2006-03-30 | Showa Denko Kk | 半導体発光素子の製造方法 |
| JP2006140276A (ja) * | 2004-11-11 | 2006-06-01 | Yamaha Corp | 半導体ウェーハとそれを用いた半導体素子及びチップサイズ・パッケージ並びに半導体ウェーハの製造方法、半導体ウェーハの検査方法 |
| JP2006278646A (ja) * | 2005-03-29 | 2006-10-12 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
| JP2012054378A (ja) * | 2010-09-01 | 2012-03-15 | Renesas Electronics Corp | 半導体装置 |
| WO2012099080A1 (ja) * | 2011-01-18 | 2012-07-26 | 富士電機株式会社 | 逆阻止型半導体素子の製造方法 |
| JP5995435B2 (ja) * | 2011-08-02 | 2016-09-21 | ローム株式会社 | 半導体装置およびその製造方法 |
| DE102011112659B4 (de) * | 2011-09-06 | 2022-01-27 | Vishay Semiconductor Gmbh | Oberflächenmontierbares elektronisches Bauelement |
| US9704718B2 (en) * | 2013-03-22 | 2017-07-11 | Infineon Technologies Austria Ag | Method for manufacturing a silicon carbide device and a silicon carbide device |
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| JP2015053428A (ja) * | 2013-09-09 | 2015-03-19 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
| JP2015133460A (ja) * | 2014-01-16 | 2015-07-23 | 株式会社ディスコ | ウェーハの分割方法 |
| US20160148842A1 (en) * | 2014-11-24 | 2016-05-26 | Nxp B.V. | Dicing of low-k wafers |
| US9711463B2 (en) * | 2015-01-14 | 2017-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dicing method for power transistors |
| US9466585B1 (en) * | 2015-03-21 | 2016-10-11 | Nxp B.V. | Reducing defects in wafer level chip scale package (WLCSP) devices |
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| JP2017199834A (ja) * | 2016-04-28 | 2017-11-02 | 株式会社ジェイデバイス | 半導体パッケージ及び半導体パッケージの製造方法 |
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| JP6766758B2 (ja) * | 2017-06-15 | 2020-10-14 | 株式会社デンソー | 半導体装置およびその製造方法 |
| US10403506B2 (en) * | 2018-01-07 | 2019-09-03 | Infineon Technologies Ag | Separation of workpiece with three material removal stages |
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2019
- 2019-09-04 JP JP2019161250A patent/JP7339819B2/ja active Active
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2020
- 2020-02-21 CN CN202010106493.2A patent/CN112542382B/zh active Active
- 2020-02-27 US US16/802,670 patent/US11342426B2/en active Active
-
2022
- 2022-04-20 US US17/725,124 patent/US11887858B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009105211A (ja) | 2007-10-23 | 2009-05-14 | Disco Abrasive Syst Ltd | ウエーハの分割方法 |
| US20120306056A1 (en) | 2011-06-03 | 2012-12-06 | Nxp B.V. | Semiconductor wafer and method of producing the same |
| US20140264768A1 (en) | 2013-03-15 | 2014-09-18 | Nxp B. V. | Die Preparation for Wafer-Level Chip Scale Package (WLCSP) |
Also Published As
| Publication number | Publication date |
|---|---|
| US20220246734A1 (en) | 2022-08-04 |
| CN112542382B (zh) | 2024-04-09 |
| US11342426B2 (en) | 2022-05-24 |
| US20210066130A1 (en) | 2021-03-04 |
| JP2021040068A (ja) | 2021-03-11 |
| CN112542382A (zh) | 2021-03-23 |
| US11887858B2 (en) | 2024-01-30 |
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