CN112542382B - 半导体装置的制造方法以及半导体装置 - Google Patents

半导体装置的制造方法以及半导体装置 Download PDF

Info

Publication number
CN112542382B
CN112542382B CN202010106493.2A CN202010106493A CN112542382B CN 112542382 B CN112542382 B CN 112542382B CN 202010106493 A CN202010106493 A CN 202010106493A CN 112542382 B CN112542382 B CN 112542382B
Authority
CN
China
Prior art keywords
semiconductor
groove
wafer
electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010106493.2A
Other languages
English (en)
Other versions
CN112542382A (zh
Inventor
布谷伸仁
隐塚信次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Publication of CN112542382A publication Critical patent/CN112542382A/zh
Application granted granted Critical
Publication of CN112542382B publication Critical patent/CN112542382B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66128—Planar diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Plasma & Fusion (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Electromagnetism (AREA)
  • Mechanical Engineering (AREA)
  • Dicing (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Laser Beam Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

实施方式提供能够提高制造成品率的半导体装置的制造方法以及半导体装置。实施方式的半导体装置包括：半导体部；在上述半导体部的背面上设置的第1电极；及在上述半导体部的表面上设置的第2电极。上述半导体装置的制造方法包括：形成将包含成为上述半导体部的区域的晶片的背面覆盖的上述第1电极的工序；沿着成为上述半导体部的区域的外缘，形成将上述第1电极选择性地去除而成的、而且包含位于上述晶片中的部分的第1槽的工序；以及沿着上述晶片的表面中的成为上述半导体部的区域的外缘，形成与上述第1槽相连的第2槽，将上述晶片分割的工序。上述第2槽在沿着上述晶片的上述表面的方向上的宽度，形成得比上述第1槽在上述方向的宽度窄。

Description

半导体装置的制造方法以及半导体装置
关联申请
本申请享受以日本专利申请2019－161250号(申请日：2019年9月4日)为基础申请的优先权。本申请通过参照该基础申请，包含基础申请的全部内容。
技术领域
实施方式涉及半导体装置的制造方法以及半导体装置。
背景技术
在半导体装置的制造过程中，为了将晶片单片化为半导体芯片，大多使用例如冲切器等的机械加工。但是，通过这样的机械加工形成的半导体芯片，包含毛刺、缺口等，存在制造成品率低下的情况。
发明内容
实施方式提供能够提高制造成品率的半导体装置的制造方法以及半导体装置。
实施方式的半导体装置包括：半导体部；在上述半导体部的背面上设置的第1电极；及在上述半导体部的表面上设置的第2电极。上述半导体装置的制造方法包括：在包含成为上述半导体部的区域的晶片的表面上形成了上述第2电极后，形成将上述晶片的背面覆盖的上述第1电极的工序；沿着成为上述半导体部的区域的外缘，形成将上述第1电极选择性地去除而成的、而且包含位于上述晶片中的部分的第1槽的工序；以及沿着上述晶片的上述表面中的成为上述半导体部的区域的外缘，形成与上述第1槽相连的第2槽，将上述晶片分割的工序。上述第2槽在沿着上述晶片的上述表面的方向上的宽度，形成得比上述第1槽在上述方向的宽度窄。
附图说明
图1的(a)、(b)是表示实施方式的半导体装置的示意图。
图2的(a)～图5的(c)是表示实施方式的半导体装置的制造过程的示意剖视图。
图6的(a)～(c)是表示比较例的半导体装置的制造过程的示意剖视图。
图7的(a)～(c)是表示实施方式的变形例的半导体装置的制造过程的示意剖视图。
图8的(a)、(b)是表示实施方式的变形例的半导体装置的示意剖视图。
具体实施方式
以下，关于实施方式，使用附图进行说明。对图中的相同部分附以同一符号并适当省略其详细的说明，对不同的部分进行说明。另外，图是示意性的或者概念性的，各部分的厚度与宽度的关系、部分间的大小的比率等，未必与现实的相同。另外，即使在表示相同的部分的情况下，也存在根据图而彼此的尺寸、比率不同而进行表示的情况。
并且，使用各图中所示的X轴、Y轴以及Z轴，说明各部分的配置以及构成。X轴、Y轴、Z轴相互正交，分别表示X方向、Y方向、Z方向。另外，存在将Z方向作为上方，将其相反方向作为下方进行说明的情况。
图1的(a)以及(b)是表示实施方式的半导体装置1的示意图。图1的(a)是表示半导体装置1的构造的示意剖视图。图1的(b)是表示半导体装置1的背面的示意俯视图。半导体装置1例如是PIN二极管。
如图1的(a)所示，半导体装置1例如包括半导体部10、第1电极20和第2电极30。半导体部10例如是硅。第1电极20例如是阴极电极，第2电极30例如是阳极电极。
半导体部10例如包括第1半导体层13、第2半导体层15及第3半导体层17。第1半导体层13例如是I层(intrinsic layer)。第2半导体层15例如是p型阳极层，第3半导体层17例如是n型阴极层。
第2半导体层15位于第1半导体层13与第2电极30之间。第3半导体层17位于第1半导体层13与第1电极20之间，包含比第1半导体层13的n型杂质高浓度的n型杂质。
第1电极20覆盖半导体部10的背面BS，并与第3半导体层17电连接。第2电极20设置于半导体部10的表面FS的上方。第2电极20与第2半导体层15电连接。
半导体部10还具有第1侧面SS1以及第2侧面SS2。第1侧面SS1与表面FS相连，第2侧面SS2将第1侧面SS1与背面BS相连。第2侧面SS2是在半导体部10的背面BS侧设置的槽CG(参照图4的(a))的一部分。第2侧面SS2包含相对于第1侧面SS1以及背面BS倾斜的部分。
槽CG例如具有沿着背面BS的方向(X方向)的宽度WG以及沿着第1侧面SS1的方向(Z方向)的深度DG。槽CG例如具有比宽度WG浅的深度DG(WG＞DG)。
如图1的(b)所示，槽CG沿着半导体部10的外缘而设置。槽CG例如在X方向以及Y方向上延伸。
另外，在半导体装置1是肖特基势垒二极管(SBD)的情况下，不设置第2半导体层15(p型阳极层)，第2电极30例如与第1半导体层13直接接触。
接下来，参照图2的(a)～图5的(c)，对半导体装置1的制造方法进行说明。图2的(a)～图5的(c)是表示实施方式的半导体装置1的制造过程的示意剖视图。
如图2的(a)所示，在半导体晶片100的表面FS侧形成了第2半导体层15后，在第2半导体层15的上方选择性地形成第2电极30。半导体晶片100例如是使杂质浓度较低的n型硅晶片。第2半导体层15通过对半导体晶片100选择性地离子注入p型杂质例如硼(B)而形成。第2电极30与第2半导体层15电连接。第2电极30例如包含铝、钨、钛等。
如图2的(b)所示，在半导体晶片100的表面FS粘贴支承部件40。支承部件40例如是表面保护片。支承部件40覆盖并保护第2电极30。
如图3的(a)所示，半导体晶片100通过对背面BS侧进行磨削、研磨或蚀刻而被薄层化。半导体晶片100将成为半导体部10的部分保留而被去除。
如图3的(b)所示，在半导体晶片100的背面BS侧例如离子注入作为n型杂质的磷。
如图3的(c)所示，在形成了第3半导体层17后，形成将半导体晶片100的背面BS覆盖的第1电极20。第3半导体层17例如通过使用激光退火法使被离子注入到半导体晶片100的n型杂质活性化而形成。第1电极20例如包含Al、Ni、Ti、Au、Ag、Pt、Cu、Sn中的至少一个元素。
如图4的(a)所示，通过对半导体晶片100的背面BS侧照射激光，由此形成槽CG。槽CG通过将第1电极20选择性地去除并且将半导体晶片100的一部分选择性地去除而形成。槽CG的在半导体晶片100中形成的部分的深度DG(参照图1的(a))例如是数微米。另外，槽CG可以通过用例如等离子蚀刻、RIE(Reactive Ion Etching)、CDE(Chemical Dry Etching)或湿式蚀刻将半导体晶片的背面BS选择性地蚀刻而形成。
槽CG例如形成为在X方向以及Y方向上延伸并交叉成格子状。槽CG例如沿着成为半导体部10的区域的外缘而形成。激光被控制为对相同的位置照射1次或多次。
另外，激光被会聚为规定的光斑直径而照射，因此中心的能量强度高，趋向外侧而强度降低。因此，槽CG形成为具有从其底面朝向上方倾斜的内壁。内壁相对于底面的倾斜角θ例如优选为5度以下，但也可以为其以上。
如图4的(b)所示，在半导体晶片100的背面BS侧粘贴例如切割片50。
图4的(c)示出了粘贴切割片50后的半导体晶片100。表示将图4的(b)的上下颠倒后的构造。
如图5的(a)所示，从半导体晶片100的表面将支承部件40剥离。接下来，如图5的(b)所示，形成与槽CG相连的槽(以下，为切割空间DS)。切割空间DS形成为，其宽度WDS比槽CG的X方向的宽度WCG窄。
切割空间DS例如通过使用切割刀片DB将半导体晶片100切断而形成。为了形成切割空间DS而使用的切割刀片DB的宽度WDB比槽CG的宽度WCG窄。
如图5的(c)所示那样，将半导体晶片100切断，由此能够将半导体装置1芯片化。切割空间DS形成为沿着半导体部10的外缘地在X方向以及Y方向上延伸。
图6的(a)～(c)是表示比较例的半导体装置1的制造过程的示意剖视图。图6的(a)以及(b)是表示使用切割刀片DB将半导体晶片100分割的过程的示意图。图6的(c)是表示使用比较例的制造方法被芯片化后的半导体装置1的剖视图。
如图6的(a)所示，在本例子中，在半导体晶片100的背面BS未形成槽CG。因此，第1电极20也通过切割刀片DB被分割。
如图6的(b)所示，使切割刀片DB旋转，同时使半导体晶片100在例如Y方向上移动。此时，在半导体晶片100的背面侧，产生沿着切割刀片DB的外缘被磨削得较薄的部分TP，并朝向切割片50被推压。因此，容易产生所谓的崩裂或裂纹。
作为结果，如图6的(c)所示，半导体装置1有时在背面侧包含裂纹DC。另外，第1电极20例如有时被切断为包含毛刺20f。毛刺20f例如是在第1电极20的切断时由于切割刀片DB的卷入而产生的。
这样的缺陷例如使半导体装置1的强度降低，成为芯片破损等的故障的一个原因。另外，第1电极20的毛刺20f在芯片接合时，使焊料中产生气泡，成为空隙的主要原因。另外，若从半导体装置1剥去，则也可能成为使制造环境的洁净度降低的粉尘。
在本实施方式的制造方法中，通过在半导体晶片100的背面侧形成槽CG，能够消除被磨削得较薄的部分TP，防止崩裂或裂纹。另外，不用切割刀片DB将第1电极20切断，所以也不会产生毛刺20f。
接下来，参照图7的(a)～(c)，对实施方式的变形例的制造方法进行说明。图7的(a)～(c)是表示实施方式的变形例的半导体装置的制造过程的示意剖视图。
如图7的(a)所示，在从半导体晶片100的表面将支承部件40剥离后(参照图5的(a))，形成蚀刻掩模55。蚀刻掩模55形成于半导体晶片100的表面上，包括沿着成为半导体部10的区域的外缘的开口DL。
如图7的(b)所示，例如使用干式蚀刻法，将半导体晶片100选择性地去除，形成切割空间DS。切割空间DS形成为与槽CG相连。
如图7的(c)所示，通过将蚀刻掩模55去除，能够获得被芯片化的半导体装置1。
在本例中也是，通过在半导体晶片100的背面侧形成槽CG，第1电极20被选择性地去除。由此，在将半导体晶片100分割时，不需要对第1电极20进行蚀刻，例如，干式蚀刻变得容易。另外，通过在半导体装置1的背面侧形成槽CG，由此例如能够抑制芯片接合时的焊料的爬升。
图8的(a)以及(b)是表示实施方式的变形例的半导体装置2、3的示意剖视图。图8的(a)以及(b)所示的半导体装置2以及3分别是MOSFET以及IGBT(Insulated Gate BipolarTransistor)。半导体装置2以及3具有在半导体部10的背面侧设置的槽CG。
在图8的(a)所示的半导体装置2中，第1电极20例如是漏极电极，第2电极30例如是源极电极。第1半导体层13例如是n型漂移层。第2半导体层15例如是p型扩散层，第3半导体层17是n型漏极层。
半导体装置2中的半导体部10还包括第4半导体层16。第4半导体层16例如是n型源极层，选择性地设置于第2半导体层15与第2电极30之间。第4半导体层16例如包含比第1半导体层13的n型杂质高浓度的n型杂质，并与第2电极30电连接。
半导体装置2还包括控制电极60。控制电极60配置于在半导体部10的表面侧设置的沟槽的内部，位于半导体部10与第2电极30之间。控制电极60通过绝缘膜63从半导体部10电绝缘。另外，控制电极60通过绝缘膜65从第2电极30电绝缘。
在图8的(b)所示的半导体装置3中，第1电极20例如是集电极电极，第2电极30例如是发射极电极。第1半导体层13例如是n型基极层。第2半导体层15例如是p型基极层，第3半导体层19是p型集电极层。
半导体装置3中的半导体部10还包括第4半导体层16。第4半导体层16例如是n型发射极层，选择性地设置于第2半导体层15与第2电极30之间。第4半导体层16例如包含比第1半导体层的n型杂质高浓度的n型杂质，并与第2电极30电连接。
在这些例子中也是，通过在半导体部10的背面侧设置槽CG，能够避免芯片化工序中的崩裂和裂纹的产生。另外，能够防止第1电极20的毛刺20f(参照图6的(c))的产生。
以上，对几个实施例进行了说明，但实施方式并不限定与此。例如，槽CG可以通过将半导体晶片选择性地蚀刻形成以代替通过激光照射形成。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子提示的，无意限定发明的范围。这些新的实施方式能够以其他的各种各样的方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。这些实施方式及其变形，包含在发明的范围及主旨中，并且包含在权利要求书记载的发明及其等同的范围中。

Claims (10)

1.一种半导体装置的制造方法，
该半导体装置包括半导体部、在上述半导体部的背面上设置的第1电极及在上述半导体部的表面上设置的第2电极，该半导体装置的制造方法包括如下工序：
在包含成为上述半导体部的区域的晶片的表面上形成了上述第2电极后，形成将上述晶片的背面覆盖的上述第1电极的工序；
沿着成为上述半导体部的区域的外缘，形成将上述第1电极选择性地去除而成的、而且包含位于上述晶片中的部分的第1槽的工序；以及
沿着上述晶片的上述表面中的成为上述半导体部的区域的外缘，形成与上述第1槽相连的第2槽，将上述晶片分割的工序，
上述第2槽在沿着上述晶片的表面的第1方向上的宽度，形成得比上述第1槽在上述第1方向的宽度窄，
上述第1槽形成为具有向朝向所述晶片内的方向弯曲的内表面，
上述第1槽的位于上述晶片中的部分在上述第1方向上的宽度的二分之一比在与上述晶片的上述背面垂直的第2方向上从上述背面到达上述晶片中的上述第1槽的深度宽。
2.如权利要求1所述的半导体装置的制造方法，其中，
上述第1槽形成为，在沿着上述晶片的上述背面且与上述第1方向交叉的第3方向上延伸，
上述第2槽形成为，沿着上述晶片的上述表面地在上述第1方向以及上述第3方向上延伸。
3.如权利要求1所述的半导体装置的制造方法，其中，
上述第1槽，在上述晶片的上述背面侧，通过用激光照射将上述第1电极以及上述半导体部选择性地去除而形成。
4.如权利要求2所述的半导体装置的制造方法，其中，
上述第1槽，在上述晶片的上述背面侧，通过用激光照射将上述第1电极以及上述半导体部选择性地去除而形成。
5.如权利要求1所述的半导体装置的制造方法，其中，
上述第1槽通过将上述晶片的上述背面选择性地蚀刻而形成。
6.如权利要求2所述的半导体装置的制造方法，其中，
上述第1槽通过将上述晶片的上述背面选择性地蚀刻而形成。
7.如权利要求1～6中任一项所述的半导体装置的制造方法，其中，
上述第2槽通过用切割刀片将上述晶片切断而形成，
上述切割刀片的厚度比上述第1槽的上述宽度薄。
8.如权利要求1～6中任一项所述的半导体装置的制造方法，其中，
上述第2槽通过用干式蚀刻将上述半导体部选择性地去除而形成。
9.一种半导体装置，包括：
半导体部；
在上述半导体部的背面上设置的第1电极；以及
在上述半导体部的表面上设置的第2电极，
上述半导体部具有与上述表面相连的第1侧面和将上述背面与上述第1侧面相连的第2侧面，上述第2侧面向朝向上述半导体部内的方向弯曲且包含相对于上述第1侧面以及上述背面倾斜的部分，
在与上述半导体部的上述背面平行的俯视时的上述第1侧面与上述第1电极之间的第1间隔比在与上述第1侧面平行的俯视时的上述第1侧面与上述背面之间的第2间隔宽。
10.如权利要求9所述的半导体装置，其中，
上述半导体部包括第1导电型的第1半导体层及第2导电型的第2半导体层，
上述第2半导体层位于上述第1半导体层与上述第2电极之间，并与上述第2电极电连接。
CN202010106493.2A 2019-09-04 2020-02-21 半导体装置的制造方法以及半导体装置 Active CN112542382B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-161250 2019-09-04
JP2019161250A JP7339819B2 (ja) 2019-09-04 2019-09-04 半導体装置の製造方法および半導体装置

Publications (2)

Publication Number Publication Date
CN112542382A CN112542382A (zh) 2021-03-23
CN112542382B true CN112542382B (zh) 2024-04-09

Family

ID=74681746

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010106493.2A Active CN112542382B (zh) 2019-09-04 2020-02-21 半导体装置的制造方法以及半导体装置

Country Status (3)

Country Link
US (2) US11342426B2 (zh)
JP (1) JP7339819B2 (zh)
CN (1) CN112542382B (zh)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05166926A (ja) * 1991-12-12 1993-07-02 Hitachi Ltd 半導体基板ダイシング法
JPH06275583A (ja) * 1993-03-24 1994-09-30 Disco Abrasive Syst Ltd 面取り半導体チップ及びその面取り加工方法
JPH09141646A (ja) * 1995-11-21 1997-06-03 Sony Corp 基板加工方法
CN1790704A (zh) * 2004-11-11 2006-06-21 雅马哈株式会社 半导体器件,半导体晶片,芯片尺寸封装及制作和检测方法
CN101015070A (zh) * 2004-08-20 2007-08-08 昭和电工株式会社 制造半导体发光器件的方法以及采用该方法制造的器件
JP2009105211A (ja) * 2007-10-23 2009-05-14 Disco Abrasive Syst Ltd ウエーハの分割方法
JP2015053428A (ja) * 2013-09-09 2015-03-19 住友電気工業株式会社 炭化珪素半導体装置の製造方法
JP2015133460A (ja) * 2014-01-16 2015-07-23 株式会社ディスコ ウェーハの分割方法
WO2018230297A1 (ja) * 2017-06-15 2018-12-20 株式会社デンソー 半導体装置およびその製造方法
US10224307B2 (en) * 2015-07-14 2019-03-05 Goertek, Inc. Assembling method, manufacturing method, device and electronic apparatus of flip-die

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3838501A (en) * 1973-02-09 1974-10-01 Honeywell Inf Systems Method in microcircuit package assembly providing nonabrasive, electrically passive edges on integrated circuit chips
JPH05102300A (ja) 1991-10-07 1993-04-23 Mitsubishi Electric Corp 半導体装置
US6271102B1 (en) * 1998-02-27 2001-08-07 International Business Machines Corporation Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
JP2004111606A (ja) 2002-09-18 2004-04-08 Tokyo Seimitsu Co Ltd ウェーハの加工方法
US6998694B2 (en) * 2003-08-05 2006-02-14 Shye-Lin Wu High switching speed two mask Schottky diode with high field breakdown
US7214568B2 (en) * 2004-02-06 2007-05-08 Agere Systems Inc. Semiconductor device configured for reducing post-fabrication damage
JP2006278646A (ja) * 2005-03-29 2006-10-12 Sanyo Electric Co Ltd 半導体装置の製造方法
JP5166926B2 (ja) 2008-03-13 2013-03-21 株式会社大和証券グループ本社 有価証券売買処理システムおよびその方法、並びにプログラム
JP2012054378A (ja) * 2010-09-01 2012-03-15 Renesas Electronics Corp 半導体装置
WO2012099080A1 (ja) * 2011-01-18 2012-07-26 富士電機株式会社 逆阻止型半導体素子の製造方法
EP2530709B1 (en) * 2011-06-03 2015-09-09 Nxp B.V. Method of producing a semiconductor wafer
JP5995435B2 (ja) * 2011-08-02 2016-09-21 ローム株式会社 半導体装置およびその製造方法
DE102011112659B4 (de) * 2011-09-06 2022-01-27 Vishay Semiconductor Gmbh Oberflächenmontierbares elektronisches Bauelement
US8895363B2 (en) * 2013-03-15 2014-11-25 Nxp B.V. Die preparation for wafer-level chip scale package (WLCSP)
US9704718B2 (en) * 2013-03-22 2017-07-11 Infineon Technologies Austria Ag Method for manufacturing a silicon carbide device and a silicon carbide device
US9362366B2 (en) * 2013-05-13 2016-06-07 Panasonic Intellectual Property Management Co., Ltd. Semiconductor element, semiconductor element manufacturing method, semiconductor module, semiconductor module manufacturing method, and semiconductor package
US20160148842A1 (en) * 2014-11-24 2016-05-26 Nxp B.V. Dicing of low-k wafers
US9711463B2 (en) * 2015-01-14 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Dicing method for power transistors
US9466585B1 (en) * 2015-03-21 2016-10-11 Nxp B.V. Reducing defects in wafer level chip scale package (WLCSP) devices
US20170084490A1 (en) * 2015-09-18 2017-03-23 Stmicroelectronics, Inc. Method for making ic with stepped sidewall and related ic devices
JP6546507B2 (ja) * 2015-10-26 2019-07-17 株式会社ディスコ デバイスの製造方法
JP2017162876A (ja) * 2016-03-07 2017-09-14 株式会社ジェイデバイス 半導体パッケージの製造方法
JP2017199834A (ja) * 2016-04-28 2017-11-02 株式会社ジェイデバイス 半導体パッケージ及び半導体パッケージの製造方法
US10535588B2 (en) * 2017-01-18 2020-01-14 Stmicroelectronics, Inc. Die with metallized sidewall and method of manufacturing
US10403506B2 (en) * 2018-01-07 2019-09-03 Infineon Technologies Ag Separation of workpiece with three material removal stages

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05166926A (ja) * 1991-12-12 1993-07-02 Hitachi Ltd 半導体基板ダイシング法
JPH06275583A (ja) * 1993-03-24 1994-09-30 Disco Abrasive Syst Ltd 面取り半導体チップ及びその面取り加工方法
JPH09141646A (ja) * 1995-11-21 1997-06-03 Sony Corp 基板加工方法
CN101015070A (zh) * 2004-08-20 2007-08-08 昭和电工株式会社 制造半导体发光器件的方法以及采用该方法制造的器件
CN1790704A (zh) * 2004-11-11 2006-06-21 雅马哈株式会社 半导体器件,半导体晶片,芯片尺寸封装及制作和检测方法
JP2009105211A (ja) * 2007-10-23 2009-05-14 Disco Abrasive Syst Ltd ウエーハの分割方法
JP2015053428A (ja) * 2013-09-09 2015-03-19 住友電気工業株式会社 炭化珪素半導体装置の製造方法
JP2015133460A (ja) * 2014-01-16 2015-07-23 株式会社ディスコ ウェーハの分割方法
US10224307B2 (en) * 2015-07-14 2019-03-05 Goertek, Inc. Assembling method, manufacturing method, device and electronic apparatus of flip-die
WO2018230297A1 (ja) * 2017-06-15 2018-12-20 株式会社デンソー 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US20220246734A1 (en) 2022-08-04
JP7339819B2 (ja) 2023-09-06
US11887858B2 (en) 2024-01-30
US11342426B2 (en) 2022-05-24
US20210066130A1 (en) 2021-03-04
CN112542382A (zh) 2021-03-23
JP2021040068A (ja) 2021-03-11

Similar Documents

Publication Publication Date Title
US8877611B2 (en) Devices with crack stops
US9716027B2 (en) Method for manufacturing semiconductor device
JP5740820B2 (ja) 半導体装置および半導体装置の製造方法
US8148240B2 (en) Method of manufacturing semiconductor chips
KR102643785B1 (ko) 자기 정렬된 후면 도전층을 포함하는 반도체 칩 및 이의 제조 방법
JP2010016188A (ja) 半導体装置の製造方法および半導体装置
TW201737331A (zh) 半導體裝置及其製造方法
CN107068564B (zh) 形成半导体器件的方法
JP5839768B2 (ja) 半導体装置の製造方法
US10559664B2 (en) Method of manufacturing semiconductor device by removing a bulk layer to expose an epitaxial-growth layer and by removing portions of a supporting-substrate to expose portions of the epitaxial-growth layer
US11387326B2 (en) Silicon carbide semiconductor device and method for manufacturing the same
CN112542382B (zh) 半导体装置的制造方法以及半导体装置
JP2016096212A (ja) 半導体装置、および、半導体装置の製造方法
JPWO2015194590A1 (ja) 半導体装置および半導体装置の製造方法
US8728923B2 (en) Manufacturing method of semiconductor device
CN110197815B (zh) 半导体装置以及切割方法
JP6429168B2 (ja) パワー半導体装置及びパワー半導体装置の製造方法
JP2004327708A (ja) 半導体装置およびその製造方法
US20210090903A1 (en) Method for manufacturing semiconductor device
US10636708B2 (en) Method of manufacturing semiconductor device
JP2016058610A (ja) 半導体装置およびその製造方法
JP2017069269A (ja) 半導体装置および半導体装置の製造方法
CN113451247A (zh) 半导体装置
JP2011054914A (ja) 半導体装置の製造方法および半導体ウエハ
JP2013149804A (ja) 半導体装置の製造方法及び半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant