JP7304936B2 - スルーシリコンビアを含む3次元回路の積層 - Google Patents
スルーシリコンビアを含む3次元回路の積層 Download PDFInfo
- Publication number
- JP7304936B2 JP7304936B2 JP2021507075A JP2021507075A JP7304936B2 JP 7304936 B2 JP7304936 B2 JP 7304936B2 JP 2021507075 A JP2021507075 A JP 2021507075A JP 2021507075 A JP2021507075 A JP 2021507075A JP 7304936 B2 JP7304936 B2 JP 7304936B2
- Authority
- JP
- Japan
- Prior art keywords
- die
- silicon
- silicon substrate
- electrical components
- assembly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910052710 silicon Inorganic materials 0.000 title claims description 196
- 239000010703 silicon Substances 0.000 title claims description 196
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 181
- 239000000758 substrate Substances 0.000 claims description 117
- 238000000034 method Methods 0.000 claims description 39
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 description 5
- 238000000429 assembly Methods 0.000 description 3
- 230000000712 assembly Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
- H01L2224/80012—Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
- H01L2224/80013—Plasma cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80053—Bonding environment
- H01L2224/80095—Temperature settings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12043—Photo diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1425—Converter
- H01L2924/14253—Digital-to-analog converter [DAC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1426—Driver
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Led Device Packages (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
複数のスルーシリコンビアをシリコン基板中に形成することと、
シリコン基板を第1のダイ上に取り付けることであって、スルーシリコンビアの少なくとも一部が第1のダイに電気的に接続される、シリコン基板を取り付けることと、
シリコン基板および第1のダイをフェースツーフェース接合を通して第2のダイ上に取り付けることであって、第1のダイが第2のダイに電気的に接続される、シリコン基板および第1のダイを取り付けることと、
第2のダイが第1のダイおよびシリコン基板上に取り付けられた後に、スルーシリコンビアを露出させることと
を含み得、
シリコン基板が、露出させることの前に、キャリア基板として機能するように構成される。
第1のダイおよび第2のダイを取り付けられたシリコン基板をプリント回路板上に取り付けることであって、第2のダイがプリント回路板に電気的に接続される、シリコン基板を取り付けること
をさらに含み得る。
スルーシリコンビアが露出された後に、1つまたは複数の電気的構成要素をシリコン基板上に取り付けることであって、電気的構成要素がスルーシリコンビアを通して第1のダイに電気的に接続される、1つまたは複数の電気的構成要素を取り付けること
をさらに含み得る。
スルーシリコンビアを伴って形成されたシリコン基板と、
接合によってシリコン基板に取り付けられた第1のダイであって、第1のダイの電極がスルーシリコンビアに電気的に接続される、第1のダイと、
フェースツーフェース接合によって第1のダイに取り付けられた第2のダイであって、第2のダイの電極が第1のダイの電極に電気的に接続される、第2のダイと
を備え、
シリコン基板が、露出させることの前に、キャリア基板として機能するように構成される。
Claims (19)
- 積層回路ダイのアセンブリを作製するための方法であって、
複数のスルーシリコンビアをシリコン基板中に形成することと、
前記シリコン基板を第1のダイ上に取り付けることであって、前記スルーシリコンビアの少なくとも一部が前記第1のダイに電気的に接続される、前記シリコン基板を取り付けることと、
前記シリコン基板および前記第1のダイをフェースツーフェース接合を通して第2のダイ上に取り付けることであって、前記第1のダイが前記第2のダイに電気的に接続される、前記シリコン基板および前記第1のダイを取り付けることと、
前記第2のダイが前記第1のダイおよび前記シリコン基板上に取り付けられた後に、前記スルーシリコンビアを露出させることと
を含み、
前記シリコン基板が、前記露出させることの前に、キャリア基板として機能するように構成された、
方法。 - 前記スルーシリコンビアの数が、10,000から500,000までの範囲内にある、請求項1に記載の方法。
- 前記スルーシリコンビアが、1から50マイクロメートルまでの範囲内のピッチを有する、請求項1に記載の方法。
- 前記第1のダイおよび前記第2のダイを取り付けられた前記シリコン基板をプリント回路板上に取り付けることであって、前記第2のダイが前記プリント回路板に電気的に接続される、前記シリコン基板を取り付けること
をさらに含む、請求項1に記載の方法。 - 前記スルーシリコンビアが露出された後に、1つまたは複数の電気的構成要素を前記シリコン基板上に取り付けることであって、前記電気的構成要素が前記スルーシリコンビアを通して前記第1のダイに電気的に接続される、1つまたは複数の電気的構成要素を取り付けること
をさらに含む、請求項1に記載の方法。 - 前記1つまたは複数の電気的構成要素が、マイクロ発光ダイオードまたはフォトダイオードのアレイを含む、請求項5に記載の方法。
- 前記第1のダイが、前記1つまたは複数の電気的構成要素に駆動電流を提供するように構成された駆動回路を備える、請求項5に記載の方法。
- 前記第2のダイが、前記1つまたは複数の電気的構成要素を動作させるためにデジタル信号をアナログ信号に変換するように構成されたデジタル回路を備える、請求項5に記載の方法。
- 前記シリコン基板が、前記電気的構成要素の動作から生成された熱を発散するように構成された金属要素を備える、請求項5に記載の方法。
- 前記スルーシリコンビアが、前記シリコン基板のエッジにおいて形成される、請求項1に記載の方法。
- 積層回路ダイのアセンブリであって、
スルーシリコンビアを伴って形成されたシリコン基板と、
接合によって前記シリコン基板に取り付けられた第1のダイであって、前記第1のダイの電極が前記スルーシリコンビアに電気的に接続される、第1のダイと、
フェースツーフェース接合によって前記第1のダイに取り付けられた第2のダイであって、前記第2のダイの電極が前記第1のダイの前記電極に電気的に接続される、第2のダイと
を備え、
前記シリコン基板が、露出させることの前に、キャリア基板として機能するように構成され、
前記スルーシリコンビアの数が、10,000から500,000までの範囲内にある、アセンブリ。 - 前記スルーシリコンビアが、1から50マイクロメートルまでの範囲内のピッチを有する、請求項11に記載のアセンブリ。
- 前記第1のダイおよび前記第2のダイを取り付けられた前記シリコン基板がその上に取り付けられた、プリント回路板をさらに備え、前記第2のダイが前記プリント回路板に電気的に接続される、請求項11に記載のアセンブリ。
- 前記スルーシリコンビアが露出された後に前記シリコン基板上に取り付けられた、1つまたは複数の電気的構成要素をさらに備え、前記電気的構成要素が前記スルーシリコンビアを通して前記第1のダイに電気的に接続される、請求項11に記載のアセンブリ。
- 前記1つまたは複数の電気的構成要素が、マイクロ発光ダイオードまたはフォトダイオードのアレイを含む、請求項14に記載のアセンブリ。
- 前記第1のダイが、前記1つまたは複数の電気的構成要素に駆動電流を提供するように構成された駆動回路を備える、請求項14に記載のアセンブリ。
- 前記第2のダイが、前記1つまたは複数の電気的構成要素を動作させるためにデジタル信号をアナログ信号に変換するように構成されたデジタル回路を備える、請求項14に記載のアセンブリ。
- 前記シリコン基板が、前記電気的構成要素の動作から生成された熱を発散するように構成された金属要素を備える、請求項14に記載のアセンブリ。
- 前記スルーシリコンビアが、前記シリコン基板のエッジにおいて形成される、請求項11に記載のアセンブリ。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862734700P | 2018-09-21 | 2018-09-21 | |
US62/734,700 | 2018-09-21 | ||
US16/222,460 | 2018-12-17 | ||
US16/222,460 US10700041B2 (en) | 2018-09-21 | 2018-12-17 | Stacking of three-dimensional circuits including through-silicon-vias |
PCT/US2018/066414 WO2020060578A1 (en) | 2018-09-21 | 2018-12-19 | Stacking of three-dimensional circuits including through-silicon-vias |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2022510747A JP2022510747A (ja) | 2022-01-28 |
JP7304936B2 true JP7304936B2 (ja) | 2023-07-07 |
Family
ID=69883596
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021507075A Active JP7304936B2 (ja) | 2018-09-21 | 2018-12-19 | スルーシリコンビアを含む3次元回路の積層 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10700041B2 (ja) |
EP (1) | EP3853892A4 (ja) |
JP (1) | JP7304936B2 (ja) |
KR (1) | KR20210049906A (ja) |
CN (1) | CN112714952A (ja) |
WO (1) | WO2020060578A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11373991B2 (en) * | 2020-02-06 | 2022-06-28 | Lumileds Llc | Methods of manufacturing light-emitting devices with metal inlays and bottom contacts |
US11575074B2 (en) | 2020-07-21 | 2023-02-07 | Lumileds Llc | Light-emitting device with metal inlay and top contacts |
JP7510820B2 (ja) | 2020-08-31 | 2024-07-04 | シャープ福山レーザー株式会社 | 画像表示素子 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010245288A (ja) | 2009-04-06 | 2010-10-28 | Canon Inc | 半導体装置の製造方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8334170B2 (en) * | 2008-06-27 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for stacking devices |
CN102379037B (zh) * | 2009-03-30 | 2015-08-19 | 高通股份有限公司 | 使用顶部后钝化技术和底部结构技术的集成电路芯片 |
US9236341B1 (en) * | 2010-08-25 | 2016-01-12 | Xilinix, Inc. | Through-silicon vias with metal system fill |
US8236584B1 (en) * | 2011-02-11 | 2012-08-07 | Tsmc Solid State Lighting Ltd. | Method of forming a light emitting diode emitter substrate with highly reflective metal bonding |
US8653542B2 (en) * | 2011-01-13 | 2014-02-18 | Tsmc Solid State Lighting Ltd. | Micro-interconnects for light-emitting diodes |
US8560982B2 (en) * | 2011-06-27 | 2013-10-15 | Xilinx, Inc. | Integrated circuit design using through silicon vias |
KR20130044052A (ko) * | 2011-10-21 | 2013-05-02 | 에스케이하이닉스 주식회사 | 적층 반도체 패키지 |
JP2013110151A (ja) | 2011-11-17 | 2013-06-06 | Elpida Memory Inc | 半導体チップ及び半導体装置 |
JP5925006B2 (ja) * | 2012-03-26 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
TWI506712B (zh) * | 2012-10-25 | 2015-11-01 | 矽品精密工業股份有限公司 | 半導體結構之測試方法 |
US20140327132A1 (en) | 2013-05-03 | 2014-11-06 | National Center For Advanced Packaging (Ncap China) | TSV Backside Reveal Structure and Exposing Process |
US9184139B2 (en) | 2013-12-17 | 2015-11-10 | Stats Chippac, Ltd. | Semiconductor device and method of reducing warpage using a silicon to encapsulant ratio |
US9543229B2 (en) * | 2013-12-27 | 2017-01-10 | International Business Machines Corporation | Combination of TSV and back side wiring in 3D integration |
KR102258739B1 (ko) * | 2014-03-26 | 2021-06-02 | 삼성전자주식회사 | 하이브리드 적층 구조를 갖는 반도체 소자 및 그 제조방법 |
KR102258743B1 (ko) * | 2014-04-30 | 2021-06-02 | 삼성전자주식회사 | 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치 |
US9666520B2 (en) * | 2014-04-30 | 2017-05-30 | Taiwan Semiconductor Manufactuing Company, Ltd. | 3D stacked-chip package |
KR102352677B1 (ko) | 2014-08-27 | 2022-01-17 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US20160343719A1 (en) * | 2015-05-22 | 2016-11-24 | Globalfoundries Singapore Pte. Ltd. | Interposers for integrated circuits with one-time programming and methods for manufacturing the same |
US9806128B2 (en) * | 2015-05-22 | 2017-10-31 | Globalfoundries Singapore Pte. Ltd. | Interposers for integrated circuits with multiple-time programming and methods for manufacturing the same |
JP6531603B2 (ja) | 2015-10-01 | 2019-06-19 | 富士通株式会社 | 電子部品、電子装置及び電子装置の製造方法 |
US9818726B2 (en) * | 2015-12-28 | 2017-11-14 | International Business Machines Corporation | Chip stack cooling structure |
US9704830B1 (en) * | 2016-01-13 | 2017-07-11 | International Business Machines Corporation | Semiconductor structure and method of making |
US11189573B2 (en) * | 2016-03-31 | 2021-11-30 | Intel Corporation | Semiconductor package with electromagnetic interference shielding using metal layers and vias |
US10833052B2 (en) * | 2016-10-06 | 2020-11-10 | Micron Technology, Inc. | Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods |
US10763290B2 (en) * | 2017-02-22 | 2020-09-01 | Elwha Llc | Lidar scanning system |
-
2018
- 2018-12-17 US US16/222,460 patent/US10700041B2/en active Active
- 2018-12-19 CN CN201880097740.8A patent/CN112714952A/zh active Pending
- 2018-12-19 WO PCT/US2018/066414 patent/WO2020060578A1/en unknown
- 2018-12-19 EP EP18933878.3A patent/EP3853892A4/en not_active Withdrawn
- 2018-12-19 KR KR1020217009537A patent/KR20210049906A/ko not_active Application Discontinuation
- 2018-12-19 JP JP2021507075A patent/JP7304936B2/ja active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010245288A (ja) | 2009-04-06 | 2010-10-28 | Canon Inc | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2022510747A (ja) | 2022-01-28 |
KR20210049906A (ko) | 2021-05-06 |
EP3853892A4 (en) | 2021-11-17 |
EP3853892A1 (en) | 2021-07-28 |
US10700041B2 (en) | 2020-06-30 |
CN112714952A (zh) | 2021-04-27 |
WO2020060578A1 (en) | 2020-03-26 |
US20200098729A1 (en) | 2020-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI546915B (zh) | 多重中介層基板電路組件以及其製造方法 | |
JP7304936B2 (ja) | スルーシリコンビアを含む3次元回路の積層 | |
US7646086B2 (en) | Semiconductor package | |
CN111357102A (zh) | 用于多芯片模块的非嵌入式硅桥芯片 | |
TWI694612B (zh) | 半導體模組 | |
TW201921625A (zh) | 具有橫向偏移堆疊之半導體晶粒之半導體裝置 | |
JP2008546174A5 (ja) | ||
TW201742223A (zh) | 半導體封裝 | |
WO2010035376A1 (ja) | 半導体装置の製造方法 | |
US10297552B2 (en) | Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects | |
US9257355B2 (en) | Method for embedding a chipset having an intermediary interposer in high density electronic modules | |
KR20070092120A (ko) | 반도체 장치 및 그 제조 방법 | |
US10546987B2 (en) | Method for producing a component, and a component | |
EP3104410B1 (en) | Multi-chip module, on-board computer, sensor interface substrate, and multi-chip module manufacturing method | |
KR20150033937A (ko) | 반도체 패키지 및 그 제작 방법 | |
JP2002270720A (ja) | 半導体装置およびその製造方法 | |
CN102881666B (zh) | 晶圆级器件封装 | |
CN113299632A (zh) | 具有镜像电路的堆叠式晶粒的集成电路器件 | |
JP2021530098A (ja) | 半導体チップ積層配置、およびそのような半導体チップ積層配置を製造するための半導体チップ | |
JP2004134480A (ja) | 半導体装置及びその製造方法 | |
JP4334397B2 (ja) | 半導体装置及びその製造方法 | |
CN112151457A (zh) | 封装结构及其制作方法和电子设备 | |
US10680033B2 (en) | Chip packaging method and chip package | |
CN109243981B (zh) | 封装结构及其制造方法 | |
JP5555400B2 (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210922 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20221013 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20221101 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20230201 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20230530 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20230627 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7304936 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |