CN112714952A - 包括贯穿硅通孔的三维电路的堆叠 - Google Patents

包括贯穿硅通孔的三维电路的堆叠 Download PDF

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CN112714952A
CN112714952A CN201880097740.8A CN201880097740A CN112714952A CN 112714952 A CN112714952 A CN 112714952A CN 201880097740 A CN201880097740 A CN 201880097740A CN 112714952 A CN112714952 A CN 112714952A
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die
silicon
silicon substrate
assembly
electrical components
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拉金德拉·D·潘西
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Meta Platforms Technologies LLC
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Facebook Technologies LLC
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Abstract

通过氧化物‑氧化物键合堆叠电路管芯的组件。该组件包括硅衬底，在该硅衬底中形成多个贯穿硅通孔。硅衬底通过电介质‑电介质键合附接到管芯上，贯穿硅通孔的至少一部分电连接到管芯。硅衬底和管芯通过氧化物‑氧化物键合附接到另一个管芯上。然后显露贯穿硅通孔。硅衬底在显露之前用作载体衬底。硅衬底和两个管芯可以附接到印刷电路板，印刷电路板电连接到两个管芯。一个或更多个电气部件可以附接到硅衬底上，并通过贯穿硅通孔电连接到管芯。硅衬底可以包括用于扩散由一个或更多个电气部件的操作产生的热量的金属元件。

Description

包括贯穿硅通孔的三维电路的堆叠
背景
公开的领域
本公开总体涉及三维(3D)电路的堆叠，并且具体涉及堆叠包括形成在无源层中的贯穿硅通孔(through-silicon-vias)的电路管芯(die)。
相关技术的描述
3D集成电路可以包括堆叠在一起并通过使用贯穿硅通孔互连的多个电路管芯。与传统的二维工艺相比，3D集成电路可以以更低的功率和更小的占用面积实现性能改善。然而，目前用于堆叠3D电路管芯的现有方法在面对背(face-to-back)配置方面存在限制。例如，它们不能在功能电路上集成高密度功能模块。它们也不能在不损失有源电路面积的情况下提供大量贯穿硅通孔互连。此外，当前存在的方法使用临时载体，并且在临时载体和管芯之间的表面键合方面存在挑战。当前现有方法中的这些缺陷禁止在3D电路管芯中集成高密度电子部件。
概述
实施例涉及制造堆叠电路管芯的组件。在硅衬底中形成多个贯穿硅通孔。硅衬底可以用作堆叠电路管芯的永久载体。硅衬底通过电介质-电介质键合(dielectric-to-dielectric bonding)附接到第一管芯上。部分或全部贯穿硅通孔电连接到第一管芯。硅衬底和第一管芯通过面对面键合(face-to-face bonding)附接到第二管芯上。第一管芯电连接到第二管芯。硅衬底可以被减薄以显露贯穿硅通孔。贯穿硅通孔在附接在硅衬底上的电气部件和第一管芯之间提供电连接。
在一些实施例中，在显露贯穿硅通孔之后，将微型发光二极管(LED)阵列附接到硅衬底上。微型LED通过贯穿硅通孔电连接到第一管芯。第一管芯可以包括提供电流来驱动微型LED的驱动电路。第二管芯可以包括将数字信号转换成模拟信号以操作微型LED的数字电路。此外，硅衬底可以包括金属元件，该金属元件耗散由微型LED的操作产生的热量。
根据本发明的实施例在所附权利要求中具体公开，该权利要求涉及堆叠电路管芯的方法和组件，其中在一个权利要求类别(例如方法)中提到的任何特征，也可以在例如组件、系统、存储介质和计算机程序产品的另一个权利要求类别中要求保护。所附权利要求中的从属关系或往回引用仅出于形式原因而选择。然而，也可以要求保护由对任何前面权利要求的有意往回引用(特别是多项引用)而产生的任何主题，使得权利要求及其特征的任何组合被公开并可被要求保护，而不考虑在所附权利要求中选择的从属性。可以被要求保护的主题不仅包括如在所附权利要求中阐述的特征的组合，而且还包括在权利要求中的特征的任何其他组合，其中，在权利要求中提到的每个特征可以与在权利要求中的任何其他特征或其他特征的组合相结合。此外，本文描述或描绘的实施例和特征中的任一个可以在单独的权利要求中和/或以与本文描述或描绘的任何实施例或特征的任何组合或以与所附权利要求的任何特征的任何组合被要求保护。
在一个实施例中，一种用于制造堆叠电路管芯组件的方法可以包括：
在硅衬底中形成多个贯穿硅通孔；
将硅衬底附接到第一管芯上，其中贯穿硅通孔的至少一部分电连接到第一管芯；
通过面对面键合将硅衬底和第一管芯附接到第二管芯上，其中第一管芯电连接到第二管芯；和
在第二管芯附接到第一管芯和硅衬底上之后，显露贯穿硅通孔，
其中所述硅衬底被配置成在显露之前用作载体衬底。
贯穿硅通孔的数量可以在10000到500000的范围内。
贯穿硅通孔的间距可以在1至50微米的范围内。
在一个实施例中，一种方法可以包括：
将附接有第一管芯和第二管芯的硅衬底附接在印刷电路板上，其中第二管芯电连接到印刷电路板。
在一个实施例中，一种方法可以包括：
在显露贯穿硅通孔之后，将一个或更多个电气部件附接到硅衬底上，其中电气部件通过贯穿硅通孔电连接到第一管芯。
一个或更多个电气部件可以包括微型发光二极管或光电二极管的阵列。
第一管芯可以包括被配置为向一个或更多个电气部件提供驱动电流的驱动电路。
第二管芯可以包括数字电路，该数字电路被配置成将数字信号转换成用于操作所述一个或更多个电气部件的模拟信号。
硅衬底可以包括金属元件，该金属元件被配置为扩散由电气部件的操作产生的热量。
贯穿硅通孔可以形成在硅衬底的边缘。
在一个实施例中，堆叠电路管芯的组件可以包括：
形成有贯穿硅通孔的硅衬底；
第一管芯，其通过键合附接到硅衬底，其中第一管芯的电极电连接到贯穿硅通孔；和
第二管芯，其通过面对面键合附接到第一管芯，其中第二管芯的电极电连接到第一管芯的电极，
其中所述硅衬底被配置成在显露之前用作载体衬底。
贯穿硅通孔的数量可以在10000至500000的范围内。
贯穿硅通孔的间距可以在1至50微米的范围内。
在一个实施例中，组件可以包括印刷电路板，其上附接有与第一管芯和第二管芯附接的硅衬底，第二管芯可以电连接到印刷电路板。
在一个实施例中，组件可以包括在显露贯穿硅通孔之后附接在硅衬底上的一个或更多个电气部件，电气部件可以通过贯穿硅通孔电连接到第一管芯。
一个或更多个电气部件可以包括微型发光二极管或光电二极管的阵列。
第一管芯可以包括被配置为向一个或更多个电气部件提供驱动电流的驱动电路。
第二管芯可以包括数字电路，该数字电路被配置成将数字信号转换成用于操作所述一个或更多个电气部件的模拟信号。
硅衬底可以包括金属元件，该金属元件被配置为扩散由电气部件的操作产生的热量。
贯穿硅通孔可以形成在硅衬底的边缘。
在根据本发明的实施例中，一个或更多个计算机可读非暂时性存储介质可以包含软件，该软件在被执行时可操作来执行根据本发明或任何上述实施例的方法，特别是在制造或组装过程或系统中执行所述方法。
在根据本发明的实施例中，系统可以包括：一个或更多个处理器；以及至少一个耦合到处理器并包括可由处理器执行的指令的存储器，处理器在执行指令时可操作来执行根据本发明或任何上述实施例的方法，特别是在制造或组装过程或系统中执行所述方法。
在根据本发明的实施例中，优选地包括计算机可读非暂时性存储介质的计算机程序产品，当在数据处理系统上执行时可操作来执行根据本发明或任何上述实施例的方法，尤其是在制造或组装过程或系统中执行所述方法。
附图简述
通过结合附图考虑以下详细描述，可以容易地理解实施例的教导。
图1A是根据实施例的堆叠电路管芯的组件的示例示意图，其中硅衬底用作载体。
图1B是示出根据实施例的硅衬底的截面图。
图2A-2D示出了根据实施例的堆叠电路管芯组件的形成过程，其中硅衬底用作载体。
图3是示出根据实施例的制造堆叠电路管芯组件的过程的流程图。
附图仅为了说明的目的而描绘各种实施例。
详细描述
在实施例的以下描述中，阐述了许多具体细节，以便提供更透彻的理解。然而，注意的是，实施例可以在没有这些具体细节中的一个或更多个的情况下被实践。在其他实例中，没有详细描述众所周知的特征，以避免不必要地使描述复杂化。
在本文中参考附图描述实施例，在附图中相似的参考数字表示相同或功能相似的元件。另外，在附图中，每个参考数字的最左边的数字对应于第一次使用该参考数字的附图。
实施例涉及通过使用永久载体来制造堆叠电路管芯的组件。该组件包括用作永久载体的硅衬底、第一管芯和第二管芯。硅衬底通过电介质-电介质键合附接到第一管芯上。第二管芯也通过电介质-电介质键合附接到第一管芯和硅衬底上。贯穿硅通孔形成在硅衬底中，并通过减薄硅衬底而显露。多个电气部件附接在硅衬底上，并通过贯穿硅通孔电连接到第一管芯。硅衬底包括金属元件，用于电气布线和/或耗散由电气部件的操作产生的热量。该组件可以附接在印刷电路板上，第二管芯电连接到印刷电路板。
图1A是根据实施例的堆叠电路管芯的组件100的示例示意图。组件100可以包括硅衬底110、第一管芯120和第二管芯130等部件。硅衬底110、第一管芯120和第二管芯130通过电介质-电介质键合140堆叠在一起。在一个实施例中，电介质-电介质键合140是通过使氧化物的顶面与氧化物的底面接触而形成的氧化物-氧化物键合。通过使用氧化物-氧化物键合，组件100可以承受高温。电介质-电介质键合140可以是碳化硅键合或其他类型的键合。硅衬底110具有从5μm到10μm范围内的厚度。在一个实施例中，硅衬底110约5μm厚、3mm宽和6mm长，第一管芯120和第二管芯各约50μm厚、3mm宽和6mm长。在其他实施例中，硅衬底110、第一管芯120和第二管芯130可以具有不同的尺寸。
硅衬底110包括贯穿硅通孔150。在一些实施例中，贯穿硅通孔150可以在硅衬底110与第一管芯120和第二管芯130组装之前或之后形成。贯穿硅通孔150通过减薄硅衬底110以获得具有贯穿硅通孔150的暴露垫片的平坦表面而显露。平坦的表面有利于高密度电气部件(例如传感器、光电二极管、微型LED)的精细间距附接。在一些实施例中，贯穿硅通孔具有从1μm到50μm范围内的间距。硅衬底110可以包括大量贯穿硅通孔150。贯穿硅通孔150的数量可以在10000到500000的范围内。在图1的实施例中，贯穿硅通孔150位于硅衬底110的边缘。在贯穿硅通孔150和硅衬底110的边缘之间有大约0.25mm的间隙。在其他实施例中，贯穿硅通孔150可以位于硅衬底110的其他区域中。
在图1A的实施例中，微型LED阵列160附接在硅衬底110上，并电连接到贯穿硅通孔150。在其他实施例中，贯穿硅通孔150可以连接到不同的器件(例如，多个微型LED)。微型LED阵列110包括多个微型LED。这些微型LED可用于头戴式设备、电话或其他类型的电子设备中的显示元件，以体现一个或更多个像素。
至少一些贯穿硅通孔150电连接到第一管芯120。第一管芯120例如通过第一管芯120中的通孔170和电极175电连接到第二管芯130。在一个实施例中，第一管芯120包括大约5000个具有大约75μm间距的通孔。因此，利用贯穿硅通孔150，微型LED阵列160电连接到第一管芯120和第二管芯130。
在图1A的实施例中，组件100附接在印刷电路板180上，第二管芯130通过第二管芯130中的通孔170和电极175电(和/或数字)连接到印刷电路板180。在第二管芯中可以有大约500个通孔170，其具有至少125μm的间距。在一些实施例中，印刷电路板180包括向第二管芯130提供数字信号的电路。第二管芯130可以包括将从印刷电路板180接收的数字信号转换成模拟信号以操作微型LED阵列160的电路。第一管芯120接收由第二管芯130产生的模拟信号，并基于该模拟信号向微型LED阵列160提供驱动电流。在一个实施例中，第一管芯120包括驱动电路，该驱动电路单独驱动微型LED阵列160中的每个微型LED，使得每个微型LED可以具有不同的亮度和/或颜色。
在图1A的实施例中，贯穿硅通孔150形成在硅衬底110(其可以是无源层并且不包括有源电路部件)中，而不是形成在第一管芯120或第二管芯130(其可以是形成电路部件的有源电路区域)中。因此，该实施例消除了在有源电路区域中形成大量高密度贯穿硅通孔的需要，因此避免了有源电路区域的损失。此外，硅衬底110用作永久载体，这消除了使用临时载体的需要。组件形成后，不需要移除永久载体。此外，将第一管芯120附接到硅衬底110上的过程比将第一管芯120附接到临时载体上更容易，临时载体对键合表面的平整度有很高的要求。
图1B是示出根据实施例的硅衬底110的截面图。除了贯穿硅通孔150之外，多个金属元件190布置在硅衬底110中。金属元件190可以是嵌入硅衬底110中的一块铜、金或其他类型的金属。图1B示出了具有矩形形状的七个金属元件190。在其他实施例中，硅衬底110可以包括不同数量的具有各种形状的金属元件190。此外，金属元件190可以占据上至90％的横截面面积。金属元件190可以耗散由微型LED阵列160和/或其他电气部件的操作产生的热量。金属元件190也可以嵌入硅衬底110中用于电气布线。在一些实施例中，金属元件190是虚设的填充物(dummy fill)，并且不电连接到贯穿硅通孔150。
图2A-2D示出了根据实施例的通过使用永久载体形成堆叠电路管芯的组件的过程。图2A示出了硅衬底210，其中形成了多个贯穿硅通孔220。硅衬底210的厚度大于贯穿硅通孔220的高度，使得贯穿硅通孔220不显露。在一个实施例中，贯穿硅通孔220的高度在从5μm到10μm的范围内。贯穿硅通孔150形成高密度电互连。硅衬底210可以用作载体衬底，该载体衬底可以用作将多个集成电路堆叠在一个封装中的机械基底。除了贯穿硅通孔220之外，金属元件(图2A中未示出)嵌入硅衬底中以促进散热。图2A还示出了具有电极240的第一管芯230。第一管芯230包括硅晶片250。图2A还示出了具有电极270的第二管芯260。第二管芯包括硅晶片280。
在图2B中，硅衬底210附接到第一管芯230上，其中贯穿硅通孔220的至少一部分电连接到第一管芯230的电极240。研磨掉第一管芯230的硅晶片250，以显露第一管芯230中的通孔。例如，通过在硅衬底210和第一管芯230的表面上执行表面处理(例如，通过化学机械平坦化或等离子体处理)，邻接硅衬底210和第一管芯230的经处理的表面，以在经处理的表面之间形成范德瓦尔斯键合，然后在200℃至250℃的温度范围内对该表面退火，在硅衬底210和第一管芯230之间形成氧化物-氧化物键合235的层。氧化物-氧化物键合235避免了使用不能承受高温的粘性聚合物。替代氧化物-氧化物键合235，可以在硅衬底210和第一管芯230之间形成电介质-电介质键合层。
在图2C中，硅衬底210和第一管芯230被附接到第二管芯260上。第一管芯230和第二管芯260之间的键合是面对面键合。因为硅衬底210用作载体衬底，所以第一管芯230和第二管芯260不必太薄以利于面对面键合。研磨掉第二管芯260的硅晶片280，以显露第二管芯260中的通孔。在第一管芯230和第二管芯260之间有氧化物-氧化物键合层。氧化物-氧化物键合可以例如使用与上述硅衬底210和第一管芯230相同的工艺来获得。此外，第一管芯230电连接到第二管芯260。替代氧化物-氧化物键合265，可以在第一管芯230和第二管芯260之间形成电介质-电介质键合层。
在图2D中，减薄硅衬底210以显露贯穿硅通孔220。在一个实施例中，硅衬底210通过干法蚀刻或湿法蚀刻减薄。在另一实施例中，硅衬底210通过机械抛光、化学抛光或两者的组合减薄。硅衬底210的厚度减小到等于或小于贯穿硅通孔220的高度。结果，贯穿硅通孔220穿过硅衬底210，以建立从硅衬底210面向第一管芯230的一侧到硅衬底210的相对侧的电连接。此外，因为贯穿硅通孔220形成在硅衬底(其为无源层)中，所以避免或减少了第一管芯230和第二管芯260中有源电路区域的损失。在图2A-2D的实施例中，在硅衬底210附接到第一管芯230和第二管芯260之前，贯穿硅通孔220形成在硅衬底210中。在一些实施例中，贯穿硅通孔220在硅衬底210附接到第一管芯230上之后，但是在硅衬底210和第一管芯230附接到第二管芯260上之前形成。在一些其他实施例中，在硅衬底210附接到第一管芯230和第二管芯260之后，可以在硅衬底210中形成贯穿硅通孔220。
图3是示出根据实施例的制造堆叠电路管芯组件的过程的流程图。过程可以在一些实施例中包括与结合图3所描述的那些步骤不同或附加的步骤，或者可以以与结合图3所描述的顺序不同的顺序执行步骤。
在硅衬底中形成310多个贯穿硅通孔。在一些实施例中，贯穿硅通孔形成在硅衬底的边缘。
硅衬底例如通过氧化物-氧化物键合附接到第一管芯上。氧化物-氧化物键合可以通过等离子体处理、压缩和退火来形成。贯穿硅通孔的至少一部分电连接到第一管芯。硅衬底和第一管芯通过面对面键合附接330到第二管芯上，第一管芯电连接到第二管芯。硅衬底可以在附接过程中用作载体衬底。
在第二管芯附接到第一管芯和硅衬底上之后，显露340贯穿硅通孔。贯穿硅通孔可以通过蚀刻、抛光或其他方法使硅衬底减薄来显露。减薄的硅衬底的厚度不大于贯穿硅通孔的高度，从而显露贯穿硅通孔的导电垫。电气部件可以附接在硅衬底上并电连接到贯穿硅通孔。电气部件的例子包括微型LED和光电二极管。第一管芯和第二管芯可以包括控制和驱动电气部件操作的电路。因为贯穿硅通孔没有形成在第一管芯或第二管芯中，所以消除了第一管芯和第二管芯上的有源电路区域的损失。
在说明书中使用的语言主要出于可读性和指导性的目的而被选择，并且它可以不被选择来描绘或限制发明的主题。因此，意图是本公开的范围不由该详细描述限制，而是由在基于其的申请上发布的任何权利要求限制。因此，实施例的公开意图对本公开的范围是说明性的，而不是限制性的，在所附权利要求中阐述了本公开的范围。

Claims (34)

1.一种制造堆叠电路管芯的组件的方法，包括：
在硅衬底中形成多个贯穿硅通孔；
将所述硅衬底附接到第一管芯上，其中所述贯穿硅通孔的至少一部分电连接到所述第一管芯；
通过面对面键合将所述硅衬底和所述第一管芯附接到第二管芯上，其中所述第一管芯电连接到所述第二管芯；和
在所述第二管芯附接到所述第一管芯和所述硅衬底上之后，显露所述贯穿硅通孔，
其中所述硅衬底被配置成在所述显露之前用作载体衬底。
2.根据权利要求1所述的方法，其中所述贯穿硅通孔的数量在10000至500000的范围内。
3.根据权利要求1所述的方法，其中所述贯穿硅通孔具有1至50微米范围内的间距。
4.根据权利要求1所述的方法，还包括：
将附接有所述第一管芯和所述第二管芯的硅衬底附接在印刷电路板上，其中所述第二管芯电连接到所述印刷电路板。
5.根据权利要求1所述的方法，还包括：
在显露所述贯穿硅通孔之后，将一个或更多个电气部件附接到所述硅衬底上，其中所述电气部件通过所述贯穿硅通孔电连接到所述第一管芯。
6.根据权利要求5所述的方法，其中所述一个或更多个电气部件包括微型发光二极管或光电二极管的阵列。
7.根据权利要求5所述的方法，其中所述第一管芯包括被配置为向所述一个或更多个电气部件提供驱动电流的驱动电路。
8.根据权利要求5所述的方法，其中所述第二管芯包括数字电路，所述数字电路被配置成将数字信号转换成用于操作所述一个或更多个电气部件的模拟信号。
9.根据权利要求5所述的方法，其中所述硅衬底包括金属元件，所述金属元件被配置为扩散由所述电气部件的操作产生的热量。
10.根据权利要求1所述的方法，其中所述贯穿硅通孔形成在所述硅衬底的边缘。
11.一种堆叠电路管芯的组件，包括：
硅衬底，其形成有贯穿硅通孔；
第一管芯，其通过键合附接到所述硅衬底，其中所述第一管芯的电极电连接到所述贯穿硅通孔；和
第二管芯，其通过面对面键合附接到所述第一管芯，其中所述第二管芯的电极电连接到所述第一管芯的电极，
其中所述硅衬底被配置成在显露之前用作载体衬底。
12.根据权利要求11所述的组件，其中所述贯穿硅通孔的数量在10000至500000的范围内。
13.根据权利要求11所述的组件，其中所述贯穿硅通孔具有1至50微米范围内的间距。
14.根据权利要求11所述的组件，还包括印刷电路板，在所述印刷电路板上附接有与所述第一管芯和所述第二管芯附接的硅衬底，所述第二管芯电连接到所述印刷电路板。
15.根据权利要求11所述的组件，还包括在显露所述贯穿硅通孔之后附接到所述硅衬底上的一个或更多个电气部件，所述电气部件通过所述贯穿硅通孔电连接到所述第一管芯。
16.根据权利要求15所述的组件，其中所述一个或更多个电气部件包括微型发光二极管或光电二极管的阵列。
17.根据权利要求15所述的组件，其中所述第一管芯包括驱动电路，所述驱动电路被配置为向所述一个或更多个电气部件提供驱动电流。
18.根据权利要求15所述的组件，其中所述第二管芯包括数字电路，所述数字电路被配置为将数字信号转换成用于操作所述一个或更多个电气部件的模拟信号。
19.根据权利要求15所述的组件，其中，所述硅衬底包括金属元件，所述金属元件被配置为扩散由所述电气部件的操作产生的热量。
20.根据权利要求11所述的组件，其中所述贯穿硅通孔形成在所述硅衬底的边缘。
21.一种制造堆叠电路管芯的组件的方法，包括：
在硅衬底中形成多个贯穿硅通孔；
将所述硅衬底附接到第一管芯上，其中所述贯穿硅通孔的至少一部分电连接到所述第一管芯；
通过面对面键合将所述硅衬底和所述第一管芯附接到第二管芯上，其中所述第一管芯电连接到所述第二管芯；和
在所述第二管芯附接到所述第一管芯和所述硅衬底上之后，显露所述贯穿硅通孔，
其中所述硅衬底被配置成在所述显露之前用作载体衬底。
22.根据权利要求21所述的方法，其中所述贯穿硅通孔的数量在10000至500000的范围内。
23.根据权利要求21或22所述的方法，其中所述贯穿硅通孔具有1至50微米范围内的间距。
24.根据权利要求21至23中任一项所述的方法，还包括：
将附接有所述第一管芯和所述第二管芯的所述硅衬底附接在印刷电路板上，其中所述第二管芯电连接到所述印刷电路板。
25.根据权利要求21至24中任一项所述的方法，还包括：
在显露所述贯穿硅通孔之后，将一个或更多个电气部件附接到所述硅衬底上，其中所述电气部件通过所述贯穿硅通孔电连接到所述第一管芯。
26.根据权利要求25所述的方法，其中所述一个或更多个电气部件包括微型发光二极管或光电二极管的阵列；和/或
其中所述第一管芯包括被配置为向所述一个或更多个电气部件提供驱动电流的驱动电路；和/或
其中所述第二管芯包括数字电路，所述数字电路被配置成将数字信号转换成用于操作所述一个或更多个电气部件的模拟信号；和/或
其中所述硅衬底包括金属元件，所述金属元件被配置成扩散由所述电气部件的操作产生的热量。
27.根据权利要求21至26中任一项所述的方法，其中所述贯穿硅通孔形成在所述硅衬底的边缘。
28.一种堆叠电路管芯的组件，包括：
硅衬底，其形成有贯穿硅通孔；
第一管芯，其通过键合附接到所述硅衬底，其中所述第一管芯的电极电连接到所述贯穿硅通孔；和
第二管芯，其通过面对面键合附接到所述第一管芯，其中所述第二管芯的电极电连接到所述第一管芯的电极，
其中所述硅衬底被配置成在显露之前用作载体衬底。
29.根据权利要求28所述的组件，其中所述贯穿硅通孔的数量在10000至500000的范围内。
30.根据权利要求28或29所述的组件，其中所述贯穿硅通孔具有1至50微米范围内的间距。
31.根据权利要求28至30中任一项所述的组件，还包括印刷电路板，在所述印刷电路板上附接有与所述第一管芯和所述第二管芯附接的硅衬底，所述第二管芯电连接到所述印刷电路板。
32.根据权利要求28至31中任一项所述的组件，还包括在显露所述贯穿硅通孔之后附接到所述硅衬底上的一个或更多个电气部件，所述电气部件通过所述贯穿硅通孔电连接到所述第一管芯。
33.根据权利要求32所述的组件，其中所述一个或更多个电气部件包括微型发光二极管或光电二极管的阵列；和/或
其中所述第一管芯包括被配置为向所述一个或更多个电气部件提供驱动电流的驱动电路；和/或
其中所述第二管芯包括数字电路，所述数字电路被配置成将数字信号转换成用于操作所述一个或更多个电气部件的模拟信号；和/或
其中所述硅衬底包括金属元件，所述金属元件被配置成扩散由所述电气部件的操作产生的热量。
34.根据权利要求28至33中任一项所述的组件，其中所述贯穿硅通孔形成在所述硅衬底的边缘。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11373991B2 (en) * 2020-02-06 2022-06-28 Lumileds Llc Methods of manufacturing light-emitting devices with metal inlays and bottom contacts
US11575074B2 (en) 2020-07-21 2023-02-07 Lumileds Llc Light-emitting device with metal inlay and top contacts
JP2022040814A (ja) * 2020-08-31 2022-03-11 シャープセミコンダクターイノベーション株式会社 画像表示素子

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010245288A (ja) * 2009-04-06 2010-10-28 Canon Inc 半導体装置の製造方法
CN102593275A (zh) * 2011-01-13 2012-07-18 台湾积体电路制造股份有限公司 制作发光二极管封装结构的方法以及发光二极管元件
CN102637784A (zh) * 2011-02-11 2012-08-15 台湾积体电路制造股份有限公司 发光二极管封装基板及其制作方法
US20130099388A1 (en) * 2011-10-21 2013-04-25 Hynix Semiconductor Inc. Stacked semiconductor package
US20150279825A1 (en) * 2014-03-26 2015-10-01 Pil-Kyu Kang Semiconductor devices having hybrid stacking structures and methods of fabricating the same
US20150318261A1 (en) * 2014-04-30 2015-11-05 Samsung Electronics Co., Ltd. Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8334170B2 (en) * 2008-06-27 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking devices
CN105140136B (zh) * 2009-03-30 2018-02-13 高通股份有限公司 使用顶部后钝化技术和底部结构技术的集成电路芯片
US9236341B1 (en) * 2010-08-25 2016-01-12 Xilinix, Inc. Through-silicon vias with metal system fill
US8560982B2 (en) * 2011-06-27 2013-10-15 Xilinx, Inc. Integrated circuit design using through silicon vias
JP2013110151A (ja) 2011-11-17 2013-06-06 Elpida Memory Inc 半導体チップ及び半導体装置
JP5925006B2 (ja) * 2012-03-26 2016-05-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
TWI506712B (zh) * 2012-10-25 2015-11-01 矽品精密工業股份有限公司 半導體結構之測試方法
US20140327132A1 (en) 2013-05-03 2014-11-06 National Center For Advanced Packaging (Ncap China) TSV Backside Reveal Structure and Exposing Process
US9184139B2 (en) 2013-12-17 2015-11-10 Stats Chippac, Ltd. Semiconductor device and method of reducing warpage using a silicon to encapsulant ratio
US9543229B2 (en) * 2013-12-27 2017-01-10 International Business Machines Corporation Combination of TSV and back side wiring in 3D integration
US9666520B2 (en) * 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
KR102352677B1 (ko) 2014-08-27 2022-01-17 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9806128B2 (en) * 2015-05-22 2017-10-31 Globalfoundries Singapore Pte. Ltd. Interposers for integrated circuits with multiple-time programming and methods for manufacturing the same
US20160343719A1 (en) * 2015-05-22 2016-11-24 Globalfoundries Singapore Pte. Ltd. Interposers for integrated circuits with one-time programming and methods for manufacturing the same
JP6531603B2 (ja) 2015-10-01 2019-06-19 富士通株式会社 電子部品、電子装置及び電子装置の製造方法
US9818726B2 (en) * 2015-12-28 2017-11-14 International Business Machines Corporation Chip stack cooling structure
US9704830B1 (en) * 2016-01-13 2017-07-11 International Business Machines Corporation Semiconductor structure and method of making
US11189573B2 (en) * 2016-03-31 2021-11-30 Intel Corporation Semiconductor package with electromagnetic interference shielding using metal layers and vias
US10833052B2 (en) * 2016-10-06 2020-11-10 Micron Technology, Inc. Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
US10763290B2 (en) * 2017-02-22 2020-09-01 Elwha Llc Lidar scanning system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010245288A (ja) * 2009-04-06 2010-10-28 Canon Inc 半導体装置の製造方法
CN102593275A (zh) * 2011-01-13 2012-07-18 台湾积体电路制造股份有限公司 制作发光二极管封装结构的方法以及发光二极管元件
CN102637784A (zh) * 2011-02-11 2012-08-15 台湾积体电路制造股份有限公司 发光二极管封装基板及其制作方法
US20130099388A1 (en) * 2011-10-21 2013-04-25 Hynix Semiconductor Inc. Stacked semiconductor package
US20150279825A1 (en) * 2014-03-26 2015-10-01 Pil-Kyu Kang Semiconductor devices having hybrid stacking structures and methods of fabricating the same
US20150318261A1 (en) * 2014-04-30 2015-11-05 Samsung Electronics Co., Ltd. Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same

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