CN211350641U - 电子设备 - Google Patents
电子设备 Download PDFInfo
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- CN211350641U CN211350641U CN202020354540.0U CN202020354540U CN211350641U CN 211350641 U CN211350641 U CN 211350641U CN 202020354540 U CN202020354540 U CN 202020354540U CN 211350641 U CN211350641 U CN 211350641U
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Abstract
本文公开了一种电子设备。在一个示例中,电子设备包括衬底、第一裸片堆叠和第二裸片堆叠。第一裸片堆叠包括第一功能裸片和第一虚设裸片。将第一功能裸片安装到衬底。第二堆叠包括被安装到衬底的多个串行堆叠的第二功能裸片。第一虚设裸片堆叠在第一功能裸片上。第一虚设裸片的顶表面与第二裸片堆叠的顶表面基本共面。在一个特定示例中,第一裸片堆叠包括逻辑裸片,并且第二裸片堆叠包括多个串行堆叠的存储器裸片。
Description
技术领域
本公开的实施例一般地涉及芯片封装和具有所述芯片封装的电子设备。特别地,本公开的实施例涉及包括至少一个堆叠的虚设裸片的芯片封装。
背景技术
电子设备,尤其诸如平板电脑、计算机、服务器,室内电信、室外电信、工业计算机、高性能计算数据中心、复印机、数码相机,智能电话、控制系统和自动柜员机,为了增强的功能和更高的组件密度,经常采用利用芯片封装的电子组件。常规的芯片封装包括一个或多个堆叠的组件,诸如集成电路(IC)裸片、穿硅通孔(TSV)中介层和具有堆叠在印刷电路板(PCB)上的芯片封装本身的封装衬底。IC裸片可以包括存储器、逻辑、MEMS、RF或其他IC设备。
在许多芯片封装中,提供足够的热管理已变得越来越具有挑战性。无法提供足够的冷却通常会导致使用寿命缩短,甚至是设备故障。在将高带宽存储器(HBM)堆叠和逻辑裸片(诸如现场可编程门阵列(FPGA))集成在单个封装的应用中,热管理尤其是有问题的。在这种应用中,由于过度使用热界面材料或补偿高度不匹配的二次成型,HBM堆叠和逻辑裸片之间的高度差别可能导致低效地冷却。无法充分地调节芯片封装的温度还可能导致性能下降、设备故障或系统关闭。此外,HBM堆叠和逻辑裸片之间的高度差别还产生了各种组装和工厂自动化的问题,这不期望地导致了不良的产品产量和更长的,因此更昂贵的制备时间。
因此,需要一种用于共同封装逻辑和存储器应用的改进的芯片封装。
实用新型内容
本公开的实施例可以至少部分解决解决现有技术中的以上技术问题。
本文公开了一种电子设备。在第一方面,公开了一种电子设备,包括:衬底;第一裸片堆叠,被安装到所述衬底,所述第一裸片堆叠包括堆叠在第一功能裸片上的第一虚设裸片;和第二裸片堆叠,与所述第一裸片堆叠邻近设置,所述第二裸片堆叠包括多个串行堆叠的第二功能裸片,所述第一虚设裸片的顶表面与所述第二裸片堆叠的顶表面基本共面。
在一些实施例中,所述电子设备还包括:氧化物键合,将所述第一虚设裸片固定至所述第一功能裸片。
在一些实施例中,所述第一虚设裸片被减薄。
在一些实施例中,所述第二裸片堆叠的顶表面在超出所述衬底775μm的上方延伸。
在一些实施例中,形成所述第二裸片堆叠的所述多个串行堆叠的第二功能裸片包括至少12个存储器裸片。
在一些实施例中,形成所述第二裸片堆叠的所述多个串行堆叠的第二功能裸片包括多于16个的存储器裸片。
在一些实施例中,形成所述第二裸片堆叠的所述多个串行堆叠的第二功能裸片包括多于20个的存储器裸片。
在一些实施例中,所述电子设备还包括:第二虚设裸片,设置在所述第一虚设裸片和所述第一功能裸片之间。
在一些实施例中,所述第一虚设裸片和所述第二虚设裸片中的至少一个虚设裸片被减薄。
在一些实施例中,所述第一虚设裸片和所述第二虚设裸片中的一个虚设裸片被减薄,并且所述第一虚设裸片和所述第二虚设裸片中的另一虚设裸片不被减薄。
在一些实施例中,所述电子设备还包括:多个虚设裸片,设置在所述第一虚设裸片和所述第一功能裸片之间。
在一些实施例中,所述电子设备还包括:盖,设置在所述第一虚设裸片的顶表面和所述第二裸片堆叠的顶表面之上并且与之热传导接触。
在一些实施例中,所述衬底是中介层衬底,并且其中所述中介层衬底被安装在封装衬底上。
在第二方面,公开了一种电子设备。所述电子设备包括:封装衬底;中介层衬底,被安装在所述封装衬底上;存储器堆叠,被安装在所述中介层衬底的顶表面上,所述存储器堆叠包括多个串行堆叠的存储器裸片;以及逻辑堆叠,被安装在所述中介层衬底的顶表面上,所述逻辑堆叠包括设置在逻辑裸片上的一个或多个虚设裸片,一个或多个虚设裸片中的至少第一虚设裸片被减薄,所述逻辑堆叠的顶表面与所述存储器堆叠的顶表面基本共面。
在一些实施例中,所述逻辑堆叠还包括:第二虚设裸片,堆叠在所述第一虚设裸片上。
在一些实施例中,形成所述存储器堆叠的所述多个串行堆叠的存储器裸片包括至少16个存储器裸片。
在一个示例中,电子设备包括衬底、第一裸片堆叠和第二裸片堆叠。第一裸片堆叠包括第一功能裸片和第一虚设裸片。第一功能裸片安装到衬底。第二裸片堆叠包括安装在衬底上的多个串行堆叠的第二功能裸片。第一虚设裸片堆叠在第一功能裸片上。第一虚设裸片的顶表面与第二裸片堆叠的顶表面基本共面。在一个特定示例中,第一裸片堆叠包括逻辑裸片,并且第二裸片堆叠包括多个串行堆叠的存储器裸片。
在另一示例中,电子存储器设备包括:安装在封装衬底上的中介层衬底、安装在中介层衬底顶表面上的逻辑堆叠、设置在中介层衬底顶表面上的存储器堆叠。逻辑堆叠包括堆叠在逻辑裸片上的一个或多个虚设裸片。存储器堆叠包括多个串行堆叠的存储器裸片。将一个或多个虚设裸片中的至少一个虚设裸片减薄。逻辑堆叠的顶表面与存储器堆叠的顶表面基本共面。
与常规封装相比,本公开的实施例的芯片封装具有基本相等的存储器堆叠和逻辑堆叠高度,因此该芯片封装提供了显著改进的热管理。而且,由于存储器堆叠和逻辑堆叠高度基本相等因此基本共面,所以芯片封装更容易由自动化设备处理,因此降低了成本和制造的复杂度。
附图说明
可以参考实施例对以上简要概述的本实用新型进行更特定的描述,以便可以详细地理解本实用新型的上述特征,其中一些实施例被图示在附图中。然而,应当注意,附图仅图示了本实用新型的典型示例,并且由于本实用新型可以认可其他等同有效的实施例,因此附图不应被认为是对本实用新型范围的限制。
图1A是安装在印刷电路板上的集成电路芯片封装的示意正视图。
图1B至图1C是安装在印刷电路板上的集成电路芯片封装的备选变型的示意正视图。
图2至图7是在制备的不同阶段期间,不同的集成电路芯片封装示例的示意截面图。
图8是与图2至图7中描绘的制备阶段相对应的制备芯片封装的方法的流程图。
为了便于理解,在可能的地方使用相同的附图标记来表示图中共用的相同元件。可以想到,一个实施例的元件可以被有益地并入其他实施例中。
具体实施方式
本文描述的示例通常提供芯片封装和制备芯片封装的方法。芯片封装包括第一裸片堆叠,第一裸片堆叠具有与一个或多个功能裸片堆叠的虚设裸片。功能裸片可以是逻辑裸片、存储器裸片或其他功能裸片。利用虚设裸片来减小或甚至是消除共同封装到电子设备中的第二裸片堆叠与第一裸片堆叠之间的高度差别。第二裸片堆叠还可以包括多个功能裸片。一些示例性的电子设备包括多芯片模块(MCM)、系统级封装(SiP)、片上系统(SoC)、InFO封装、衬底-晶片-芯片(CoWoS)、2D封装、2.5D封装和3D封装。组成第一裸片堆叠的裸片在功能上可以是同质或异质的。类似地,组成第二堆叠的裸片在功能上可以是同质或异质的。附加地,组成两个堆叠的裸片在功能上也可以是同质或异质的。在一个示例中,芯片封装包括逻辑堆叠,该逻辑堆叠具有与逻辑裸片堆叠的虚设裸片。利用虚设裸片来减小或甚至是消除共同封装到存储器设备中的存储器堆叠和逻辑堆叠之间的高度差别。在一个示例中,存储器堆叠是高带宽存储器(HBM)堆叠,并且存储器设备是高带宽存储器(HBM)设备。由于HBM堆叠与逻辑/虚设裸片堆叠之间的高度差别基本相同,所以与具有不匹配堆叠高度的常规封装相比,改进了芯片封装的热管理。与常规的HBM设备相比,增强的热管理有利地实现了更可靠和更稳健的性能。
在常规的HBM设备中,制造约束通常限制HBM堆叠的总高度,HBM堆叠的总高度通常被限制为775μm,这是300mm直径晶片的标准厚度。由于更高的堆叠与常规的工艺和制备设备不兼容,因此该高度限度限制了在HBM堆叠内可以利用的存储器裸片的数量。如今,大多数HBM设备被限制为单个HBM堆叠内大约12至16个存储器裸片。附加地,如上所述,HBM堆叠与邻近逻辑裸片之间的不匹配在常规HBM封装的顶部处产生了不良的热传递界面,这不利于性能和设备的可靠性。
相反,本文描述的芯片封装不受775μm高度限度的约束,并且如此,HBM堆叠内的存储器裸片数目可以有利地超过单个HBM堆叠内的16个存储器裸片。附加地,HBM和逻辑/虚设裸片堆叠基本相似的高度,提高了由自动化工厂设备处理芯片封装的能力,这又减少了损坏的可能,提高了制造产出并降低了产品成本。
尽管文中描述了利用存储器裸片堆叠和邻近的逻辑裸片堆叠的上述参考的创新技术,但是通过使用减薄后的虚设裸片,使任何两个或多个裸片堆叠具有基本相等的高度被包括在本文描述的公开范围内,其中减薄后的虚设裸片是一个堆叠的一部分。
现在转向图1A,示意性地图示了集成电路电子设备150,集成电路电子设备150具有安装在印刷电路板(PCB)102上的示例性集成电路芯片封装100。芯片封装100被配置为存储器设备,诸如高带宽存储器(HBM)设备或其他存储器设备。然而,芯片封装100可以备选地配置为包括两个裸片堆叠的另一类型的电子设备,其中一个裸片堆叠包括用于产生与另一个裸片堆叠基本相等的堆叠高度的虚设裸片。芯片封装100包括衬底104,一个或多个第一裸片堆叠130和一个或多个第二裸片堆叠112安装在衬底104上。第一裸片堆叠130包括一个或多个功能裸片118和一个或多个虚设裸片120。第二堆叠112包括一个或多个功能裸片116。功能裸片116、118可以是逻辑裸片、存储器裸片或包括功能电路系统的其他类型的裸片。在图1描绘的示例中,第一裸片堆叠130在下文中被称为逻辑堆叠130,而第二裸片堆叠112在下文中被称为存储器堆叠。逻辑堆叠130包括逻辑裸片118和一个或多个虚设裸片120。存储器堆叠112包括多个串行堆叠的存储器裸片116N,其中N是正整数。存储器堆叠112还可以包括缓冲裸片114,多个存储器裸片116N安装在缓冲裸片114上。模制化合物(稍后在图5中示出)设置在裸片堆叠周围,以保持位置定向和每个堆叠112、130内的裸片间距。
在图1A所描绘的示例中,其上安装有逻辑堆叠130和存储器堆叠112的衬底104被配置为中介层衬底108。中介层衬底108安装到封装衬底110。封装衬底110的底部152安装到PCB 102的顶表面154上以形成电子设备150。
在另一示例中,芯片封装100不包括中介层衬底108,并且其上安装有逻辑堆叠130和一个或多个存储器堆叠112的衬底104被配置为封装衬底110。封装衬底110安装到PCB102上以形成电子设备150(如图1B中所示的电子设备150’)。
在另一示例中,芯片封装100包括安装到中介层衬底108的一个或多个逻辑堆叠130或一个或多个存储器堆叠112中的一项,以及安装到封装衬底110的一个或多个逻辑堆叠130或一个或多个存储器堆叠112中的另一项。封装衬底110安装到PCB 102以形成电子设备150(在图1C中示出为电子设备150”)。在图1C的示例中,多个(例如两个)逻辑堆叠130安装到中介层衬底108,而存储器堆叠112安装到封装衬底110。
返回到图1A且如上所述,存储器堆叠112包括多个堆叠的存储器裸片116N。使用焊料连接126(诸如,例如使用焊料微凸块)将存储器裸片116N机械且电性地连接。在图1A所描绘的示例中,尽管存储器裸片116N被图示在单个堆叠中,但是封装100可以包括存储器裸片116N的一个或多个堆叠。存储器裸片116N的堆叠可以包括不同数目的裸片116N。在一些示例中,存储器堆叠112中的存储器裸片116N的数目可以是12、16、20、24、32或其他期望的裸片116N的数目。每个存储器裸片116N被配置为高性能固态存储器设备,尤其诸如DRAM。
最接近中介层衬底108的存储器裸片1161设置在存储器堆叠112的缓冲裸片114上。使用焊料连接126(诸如,例如使用焊料微凸块)将存储器裸片1161机械且电性地连接到缓冲裸片114。缓冲裸片114通常管理与存储器堆叠112的存储器裸片116N的通信以及存储器裸片116N之间的通信。缓冲裸片114还用作I/O裸片,使存储器裸片116N与中介层衬底108对接,使得逻辑堆叠130的逻辑裸片118可以快速且有效地与存储器裸片116N进行通信。
利用焊料连接126将存储器堆叠112中最底部的裸片(诸如图1A中所示的缓冲裸片114),安装到中介层衬底108。焊料连接126将缓冲裸片114的电路系统166耦合至中介层衬底108的电路系统160。焊料连接126设置在缓冲裸片114和存储器裸片1161之间,以连接或耦合缓冲裸片114的电路系统166和存储器裸片1161的电路系统164。焊料连接126也设置在存储器裸片1161-N之间以连接或耦合存储器裸片1161-N的电路系统164,并且最终到中介层衬底108的电路系统160。
类似地,利用焊料连接126将中介层衬底108安装到封装衬底110。焊料连接126将封装衬底110的电路系统162耦合至中介层衬底108的电路系统160。还利用焊料连接126将封装衬底110的电路系统162机械且电性地连接到PCB 102的电路系统。因此,PCB 102的电路系统通过芯片封装100耦合至存储器裸片116N的电路系统164和逻辑裸片118的电路系统168。
存储器堆叠112具有底部144和顶表面136。在图1A的图示中,存储器堆叠112的底部144也是缓冲裸片114的底部144。类似地,存储器堆叠112的顶表面136也是存储器堆叠112中的距中介层衬底108最远的最顶层裸片116N的顶表面136。高度182被定义在存储器堆叠112的顶表面136和底部144之间并且被图示在图1A中。高度182可以大于775μm,并且在一些实施例中,高度182大于775μm。
如上所述,逻辑堆叠130包括至少一个逻辑裸片118和至少一个虚设裸片120。多个虚设裸片120由虚线示意性地图示,其中虚线将虚设裸片1201与虚设裸片120M分隔,其中M表示一个或多个虚设裸片。逻辑裸片118可以是可编程逻辑器件,诸如现场可编程门阵列(FPGA)、图形处理单元(GPU)、专用集成电路(ASIC)、片上系统(SoC)、处理器或其他IC逻辑结构。逻辑裸片118用作用于存储器堆叠112的存储器裸片116N的控制器。在图1A所描绘的示例中,芯片封装100被配置有与高带宽存储器(HBM)设备共同封装的逻辑堆叠130中的FPGA形式的至少一个逻辑裸片118,HBM设备具有包括存储器裸片116N(诸如DRAM)的至少一个存储器堆叠112。
返回到虚设裸片120的描述,虚设裸片120可以是由半导体晶片或其他合适材料制成的硅裸片。备选地,虚设裸片120可以由其他介电材料或源制备。可以将虚设裸片120键合或以其他方式粘附到逻辑裸片118。在一个示例中,利用氧化硅层将虚设裸片120键合至逻辑裸片118。可以在虚设裸片120或逻辑裸片118中的一个或两个的外表面上生长、沉积或以其他方式形成氧化物层。在一个示例中,氧化物层是氧化硅。通过将裸片118、120挤压在一起的同时施加热,氧化物层将虚设裸片120键合至逻辑裸片118。
当利用多个虚设裸片120时,可以将附加的虚设裸片120堆叠在被键合至逻辑裸片118的虚设裸片120上。可以以任何合适的方式将虚设裸片120键合或以其他方式粘附在一起。在一个示例中,利用氧化硅层将虚设裸片120键合在一起。
逻辑堆叠130具有底部138和顶表面134。在图1A的图示中,逻辑堆叠130的底部138也是逻辑裸片118的底部138。类似地,当逻辑堆叠130中存在单个虚设裸片120时,逻辑堆叠130的顶表面134也是虚设裸片120的顶表面134。当利用多个虚设裸片120时,逻辑堆叠130的顶表面134也是距中介层衬底108最远的最顶层虚设裸片120的顶表面134。高度180被定义在逻辑堆叠130的顶表面134和底部138之间,并且被图示在图1A中。高度180通常大于775μm。逻辑堆叠130的高度180也基本上与存储器堆叠112的高度182相同。如本文所利用的,高度180、182在彼此的大约10mm内时为“基本相同”,导致顶表面134、136“基本共面”。具有基本相等的高度180、182有利地提供了许多益处,如下文进一步描述的,其中一个益处是增强了逻辑堆叠130和存储器堆叠112的热管理。
在一个示例中,可以通过减薄逻辑堆叠130中的至少一个虚设裸片120,将高度180选择为基本等于存储器堆叠112的高度182。在利用多个虚设裸片120的示例中,组成逻辑堆叠130的至少一个虚设裸片120被减薄,而组成逻辑堆叠130的一个或多个其他虚设裸片120可以被减薄,也可以不被减薄。在其他示例中,组成逻辑堆叠130的两个或多个或甚至全部的虚设裸片120被减薄。在利用单个虚设裸片120的示例中,虚设裸片120和组成逻辑堆叠130的逻辑裸片118中的至少一个或两个被减薄。可以通过蚀刻、铣削、研磨、抛光、机加工或其他合适的技术来减薄虚设裸片120或逻辑裸片118。在一个备选示例中,在高度180、182基本相等的情况下,不用减薄逻辑堆叠130的虚设裸片120。
盖122设置在逻辑堆叠130和存储器堆叠112上。可以将盖122可选地耦合至中介层衬底108,例如,利用加强件(未示出)。盖122可以由介电或导电材料制成。在图1A所描绘的示例中,盖122由导电材料制成,并且用作芯片封装100中的裸片118、116N、114的热沉。盖122可以可选地包括用于增强热传递的鳍片或具有单独的设置在盖上的热沉。
热界面材料(TIM)124设置在盖122、逻辑堆叠130和存储器堆叠112之间,以增强它们之间的热传递。在一个示例中,TIM 124可以是热聚合物粘合剂、导热膜、导热液体、导热凝胶或导热环氧树脂。由于存储器堆叠112和逻辑堆叠130的高度182、180基本相等,因此在堆叠112、130和盖122之间利用的TIM 124的量可以被控制以促进它们之间良好且均匀的热传递。在具有不匹配高度的常规封装中,设置在较矮堆叠和盖之间厚的TIM具有不良的热传递,这不利地影响了性能和可靠性。与常规封装相比,芯片封装100具有基本相等的存储器堆叠和逻辑堆叠高度182、180,因此该芯片封装提供了显著改进的热管理。而且,由于存储器堆叠和逻辑堆叠高度182、180基本相等因此基本共面,所以芯片封装100更容易由自动化设备处理,因此降低了成本和制造的复杂度。
图2至图7是被配置为存储器设备的集成电路芯片封装700在制备的不同阶段期间的示意截面图。在图2至7中图示的制备阶段对应于用于制备芯片封装700的方法800,方法800的示例被提供在图8所示的流程图中。芯片封装700被配置为具有至少两个裸片堆叠,诸如设置在衬底106上的至少一个或多个逻辑堆叠130和至少一个或多个存储器堆叠112。芯片封装700可以被用作图1A所示的芯片封装100,芯片封装100是电子设备150的一部分。
现在参考图2至图8,制备芯片封装700的方法800开始于操作802:如图2所示,将至少一个虚设裸片120’堆叠在逻辑裸片118上,以形成逻辑堆叠130’。尽管图2中图示了一个虚设裸片120’,但是可以在逻辑裸片118上堆叠两个或多个虚设裸片120’。
虚设裸片120’通常具有高度202,高度202被定义在逻辑堆叠130’的顶表面134’和逻辑裸片118顶部与虚设裸片120’底部之间的界面之间。在一个示例中,高度202对应于从其上切割出虚设裸片120’的晶片厚度。例如通过键合或粘合剂将虚设裸片120’固定至逻辑裸片118。在一个示例中,利用氧化物键合或其他合适的技术将虚设裸片120’固定至逻辑裸片118。
在操作804,如图3所示,减薄固定至逻辑裸片118的虚设裸片120’,以形成逻辑堆叠130。可以通过从虚设裸片120’的顶表面134’去除材料来减薄虚设裸片120’,以形成更接近逻辑裸片118的底部138的新的顶表面134’。可以通过蚀刻、铣削、研磨、抛光、机加工或其他合适的技术将虚设裸片120’减薄到高度302。减薄后的虚设裸片由附图标记120表示。减薄后的虚设裸片120的高度302被定义在逻辑堆叠130的新顶表面134和逻辑裸片118顶部与虚设裸片120底部之间的界面之间。由于已经从虚设裸片的顶部去除了材料,因此高度302小于高度202。尽管按照图8中所述的顺序,操作802先于操作804,但是备选地,可以在操作802之前减薄虚设裸片120’,其中在将虚设裸片120粘附到逻辑裸片118之后,可选地执行操作804。
尽管图2至图3图示了在分离的裸片上执行的堆叠和减薄,但是可以备选地在切割部分晶片之前,同时减薄虚设裸片130。附加地,可以将包括虚设裸片130的晶片键合至包括逻辑裸片118的晶片,随后进行切割以形成逻辑堆叠130(可以在切割之前或之后进行减薄)。例如,尽管裸片118、120’在图2至图3中被图示为单个的裸片,但是虚设裸片120可以是包括多个虚设裸片120’的虚设晶片260(以虚线示出)的一部分,而逻辑是裸片118是包括多个逻辑裸片118的晶片270(以虚线示出)的一部分,随后可以进行切割以形成多个单个的逻辑堆叠130。在该示例中,虚设裸片120’的顶表面134’也是虚设晶片260’的顶表面262’。例如通过键合或粘合剂将虚设晶片260’的底表面264固定至包括逻辑裸片118的晶片270的顶表面274。利用氧化物键合或其他合适的技术将虚设晶片260’固定至晶片270。尽管在图2至图3中以虚线示出了堆叠在晶片270上的单个虚设晶片260’,但是可以想到,虚设晶片260’是说明性的多个堆叠的虚设晶片260。固定至晶片270的虚设晶片260’被减薄并被分离,或者备选地被分离并被减薄,以形成多个逻辑堆叠130。可以通过从虚设晶片260’的顶表面262’去除材料来减薄虚设晶片260’,以形成更接近逻辑裸片118的底部138的新的顶表面262。如上所述,减薄虚设晶片260’直到减薄后的虚设晶片120达到高度302。减薄后的虚设晶片由附图标记260表示。
在操作806,如图4所示,将减薄后的逻辑堆叠130和存储器堆叠112安装到衬底106。尽管图4所示的衬底106被配置为中介层衬底108,但是如参考图1A所讨论的,可以将堆叠112、130可选地安装到被配置为封装衬底110的衬底106。在操作806,制作中介层衬底108与堆叠112、130之间的焊料连接126,以将中介层衬底108的电路系统160电性且机械地连接至位于堆叠112、130中的电路系统164、166、168。
在操作808中,如图5所示,将模制化合物502设置在中介层衬底108的顶表面140上,以包封堆叠112、130。模制化合物502具有顶表面504,该顶表面504延伸超过堆叠112、130的顶表面134、136。模制化合物502通常是介电材料,诸如环氧树脂或高温聚合物。
在操作810,如图6所示,从模制化合物502的顶表面504去除材料,使得模制化合物502的新的顶表面602与堆叠112、130的顶表面134、136基本共面。可以通过蚀刻、铣削、研磨、抛光、机加工或其他合适的技术去除模制化合物502的顶表面504。
在操作812,如图7所示,当利用中介层时,将具有附接的堆叠112、130的中介层衬底108安装到封装衬底110的顶表面148上。在操作812,制作在中介层衬底108和封装衬底110之间的焊料连接126,以将中介层衬底108的电路系统160电性且机械地连接至位于封装衬底110中的电路系统162。
在操作814,还如图7所示,盖122设置在堆叠112、130的顶表面134、136上。TIM 124设置在盖122和堆叠112、130的顶表面134、136之间以增强从堆叠112、130的裸片到盖122的热传递。
因此,本文描述的芯片封装和制备方法基本上消除了被共同封装到HBM或其他存储器设备中的逻辑堆叠和存储器堆叠之间的高度差别。共同封装的存储器堆叠和逻辑堆叠具有基本相同的高度,与具有不匹配堆叠高度的常规封装相比,这增强了芯片封装的热管理,从而实现了更可靠和更稳健的性能。本文描述的芯片封装也不受常规芯片封装的775μm高度限度的约束,并且如此,存储器堆叠内的存储器裸片的数目可以有利地超过单个存储器堆叠内的16个存储器裸片。附加地,存储器堆叠和逻辑堆叠的基本相似的高度更有效地与工厂自动化对接,这有利地提高了产品产量,同时降低了制备成本,并且最终降低了芯片封装的成本。
尽管前述内容针对本公开的实施例,但是可以在不脱离其基本范围的情况下设计其他和进一步的实施例,并且其范围由所附权利要求确定。
Claims (16)
1.一种电子设备,其特征在于,包括:
衬底;
第一裸片堆叠,被安装到所述衬底,所述第一裸片堆叠包括堆叠在第一功能裸片上的第一虚设裸片;和
第二裸片堆叠,与所述第一裸片堆叠邻近设置,所述第二裸片堆叠包括多个串行堆叠的第二功能裸片,所述第一虚设裸片的顶表面与所述第二裸片堆叠的顶表面基本共面。
2.根据权利要求1所述的电子设备,其特征在于,还包括:
氧化物键合,将所述第一虚设裸片固定至所述第一功能裸片。
3.根据权利要求1所述的电子设备,其特征在于,所述第一虚设裸片被减薄。
4.根据权利要求1所述的电子设备,其特征在于,所述第二裸片堆叠的顶表面在超出所述衬底775μm的上方延伸。
5.根据权利要求4所述的电子设备,其特征在于,形成所述第二裸片堆叠的所述多个串行堆叠的第二功能裸片包括至少12个存储器裸片。
6.根据权利要求4所述的电子设备,其特征在于,形成所述第二裸片堆叠的所述多个串行堆叠的第二功能裸片包括多于16个的存储器裸片。
7.根据权利要求4所述的电子设备,其特征在于,形成所述第二裸片堆叠的所述多个串行堆叠的第二功能裸片包括多于20个的存储器裸片。
8.根据权利要求6所述的电子设备,其特征在于,还包括:
第二虚设裸片,设置在所述第一虚设裸片和所述第一功能裸片之间。
9.根据权利要求8所述的电子设备,其特征在于,所述第一虚设裸片和所述第二虚设裸片中的至少一个虚设裸片被减薄。
10.根据权利要求8所述的电子设备,其特征在于,所述第一虚设裸片和所述第二虚设裸片中的一个虚设裸片被减薄,并且所述第一虚设裸片和所述第二虚设裸片中的另一虚设裸片不被减薄。
11.根据权利要求6所述的电子设备,其特征在于,还包括:
多个虚设裸片,设置在所述第一虚设裸片和所述第一功能裸片之间。
12.根据权利要求1所述的电子设备,其特征在于,还包括:
盖,设置在所述第一虚设裸片的顶表面和所述第二裸片堆叠的顶表面之上并且与之热传导接触。
13.根据权利要求1所述的电子设备,其特征在于,所述衬底是中介层衬底,并且其中所述中介层衬底被安装在封装衬底上。
14.一种电子设备,其特征在于,包括:
封装衬底;
中介层衬底,被安装在所述封装衬底上;
存储器堆叠,被安装在所述中介层衬底的顶表面上,所述存储器堆叠包括多个串行堆叠的存储器裸片;以及
逻辑堆叠,被安装在所述中介层衬底的顶表面上,所述逻辑堆叠包括设置在逻辑裸片上的一个或多个虚设裸片,一个或多个虚设裸片中的至少第一虚设裸片被减薄,所述逻辑堆叠的顶表面与所述存储器堆叠的顶表面基本共面。
15.根据权利要求14所述的电子设备,其特征在于,所述逻辑堆叠还包括:
第二虚设裸片,堆叠在所述第一虚设裸片上。
16.根据权利要求14所述的电子设备,其特征在于,形成所述存储器堆叠的所述多个串行堆叠的存储器裸片包括至少16个存储器裸片。
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