CN113299632A - 具有镜像电路的堆叠式晶粒的集成电路器件 - Google Patents
具有镜像电路的堆叠式晶粒的集成电路器件 Download PDFInfo
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Abstract
本文描述了集成电路器件及其制造技术。集成电路器件利用以镜像方式制造的两对或更多对堆叠的集成电路晶粒,以降低制造的复杂性,从而降低成本。在一个示例中,提供了一种包括集成电路晶粒堆叠的集成电路器件。集成电路晶粒堆叠包括第一、第二、第三和第四集成电路晶粒。第一集成电路晶粒和第二集成电路晶粒通过它们的有源侧进行耦接,并且包括彼此为镜像的集成电路布置。第三集成电路晶粒和第四集成电路晶粒也通过它们的有源侧进行耦接,并且包括彼此为镜像的集成电路布置。
Description
技术领域
本发明的实施例总体上涉及集成电路器件,并且更具体地,涉及具有镜像电路的堆叠式集成电路晶粒的集成电路器件及其制造方法。
背景技术
电子设备经常采用电子组件,电子组件会利用芯片封装组件来提升功能性和提高组件密度。传统的芯片封装方案通常利用封装基板并经常结合硅通孔技术(TSV)中介件,以使多个集成电路(IC)晶粒(die)能够被安装在一个单独的封装基板上。IC晶粒可以包括存储器、逻辑元件或其他IC装置。这些包含一个或多个芯片封装的电子器件经常用于高级电子计算系统中,例如常见于电信和数据通信设备、数据中心和汽车电子设备。
在许多芯片封装组件中,IC晶粒被堆叠以在单个芯片封装组件内提供增强的存储器或处理能力。尽管对于增强的存储器或处理能力而言堆叠IC晶粒是期望的,但是在堆叠式集成电路器件的制造期间,堆叠IC晶粒呈现出额外的制造复杂性、挑战以及因此的成本。
因此,需要一种与常规技术相比制造成本更低廉的集成电路器件。
发明内容
本文描述了集成电路器件及其制造技术。集成电路器件利用以镜像方式制造的两对或更多对堆叠的集成电路晶粒,以降低制造的复杂性,从而降低成本。在一个示例中,提供了一种包括集成电路(IC)晶粒堆叠的集成电路器件。IC晶粒堆叠包括第一、第二、第三和第四IC晶粒。第一IC晶粒和第二IC晶粒通过它们的有源侧(active side)耦接,并且包括彼此为镜像的集成电路布置。第三IC晶粒和第四IC晶粒也通过它们的有源侧耦接,并且也包括彼此为镜像的集成电路布置。
在另一个示例中,提供了一种包括集成电路(IC)晶粒堆叠的集成电路器件。IC晶粒堆叠包括第一、第二、第三和第四IC晶粒。第一IC晶粒和第二IC晶粒通过它们的有源侧耦接,并且包括彼此为镜像的集成电路布置。第三晶粒体的有源侧耦接到第二IC晶粒的基板侧(substrate side)。第四晶粒体的有源侧耦接到第三IC晶粒的基板侧。
在又一个示例中,提供了一种用于制造集成电路器件的方法。所述方法包括将第一集成电路(IC)晶粒的有源侧安装到第二IC晶粒的有源侧,所述第一和第二IC晶粒具有彼此成镜像的集成电路布置;以及将第三IC晶粒安装到第二IC晶粒的基板侧。
附图说明
为了可以更详细地理解本发明的上述特征,可以通过参考实施例来对本发明进行更具体的描述,其中一些示例在附图中示出。然而,应当注意,附图仅示出了本发明的典型实施例,因此不应视为对本发明范围的限制,因为本发明可以允许其他等效的实施例。
图1是具有镜像电路的两个集成电路(IC)晶粒在将一个堆叠在另一个上之前的示意性俯视图。
图2是图1的IC晶粒的示意性截面图。
图3是一种用于制造集成电路器件的方法的框图,其中集成电路器件包括图1所示的IC晶粒等。
图4A-4G是根据图3的方法在制造的不同阶段的集成电路器件的另一示例的示意性侧视图。
图5是一种用于制造集成电路器件的方法的框图,其中集成电路器件包括图1所示的IC晶粒等。
图6A-6H是根据图5的方法在制造的不同阶段的集成电路器件的另一示例的示意性侧视图。
图7-9是包括具有图1的镜像电路的IC晶粒的集成电路器件的各种替代示例的示意性侧视图。
为了便于理解,在可能的情况下使用了相同的附图标记来表示附图共有的相同元件。可以预期,一个实施例的元件可以有益地并入其他实施例中。
具体实施方式
本文描述了集成电路器件及其制造技术。集成电路器件利用以镜像方式制造的两对或更多对堆叠的集成电路晶粒,以降低制造的复杂性。使用具有以镜像形式形成的电路的IC晶粒允许开发和鉴定单个掩模组,而该掩模组的镜像可以被利用来生产第二个IC晶粒,从而无需花费额外的成本和时间即可开发用于第二个IC晶粒的不同的第二个掩模组。此外,成对的镜像堆叠的集成电路晶粒允许在器件制造期间以减少数量的载流子附接和分离操作来制造四个或更多个IC晶粒的晶粒堆叠。因此,进一步降低了制造集成电路器件所需的成本和时间。因此,实现了与常规设计和制造技术相比具有显著成本和生产时间优势的坚固的集成电路器件。
现在转到图1,示出了将一个堆叠在另一个上之前的两个集成电路(IC)晶粒102、104的示意性俯视图,其中这两个集成电路晶粒102、104会在制造集成电路(IC)器件时将一个堆叠在另一个之上。IC器件中利用的IC晶粒102、104可以被配置为但不限于可编程逻辑设备,例如现场可编程门阵列(FPGA)、专用集成电路(ASIC)、存储器件,如高带宽存储器(HBM)、光学设备、处理器或其他IC存储器或逻辑结构。IC晶粒102、104中的一个或多个可以可选地包括光学装置,例如光电检测器、激光器、光源等。
第一IC晶粒102具有包含功能和其他电路112的晶粒体116。电路112由图1中的虚线所示的“F”示意性地表示。电路112终止于在多个接触垫110处的晶粒体116的有源侧106。尽管为简单起见在图1中仅示出了6个接触垫110,但是可以在晶粒体116的有源侧106上暴露超过400个接触垫110。
类似地,第二IC晶粒104具有包含功能和其他电路114的晶粒体118。电路114由图1中的虚线所示的“F”示意性地表示。电路114终止于在多个接触垫110处的晶粒体118的有源侧108。尽管为简单起见在图1中仅示出了6个接触垫110,但是可以在晶粒体118的有源侧108上暴露超过400个接触垫110。
第一IC晶粒102的电路112具有第一布置,该第一布置是第二IC晶粒104的电路114的第二布置的镜像。例如,第一IC晶粒102的接触垫110是布置在与第二IC晶粒104的接触垫110的位置成镜像的位置中。第一IC晶粒102和第二IC晶粒104的电路112、114的镜像布置在图2的IC晶粒102、104的示意性截面图中被进一步示出。
如图2所示,第一IC晶粒102的电路112通过构成晶粒体116的有源区202和基板204形成。有源区202形成在基板204上并终止于晶粒体116的有源侧106。基板204的背侧206设置在基板204的与有源区202相对的一侧上并且背对有源侧106。
有源区202包括形成在晶粒体116的线区域前端(FEOL)和线区域后端(BEOL)中的金属层和电介质层。设置在有源区202中的电路112的一部分具有电路元件220、224和布线222的布置。图2所示的两个电路元件220、224代表构成电路112的功能部分的许多电路元件。电路元件220、224可包括但不限于晶体管、二极管、电阻器、电容器、电感器和存储单元中的任何一个或多个。电路元件220、224通过布线222彼此互连并且与设置在晶粒体116的有源侧106上的接触垫110互连。布线222通常包括被配置为承载接地、电源或数据信号的导线和通孔。
电路112的一部分包括穿过基板204形成的硅通孔(TSV)210。TSV 210的一端暴露在晶粒体116的背侧206上,TSV 210的另一端通过布线222耦接到电路元件220、224和接触垫110。
类似地,第二IC晶粒104的电路114通过构成晶粒体118的有源区202和基板204形成。有源区202形成在基板204上并终止于晶粒体118的有源侧106。基板204的背侧208设置在基板204的与有源区202相对的一侧上,并且背对有源侧106。
布置在有源区202中的电路114的一部分具有电路元件230、234和布线232的布置。图2中所示的两个电路元件230、234代表了构成电路114的功能的许多电路元件。电路元件230、234可包括但不限于晶体管、二极管、电阻器、电容器、电感器和存储单元中的任何一个或多个。电路元件230、234通过布线232彼此互连并且与设置在晶粒体118的有源侧108上的接触垫110互连。布线232通常包括被配置为承载接地、电源或数据信号的导线和通孔。
如上所述,第一IC晶粒102的电路112具有第一布置,所述第一布置是构成第二IC晶粒104的电路114的第二布置的镜像。例如,第一IC晶粒102的接触垫110、电路元件220/224和布线222是处在第二IC晶粒104的接触垫110、电路元件230/234和布线232的位置的镜像中。而且,TSV 210在第一IC晶粒102的基板204内的位置是TSV 210在第二IC晶粒104的基板204内的位置的镜像。
因此,当第一IC晶粒102翻转使得第一IC晶粒102的有源侧106抵靠第二IC晶粒104的有源侧108布置时,IC晶粒102、104的接触垫110被对准以通过无焊混合焊接或通过接触垫110的焊锡连接而实现机械和电气连接。另外,由于TSV 210设置在镜像位置,暴露在IC晶粒102、104的背侧206、208上的TSV 210也可以配合以使功能电路112、114互联。
使用具有以镜像形成的电路112、114的IC晶粒102、104允许针对第一IC晶粒102开发和鉴定单个掩模组,而无需花费时间和成本来开发和鉴定用于第二IC晶粒104的全新的第二掩模组。特别是,使用镜像根据先前设计和鉴定的掩模组创建新的掩模组可确保使用镜像掩模组制造的第二IC晶粒104具有与第一IC晶粒102相同的功能、性能和可靠性,而无需为第二IC晶粒104开发不同的第二掩模组而花费大量的额外成本和时间。
图3是用于制造包括图1所示的IC晶粒102、104或其他类似的镜像IC晶粒的集成电路器件的方法300的框图。在图4A至4G中示意性地示出了根据图3的方法300制造的集成电路器件的制造的各个阶段。
方法300从步骤302开始,在该步骤中,具有镜像电路112、114的第一IC晶粒102和第二IC晶粒104被翻转,以使有源侧106、108彼此面对,如图4A所示。在步骤304,将IC晶粒102、104安装在一起,使得每个晶粒体116、118的有源侧106、108上的接触垫110被电连接,如图4B所示。可以利用诸如微凸点之类的焊料连接、混合连接或通过其他合适的技术将IC晶粒102、104安装在一起,以便形成厚实的有源-有源(AoA)IC晶粒堆叠402,其中AoA IC晶粒堆叠402包括在IC晶粒102、104的配合的有源侧106、108之间限定的有源-有源(AoA)界面410。在图4B所示的实施例中,AoA界面410利用由金属电路连接材料组成的混合连接器412耦接图4B中所示的IC晶粒102、104的接触垫110,其中金属电路连接材料设置在介电片中,。
在步骤306,将第二IC晶粒104进行薄化,如图4C所示。例如,如图所示,去除第二IC晶粒104的背侧208的一部分,使得背侧208具有新的薄化表面406,从而减小了晶粒体118的厚度。晶粒体118可以通过打磨、蚀刻、化学机械平面化或其他合适的技术来减薄。在一个示例中,通过研磨背侧208来使晶粒体118薄化,以产生在薄化表面406和有源侧108之间限定的厚度,该厚度为但不限于约50μm至约700μm。在薄化期间,由于第二IC晶粒104被固定至第一IC晶粒102,因此在步骤306处不需要载体,从而节省了时间和费用。步骤306使得厚实的AoA IC晶粒堆叠402转换为薄化AoA IC晶粒堆叠404。
在步骤308,将薄化AoA IC晶粒堆叠404对准以与翻转的第二薄化AoA IC晶粒堆叠404进行堆叠。如图4D所示,第二薄化AoA IC晶粒堆叠404具有倒转的取向,以使得一个薄化AoA IC晶粒堆叠404的薄化表面406面对另一个薄化AoA IC晶粒堆叠404的薄化表面406。
在步骤310中,将两个薄化AoA IC晶粒堆叠404安装在一起,以使暴露在薄化侧406(在薄化之前是背侧208)上的TSV 210的端部(如图2所示)被电连接,如图4E中所示,使得晶粒堆叠404的电路能够通信。薄化AoA IC晶粒堆叠404的相面对的IC晶粒104、104可以利用诸如微型凸点的焊料连接通过混合连接或通过其他合适的技术安装在一起,以形成完整的双AoA IC晶粒堆叠408。在图4E所示的实施例中,混合连接器412(例如由布置在介电片中的金属电路连接材料构成的上述连接器)被利用来耦接相邻IC晶粒104、104的暴露的TSV210。
在步骤312,将完整的双AoA IC晶粒堆叠408进行薄化以形成薄化双AoA IC晶粒堆叠440,如图4F所示。例如,至少一个第一IC晶粒102的背侧206的一部分被去除,使得背侧206具有新的薄化表面414,从而减小晶粒体116的厚度。晶粒体116可以如上所述的被薄化,并且在一个示例中,可以通过研磨来薄化。尽管在图4F中薄化双AoA IC晶粒堆叠440的顶部晶粒102显示为被薄化,但是可替代地或另外地,可以使用如上所述的技术来使薄化双AoAIC晶粒叠层440的底部晶粒102薄化。由于完整的双AoA IC晶粒堆叠408在薄化期间为第一IC晶粒102提供了牢固的锚定,在步骤312处不需要载体,因此节省了在制造薄化双AoA IC晶粒堆叠440期间的时间和费用。
在步骤314中,利用薄化双AoA IC晶粒堆叠440形成芯片封装组件430。芯片封装组件430包括封装基板432,并且可以可选地包括一个或多个其他IC晶粒434。薄化双AoA IC晶粒叠层440的电路通过焊料连接436或其他合适的封装连接而机械地和电气地连接到封装基板432。可选的附加IC晶粒434还经由焊料连接436或其他合适的封装连接而机械地和电气地连接到封装基板432。焊料连接436使IC晶粒434和薄化双AoA IC晶粒堆叠440能够互相通信,并通过在封装基板432中和/或之上形成的布线428与在封装基板432的相对侧上暴露的接触垫426通信。尽管在图4G中示出了一个附加的IC晶粒434,但是在IC晶粒434上和/或旁边可以堆叠一个或多个附加的IC晶粒。在芯片封装组件430中利用的IC晶粒434可以被配置为(但不限于)例如现场可编程门阵列(FPGA)、专用集成电路(ASIC)的可编程逻辑器件,例如高带宽存储器(HBM)的存储器件,例如光电探测器、激光器、光源的光学器件以及处理器或其他IC存储器或逻辑结构。在图4G所示的示例中,IC晶粒434被配置为逻辑晶粒,而薄化双AoA IC晶粒堆叠440被配置为存储器堆叠,从而芯片封装组件430被用作高带宽存储器(HBM)器件。IC晶粒434还可被配置为等同于上述IC晶粒102、104之一。
图5是用于制造包括图1所示的IC晶粒102、104等的集成电路器件的另一方法500的框图。根据图5的方法500制造的集成电路器件的各个制造阶段在图6A-6H中示意性地示出。
方法500从步骤502开始,其中将第三IC晶粒660固定到载体602,如图6A所示。第三IC晶粒660之所以如此命名是为了维持具有镜像电路的第一和第二IC晶粒102、104的先前惯例,这将稍后在方法500中引入。第三IC晶粒660通常包括具有设置在基板204上的有源区202的晶粒体。第三IC晶粒660可以被配置为上述的IC晶粒102、104、434中的任何一个,或者如期望的那样。晶粒体包括有源侧662和背侧664。第三IC晶粒660的有源侧662通过芯片附接的膜或其他可释放的粘合剂可释放地耦接到载体602。
在步骤504,第三IC晶粒660被薄化,如图6B所示。例如,去除第三IC晶粒660的背侧664的一部分,使得背侧664具有新的薄化表面606,从而减小了晶粒体的厚度。可以使用以上讨论的任何技术或其他合适的技术来薄化第三IC晶粒660的晶粒体。
在步骤506,将第三IC晶粒660安装到第二IC晶粒104,如图6C所示。可以利用诸如微型凸点的焊料连接配合混合连接或通过其他合适的技术将IC晶粒660、104安装在一起。在图6C中描绘的示例中,第三IC晶粒660的薄化表面606被安装到第二IC晶粒104的有源侧108,以形成有源-背侧晶粒堆叠610,如稍后在图6D中所示。在步骤508,也如图6D所示,将载体602从有源-背侧晶粒堆叠610中移除。
在步骤510,将薄化AoA IC晶粒堆叠404对准以与有源-背侧晶粒堆叠610进行堆叠,如图6E所示。薄化AoA IC晶粒堆叠404可以如上所述制造,或者通过另一种合适的技术制造。如图6E所示,薄化AoA IC晶粒堆叠404具有倒置的取向,使得薄化AoA IC晶粒堆叠404的薄化表面406面向有源-背侧晶粒堆叠610的第三IC晶粒660的有源侧662。
在步骤512,如图6F所示,将薄化AoA IC晶粒堆叠404固定到有源-背侧晶粒堆叠610,以形成有源-背侧AoA IC晶粒堆叠612,其包括在IC晶粒102、104的配合有源侧106、108之间限定的有源-有源(AoA)界面410。
在步骤514,如图6G所示,限定有源-背侧AoA IC晶粒堆叠612的远端的IC晶粒102、104中的一个被薄化,以形成薄化的有源-背侧AoA IC晶粒堆叠640。例如,如图所示,去除了第一IC晶粒102的背侧206的一部分,使得背侧206具有新的薄化表面414,从而减小了晶粒体116的厚度。可以如上所述地或通过另一种合适的技术来使晶粒体116变薄。由于在薄化期间第一IC晶粒102被固定到有源-背侧AoA IC晶粒堆叠612,所以在步骤514处不需要载体,从而节省时间和费用。第二IC晶粒也可以或可替代地被薄化。步骤516将有源-背侧AoAIC晶粒堆叠612转变为薄化的有源-背侧AoA IC晶粒堆叠640。
在步骤516,利用薄化的有源-背侧AoA IC晶粒堆叠640来形成芯片封装组件630,如图6H所示。芯片封装组件630包括封装基板632,并且可以可选地包括一个或多个另外的IC晶粒634。薄化的有源-背侧AoA IC晶粒堆叠640的电路经由焊料连接636或其他合适的封装连接机械地和电气地连接到封装基板632。可选的附加IC晶粒634还经由焊料连接636或其他合适的封装连接而机械地和电气地连接到封装基板632。焊料连接636使IC晶粒634和薄化的有源-背侧AoA IC晶粒堆叠640能够互相通信,并且能够与在封装基板632的相对侧上暴露的接触垫626通过形成在封装基板632上和/或在其中的布线628进行通信。虽然在图6H中示出了一个附加的IC晶粒634,但是一个或多个附加的IC晶粒可以堆叠在IC晶粒634上和/或旁边。在芯片封装组件630中使用的IC晶粒634可以如上面参照IC晶粒434所描述的那样进行配置。在图6H所描绘的示例中,IC晶粒634被配置为逻辑晶粒,而薄化的有源-背侧AoA IC晶粒堆叠640被配置为存储器堆叠,这样,芯片封装组件630就可以被用作高带宽存储器(HBM)器件。
图7-9是包括图1的IC晶粒102、104等的集成电路器件的各种替代示例的示意性侧视图。首先参考图7所示的集成电路器件700,集成电路器件700包括薄化双AoA IC晶粒堆叠440和至少一个附加的或第三IC晶粒702。第三IC晶粒702可以被配置为与上述的IC晶粒434相同。第三IC晶粒702包括晶粒体,晶粒体具有被设置在基板204上的有源区202。第三IC晶粒702的有源侧704电地和机械地耦接到设置在薄化双AoA IC晶粒堆叠440远端的第一IC102的薄化表面414。该第三IC晶粒702可以通过焊料、混合或其他合适的连接而安装到薄化双AoA IC晶粒堆叠440。第三IC晶粒702的基板204和/或布置在薄化双AoA IC晶粒堆叠440的相反端部处的第一IC晶粒102的基板204中的一个或全部可以被薄化,如虚线706所示。集成电路器件700可以被用在芯片封装组件中,例如图4G所示的芯片封装组件430,其中集成电路器件700代替薄化双AoA IC晶粒堆叠440。
图8是集成电路器件800的另一示意性侧视图。集成电路器件800包括薄化双AoAIC晶粒堆叠440和至少两个附加的IC晶粒。在图8所示的示例中,示出了包含IC晶粒102、104的薄化AoA IC晶粒堆叠404,其被耦接到薄化双AoA IC晶粒堆叠440。堆叠404、440可以如上所述配置,除了在图8的示例中是第一IC晶粒102而非第二IC晶粒104被薄化。薄化AoA IC晶粒堆叠404的薄化表面406被电地和机械地耦接至设置在薄化双AoA IC晶粒堆叠440远端的第一IC晶粒102的薄化表面414。薄化表面406可以通过焊接、混合或其他合适的连接而安装到薄化表面414。暴露在集成电路器件800远端的基板204中的一个或两个可以如虚线808所示那样被薄化。集成电路器件800可以用于芯片封装组件,例如如图4G所示的封装组件430,其中集成电路器件800代替了薄化双AoA IC晶粒堆叠440。
图9是集成电路器件900的另一示意性侧视图。集成电路器件900包括夹在另外的IC晶粒802处的两个薄化AoA IC晶粒堆叠404。尽管在薄化AoA IC管芯堆叠404之间仅示出了一个另外的IC晶粒802,但是可以使用一个以上的其他的IC晶粒802。IC晶粒802可以被配置为与上述IC晶粒434相同。
在图9所示的示例中,薄化AoA IC晶粒堆叠404中的一个的薄化表面406被展示为与IC晶粒802的有源侧804耦接,而另一个薄化AoA IC晶粒堆叠404的薄化表面406被显示为耦接到IC晶粒802的背侧806。集成电路器件900可以用于芯片封装组件中,例如图4G所示的芯片封装组件430,其中集成电路器件900代替薄化双AoA IC晶粒堆叠440。尽管示出了集成电路器件900的所有IC晶粒都是被薄化的配置,但是集成电路器件900的一个或多个IC晶粒可以具有完整的整体。
本文提供了包括集成电路(IC)晶粒堆叠的集成电路器件的其他示例。在第一示例中,集成电路器件的IC晶粒堆叠包括具有第一晶粒体的第一IC晶粒、具有第二晶粒体的第二IC晶粒、具有第三晶粒体的第三IC晶粒和具有第四晶粒体的第四IC晶粒。第一晶粒体具有有源侧、背侧,并且设置成集成电路的第一布置。第二晶粒体具有有源侧、背侧和集成电路的第二布置。第一IC晶粒的有源侧被安装到第二IC晶粒的有源侧。集成电路的第二布置是集成电路的第一布置的镜像。第三晶粒体具有有源侧、背侧和集成电路的第三布置。第四晶粒体具有有源侧、背侧和集成电路的第四布置。第三IC晶粒的有源侧被安装到第四IC晶粒的有源侧。集成电路的第四布置是集成电路的第三布置的镜像。
在第二示例中,第一示例的集成电路器件还可以包括具有第五晶粒体的第五IC晶粒。第五晶粒体具有有源侧、背侧和集成电路的第五布置。第五IC晶粒的背侧被安装到第四IC晶粒的背侧。
在第三示例中,第二示例的集成电路器件还可以包括具有第五晶粒体的第六IC晶粒。第六晶粒体具有有源侧、背侧和集成电路的第六布置。第六IC晶粒的有源侧被安装到第五IC晶粒的有源侧。
在第四示例中,第一示例的集成电路的第二布置是集成电路的第三或第四布置的镜像。
在第五示例中,第一示例的集成电路器件还可以包括具有第五晶粒体的第五IC晶粒。第五晶粒体具有有源侧、背侧和集成电路的第五布置。第五IC晶粒设置在第二IC晶粒与第三IC晶粒之间的IC晶粒堆叠中。
在第六示例中,第一示例的IC晶粒堆叠的第一、第二、第三和第四IC晶粒是存储器晶粒。
在第七示例中,第一示例的集成电路器件还可以包括:其上安装有IC晶粒堆叠的封装基板;以及逻辑晶粒,其安装到封装基板并被配置为通过设置在封装基板上和/或封装基板中的布线而与IC晶粒堆叠的IC晶粒通信。
在第八示例中,第七示例的第一、第二、第三和第四IC晶粒中的一个或多个被薄化。
在第九示例中,第七示例的晶粒堆叠还可以包括具有第五晶粒体的第五IC晶粒。第五晶粒体具有有源侧、背侧和集成电路的第五布置,其中第三IC晶粒或第五IC晶粒中的一个被安装在第二IC晶粒和第四IC晶粒之间。
在第十示例中,集成电路器件包括集成电路(IC)晶粒堆叠,该集成电路晶粒堆叠包括具有第一晶粒体的第一IC晶粒、具有第二晶粒体的第二IC晶粒、具有第三晶粒体的第三IC晶粒和具有第四晶粒体的第四IC晶粒。第一晶粒体具有有源侧、背侧和集成电路的第一布置。第二晶粒体具有有源侧、背侧和集成电路的第二布置。第一IC晶粒的有源侧被安装到第二IC晶粒的有源侧。集成电路的第二布置是集成电路的第一布置的镜像。第三晶粒体的有源侧耦接到第二IC晶粒的背侧。第四晶粒体具有有源侧和背侧。第四晶粒体的有源侧耦接到第三IC晶粒的背侧。
在第十一示例中,第七示例的晶粒堆叠还可以包括:其上安装有晶粒堆叠的封装基板;以及被安装到封装基板的逻辑晶粒,其被配置为通过布置在封装基板上或封装基板中的布线而与晶粒堆叠的IC晶粒通信。
在第十二示例中,提供了一种用于制造集成电路器件的方法。该方法包括:将第一集成电路(IC)晶粒的有源侧安装到第二IC晶粒的有源侧,第一和第二IC晶粒具有彼此成镜像的集成电路布置;以及将第三IC晶粒安装到第二IC晶粒的背侧。
在第十三示例中,第十二示例的方法还可以包括将第四IC晶粒的有源侧安装到第三IC晶粒的背侧,第三和第四IC晶粒具有互为镜像的集成电路布置。
在第十四示例中,第十三示例的方法还可以包括将第五IC晶粒的有源侧安装到第四IC晶粒的有源侧,第五和第四IC晶粒具有互为镜像的集成电路布置。
在第十五示例中,第十二示例的方法还可以包括将第三IC晶粒的有源侧安装到第四IC晶粒的有源侧,第三和第四IC晶粒具有互为镜像的集成电路布置。
在第十六示例中,第十五示例中的将第三IC晶粒安装到第二IC晶粒的背侧还可以包括在将第三IC晶粒安装到第二IC晶粒之前,将第一IC晶粒安装到第二IC晶粒。
在第十七示例中,第十六示例中的将第三IC晶粒安装到第二IC晶粒的背侧还可以包括在将第三IC晶粒安装到第二IC晶粒之前,将第三IC晶粒安装到第四IC晶粒。
在第十八示例中,第十七示例还可以包括在第一IC晶粒已被安装到第二IC晶粒之后薄化第一IC晶粒。
在第十九示例中,第十七示例还可以包括在将第二IC晶粒已被安装到第三IC晶粒之后,薄化第一IC晶粒和第四IC晶粒中的至少一个。
在第二十示例中,在第十五示例中的第一IC晶粒或第二IC晶粒的集成电路布置是第三IC晶粒的集成电路布置的镜像。
因此,以上已经描述了利用两对或更多对堆叠的集成电路晶粒的集成电路器件及其制造技术,所述两对或更多对堆叠的集成电路晶粒包括布置成镜像的电路以降低制造的复杂性。镜像IC晶粒允许开发单个掩模组并对于一个晶粒进行认证,而第二个掩模组以镜像图像进行制造,而无需发送用于单独的设计和认证,从而大大节省了开发时间和成本。此外,成对的镜像堆叠的集成电路晶粒允许制造具有四个以上的IC晶粒的晶粒堆叠,其中在制造期间所需的载体数量减少。因此,进一步降低了制造集成电路器件所需的成本和时间。因此,与常规制造技术相比,实现了具有显著的成本和生产时间优势的坚固的集成电路器件。
应当指出,即使在仅具有两个镜像的IC晶粒或甚至多于四个镜像的IC晶粒的IC晶粒堆叠中使用,在它们的有源侧进行耦接的镜像晶粒的使用也有利地实现了上述优点。
此外,在不使用具有以镜像布置的功能电路的IC晶粒的情况下,也可以有利地使用能够消除一个或多个载体附接和分离操作的上述制造顺序。
尽管前述内容是针对本发明的实施例,但是在不脱离本发明的基本范围的情况下,可以设计本发明的其他和进一步的实施例,并且本发明的范围由所附权利要求书确定。
Claims (15)
1.一种集成电路器件,其特征在于,所述集成电路器件包括:
集成电路晶粒堆叠,所述集成电路晶粒堆叠包括:
具有第一晶粒体的第一集成电路晶粒,所述第一晶粒体具有有源侧、背侧以及第一集成电路布置;
具有第二晶粒体的第二集成电路晶粒,所述第二晶粒体具有有源侧、背侧以及第二集成电路布置,所述第一集成电路晶粒的有源侧安装到所述第二集成电路晶粒的有源侧,所述第二集成电路布置是所述第一集成电路布置的镜像;
具有第三晶粒体的第三集成电路晶粒,所述第三晶粒体具有有源侧、背侧以及第三集成电路布置;以及
具有第四晶粒体的第四集成电路晶粒,所述第四晶粒体具有有源侧、背侧以及第四集成电路布置,所述第三集成电路晶粒的有源侧安装到所述第四集成电路晶粒的有源侧,所述第四集成电路布置是所述第三集成电路布置的镜像。
2.根据权利要求1所述的集成电路器件,其特征在于,所述集成电路器件还包括:
具有第五晶粒体的第五集成电路晶粒,所述第五晶粒体具有有源侧、背侧以及第五集成电路布置,所述第五集成电路晶粒的背侧安装到所述第四集成电路晶粒的背侧。
3.根据权利要求2所述的集成电路器件,其特征在于,所述集成电路器件还包括:
具有第六晶粒体的第六集成电路晶粒,所述第六晶粒体具有有源侧、背侧以及第六集成电路布置,所述第六集成电路晶粒的有源侧安装到所述第五集成电路晶粒的有源侧。
4.根据权利要求1所述的集成电路器件,其特征在于,所述第二集成电路布置是所述第三集成电路布置或所述第四集成电路布置的镜像。
5.根据权利要求1所述的集成电路器件,其特征在于,所述集成电路器件还包括:
具有第五晶粒体的第五集成电路晶粒,所述第五晶粒体具有有源侧、背侧和第五集成电路布置,所述第五集成电路晶粒设置在所述第二集成电路晶粒和第三集成电路晶粒之间的集成电路晶粒堆叠中。
6.根据权利要求1所述的集成电路器件,其特征在于,所述集成电路晶粒堆叠的所述第一、第二、第三和第四集成电路晶粒是存储器晶粒。
7.根据权利要求1所述的集成电路器件,其特征在于,所述集成电路器件还包括:
其上安装有所述集成电路晶粒堆叠的封装基板;以及
逻辑晶粒,所述逻辑晶粒安装到所述封装基板并被配置为通过布置在所述封装基板上和/或所述封装基板中的布线而与所述集成电路晶粒堆叠的集成电路晶粒通信,其中所述第一、第二、第三和第四集成电路晶粒中的一个或多个集成电路晶粒被薄化。
8.根据权利要求1所述的集成电路器件,其特征在于,所述集成电路器件还包括:
其上安装有所述集成电路晶粒堆叠的封装基板;和
逻辑晶粒,所述逻辑晶粒被安装到所述封装基板并被配置为通过布置在所述封装基板上和/或所述封装基板中的布线而与所述集成电路晶粒堆叠的集成电路晶粒通信,其中所述晶粒堆叠还包括:
具有第五晶粒体的第五集成电路晶粒,所述第五晶粒体具有有源侧、背侧和第五集成电路布置,其中所述第三集成电路晶粒或所述第五集成电路晶粒中的一个集成电路晶粒安装在所述第二集成电路晶粒与所述第四集成电路晶粒之间。
9.一种集成电路器件,其特征在于,所述集成电路器件包括:
集成电路晶粒堆叠,所述集成电路晶粒堆叠包括:
具有第一晶粒体的第一集成电路晶粒,所述第一晶粒体具有有源侧、背侧以及第一集成电路布置;
具有第二晶粒体的第二集成电路晶粒,所述第二晶粒体具有有源侧、背侧以及第二集成电路布置,所述第一集成电路晶粒的有源侧安装到所述第二集成电路晶粒的有源侧,所述第二集成电路布置是所述第一集成电路布置的镜像;
具有第三晶粒体的第三集成电路晶粒,所述第三晶粒体具有有源侧和背侧,所述第三晶粒体的有源侧耦接到所述第二集成电路晶粒的背侧;以及
具有第四晶粒体的第四集成电路晶粒,所述第四晶粒体具有有源侧和背侧,所述第四晶粒体的有源侧耦接到所述第三集成电路晶粒的背侧。
10.根据权利要求1或9所述的集成电路器件,其特征在于,所述集成电路器件还包括:
其上安装有所述晶粒堆叠的封装基板;和
逻辑晶粒,所述逻辑晶粒被安装到所述封装基板并被配置为通过布置在所述封装基板上和/或所述封装基板中的布线而与所述集成电路晶粒堆叠的集成电路晶粒通信。
11.一种用于制造集成电路器件的方法,其特征在于,所述方法包括:
将第一集成电路晶粒的有源侧安装到第二集成电路晶粒的有源侧,所述第一和第二集成电路晶粒具有彼此成镜像的集成电路布置;和
将第三集成电路晶粒安装到所述第二集成电路晶粒的背侧。
12.根据权利要求11所述的方法,其特征在于,所述方法还包括:
将第四集成电路晶粒的有源侧安装到所述第三集成电路晶粒的背侧,所述第三和第四集成电路晶粒具有彼此镜像的集成电路布置;和
将第五集成电路晶粒的有源侧安装到所述第四集成电路晶粒的有源侧,所述第五和第四集成电路晶粒具有彼此成镜像的集成电路布置。
13.根据权利要求11所述的方法,其特征在于,所述方法还包括:
将所述第三集成电路晶粒的有源侧安装到第四集成电路晶粒的有源侧,所述第三和第四集成电路晶粒具有彼此成镜像的集成电路布置;以及
其中,将所述第三集成电路晶粒安装到所述第二集成电路晶粒的背侧还包括:
在将所述第三集成电路晶粒安装到所述第二集成电路晶粒之前,将所述第一集成电路晶粒安装到所述第二集成电路晶粒。
14.根据权利要求13所述的方法,其特征在于,将所述第三集成电路晶粒安装到所述第二集成电路晶粒的背侧还包括:
在将所述第三集成电路晶粒安装到所述第二集成电路晶粒之前,将所述第三集成电路晶粒安装到所述第四集成电路晶粒;和
在所述第一集成电路晶粒已被安装到所述第二集成电路晶粒之后薄化所述第一集成电路晶粒,或者在所述第二集成电路晶粒已被安装到所述第三集成电路晶粒之后薄化所述第一集成电路晶粒和第四集成电路晶粒中的至少一个集成电路晶粒。
15.根据权利要求13所述的方法,其特征在于,所述第一集成电路晶粒或所述第二集成电路晶粒的集成电路布置是所述第三集成电路晶粒的集成电路布置的镜像。
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