JP7278965B2 - 静電気保護回路及びその製造方法、アレイ基板、表示装置 - Google Patents
静電気保護回路及びその製造方法、アレイ基板、表示装置 Download PDFInfo
- Publication number
- JP7278965B2 JP7278965B2 JP2019563387A JP2019563387A JP7278965B2 JP 7278965 B2 JP7278965 B2 JP 7278965B2 JP 2019563387 A JP2019563387 A JP 2019563387A JP 2019563387 A JP2019563387 A JP 2019563387A JP 7278965 B2 JP7278965 B2 JP 7278965B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- signal line
- pole
- array substrate
- protection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims description 85
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004020 conductor Substances 0.000 claims description 84
- 230000003068 static effect Effects 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 30
- 239000010409 thin film Substances 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 15
- 230000005611 electricity Effects 0.000 description 30
- 239000010410 layer Substances 0.000 description 27
- 238000010586 diagram Methods 0.000 description 12
- 239000010408 film Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000010936 titanium Substances 0.000 description 4
- 239000011651 chromium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- NPXOKRUENSOPAO-UHFFFAOYSA-N Raney nickel Chemical class [Al].[Ni] NPXOKRUENSOPAO-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
Description
静電気保護回路の製造方法に関する。
図2は、本開示の実施例による静電気保護回路の等価回路図である。図1および図2に示すように、当該静電気保護回路は、1つの第1トランジスタM1と1つの第2トランジスタM2とを含むことができる。図3は、本開示の実施例による別の静電気保護回路の等価回路図である。図3に示すように、当該静電気保護回路は、2つの第1トランジスタM1と2つの第2トランジスタM2とを含むことができる。
M2 第2トランジスタ
P1 第1信号線
P2 第2信号線
11,21 ゲート
12,22 第1極
13,23 第2極
Claims (19)
- 少なくとも1つの第1トランジスタと少なくとも1つの第2トランジスタとを含み、
前記第1トランジスタのゲートおよび第1極は第1信号線に接続され、前記第1トランジスタの第2極は第2信号線に接続され、
前記第2トランジスタのゲートおよび第1極は前記第2信号線に接続され、前記第2トランジスタの第2極は前記第1信号線に接続され、
ここで、前記第1信号線および前記第2信号線は、アレイ基板上の任意の2つの隣接する信号線であり、
各トランジスタの第1極と第2極の少なくとも一方のチャネルに近い端のアレイ基板上への正射影は、三角形または台形であり、前記三角形の先端は前記チャネルに向かって、前記台形の上底は下底に対して前記チャネルに近い、
静電気保護回路。 - 前記第1トランジスタは、薄膜トランジスタであり、
前記第1トランジスタは、以下の条件の一つを満し、即ち、
前記第1トランジスタのゲートは、前記第1信号線と同層に配置され、
前記第1トランジスタの第1極及び第2極は、前記第1信号線と同層に配置される、
請求項1に記載の静電気保護回路。 - 前記第2トランジスタは、薄膜トランジスタであり、
前記第2トランジスタは、以下の条件の一つを満し、即ち、
前記第2トランジスタのゲートは、前記第2信号線と同層に配置され、
前記第2トランジスタの第1極及び第2極は、前記第2信号線と同層に配置される、
請求項1に記載の静電気保護回路。 - 前記第1トランジスタは薄膜トランジスタであり、
前記第1信号線は、異なる層に配置された第1導線と第2導線とを含み、前記第1導線のリード部分は、リード領域に設けられたオーバーホールによって前記第2導線のリード部分に接続され、
前記第1トランジスタのゲートは前記第1導線のリード部分で構成され、前記第1トランジスタの第1極は前記第2導線のリード部分で構成され、前記第1トランジスタの第2極は前記第2信号線のリード部分で構成される、
請求項1に記載の静電気保護回路。 - 前記第2トランジスタは薄膜トランジスタであり、
前記第2信号線は、異なる層に配置された第3導線と第4導線とを含み、前記第3導線のリード部分は、リード領域に設けられたオーバーホールによって前記第4導線のリード部分に接続され、
前記第2トランジスタのゲートは前記第3導線のリード部分で構成され、前記第2トランジスタの第1極は前記第4導線のリード部分で構成され、前記第2トランジスタの第2極は前記第1信号線のリード部分で構成される、
請求項1に記載の静電気保護回路。 - 各トランジスタのチャネルのアスペクト比は1/4以下である、
請求項1から5のいずれか1項に記載の静電気保護回路。 - 各トランジスタのチャネルの前記アレイ基板上への正射影は、曲折された蛇行形状である、
請求項1から5のいずれか1項に記載の静電気保護回路。 - 前記第1トランジスタは、以下の条件の一つを満し、即ち、
前記第1トランジスタのチャネルの前記アレイ基板上への正射影は、前記第1信号線の前記アレイ基板上への正射影内にあり、
前記第1トランジスタの第1極の前記アレイ基板上への正射影は、前記第1信号線の前記アレイ基板上への正射影内にある、
請求項1から5のいずれか1項に記載の静電気保護回路。 - 前記第2トランジスタは、以下の条件の一つを満し、即ち、
前記第2トランジスタのチャネルの前記アレイ基板上への正射影は、前記第2信号線の前記アレイ基板上への正射影内にあり、
前記第2トランジスタの第1極の前記アレイ基板上への正射影は、前記第2信号線の前記アレイ基板上への正射影内にある、
請求項1から5のいずれか1項に記載の静電気保護回路。 - 各トランジスタのチャネルの第1極に近い端のアレイ基板上への正射影は、三角形または台形であり、前記三角形の先端は前記第1極に向かって、前記台形の上底は下底に対して前記第1極に近い、
請求項1から5のいずれか1項に記載の静電気保護回路。 - 各トランジスタのチャネルの第2極に近い端のアレイ基板上への正射影は、三角形または台形であり、前記三角形の先端は前記第2極に向かって、前記台形の上底は下底に対して前記第2極に近い、
請求項1から5のいずれか1項に記載の静電気保護回路。 - 各トランジスタのチャネルの第1極に近い端のアレイ基板上への正射影は、三角形または台形であり、前記三角形の先端は前記第1極に向かって、前記台形の上底は下底に対して前記第1極に近く、
各トランジスタのチャネルの第2極に近い端のアレイ基板上への正射影は、三角形または台形であり、前記三角形の先端は前記第2極に向かって、前記台形の上底は下底に対して前記第2極に近い、
請求項1から5のいずれか1項に記載の静電気保護回路。 - 少なくとも1つの第1トランジスタと少なくとも1つの第2トランジスタを形成することを含み、
ここで、前記第1トランジスタのゲートおよび第1極は第1信号線に接続され、前記第1トランジスタの第2極は第2信号線に接続され、前記第2トランジスタのゲートおよび第1極は前記第2信号線に接続され、前記第2トランジスタの第2極は前記第1信号線に接続され、前記第1信号線および前記第2信号線は、アレイ基板上の任意の2つの隣接する信号線であり、
各トランジスタの第1極と第2極の少なくとも一方のチャネルに近い端のアレイ基板上への正射影は、三角形または台形であり、前記三角形の先端は前記チャネルに向かって、前記台形の上底は下底に対して前記チャネルに近い、
静電気保護回路の製造方法。 - 静電気保護回路の製造方法であって、
前記第1トランジスタは、薄膜トランジスタであり、
前記第1トランジスタは、以下の条件の一つを満し、即ち、
各前記第1トランジスタのゲートと前記第1信号線は、一次パターニングプロセスによって形成され、
前記第1トランジスタの第1極及び第2極と前記第1信号線は、一次パターニングプロセスによって形成される、
請求項13に記載の方法。 - 静電気保護回路の製造方法であって、
前記第2トランジスタは、薄膜トランジスタであり、
前記第2トランジスタは、以下の条件の一つを満し、即ち、
前記第2トランジスタのゲートと前記第2信号線は、一次パターニングプロセスによって形成され、
前記第2トランジスタの第1極及び第2極と前記第2信号線は、一次パターニングプロセスによって形成される、
請求項13に記載の方法。 - 静電気保護回路の製造方法であって、
各前記第1トランジスタは薄膜トランジスタであり、
前記第1信号線は、異なる層に形成された第1導線と第2導線とを含み、前記第1導線のリード部分は、リード領域に形成されたオーバーホールによって前記第2導線のリード部分に接続され、
各前記第1トランジスタのゲートは前記第1導線のリード部分で形成され、各前記第1トランジスタの第1極は前記第2導線のリード部分で形成され、各前記第1トランジスタの第2極は前記第2信号線のリード部分で形成される、
請求項13に記載の方法。 - 請求項1から12のいずれか1項に記載の静電気保護回路を含む、
アレイ基板。 - 前記アレイ基板上に複数の信号線が配置され、前記複数の信号線のうち、2つの隣接する信号線の間に前記静電気保護回路が配置される、
請求項17に記載のアレイ基板。 - 請求項17または請求項18に記載のアレイ基板を含む、
表示装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2023077361A JP2023103336A (ja) | 2017-10-23 | 2023-05-09 | 静電気保護回路、アレイ基板、及び表示装置 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710994724.6A CN109698192B (zh) | 2017-10-23 | 2017-10-23 | 静电保护电路、阵列基板及显示装置 |
CN201710994724.6 | 2017-10-23 | ||
PCT/CN2018/098275 WO2019080577A1 (zh) | 2017-10-23 | 2018-08-02 | 静电保护电路、阵列基板及显示装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2023077361A Division JP2023103336A (ja) | 2017-10-23 | 2023-05-09 | 静電気保護回路、アレイ基板、及び表示装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2021500736A JP2021500736A (ja) | 2021-01-07 |
JP2021500736A5 JP2021500736A5 (ja) | 2021-09-09 |
JP7278965B2 true JP7278965B2 (ja) | 2023-05-22 |
Family
ID=66225976
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019563387A Active JP7278965B2 (ja) | 2017-10-23 | 2018-08-02 | 静電気保護回路及びその製造方法、アレイ基板、表示装置 |
JP2023077361A Pending JP2023103336A (ja) | 2017-10-23 | 2023-05-09 | 静電気保護回路、アレイ基板、及び表示装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2023077361A Pending JP2023103336A (ja) | 2017-10-23 | 2023-05-09 | 静電気保護回路、アレイ基板、及び表示装置 |
Country Status (5)
Country | Link |
---|---|
US (2) | US11495594B2 (ja) |
EP (1) | EP3703125B1 (ja) |
JP (2) | JP7278965B2 (ja) |
CN (1) | CN109698192B (ja) |
WO (1) | WO2019080577A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20220026172A (ko) * | 2020-08-25 | 2022-03-04 | 엘지디스플레이 주식회사 | 디스플레이 장치 |
WO2023127165A1 (ja) * | 2021-12-29 | 2023-07-06 | シャープディスプレイテクノロジー株式会社 | 表示装置 |
TWI820876B (zh) * | 2022-08-23 | 2023-11-01 | 友達光電股份有限公司 | 顯示裝置及檢測其之檢測方法 |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050151462A1 (en) | 2003-12-17 | 2005-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
JP2005203351A (ja) | 2003-12-17 | 2005-07-28 | Semiconductor Energy Lab Co Ltd | 表示装置及びその作製方法 |
US20100065887A1 (en) | 2008-09-15 | 2010-03-18 | Andreas Goebel | Field effect transistor source or drain with a multi-facet surface |
CN202550507U (zh) | 2012-03-15 | 2012-11-21 | 京东方科技集团股份有限公司 | 静电保护电路、阵列基板及显示装置 |
US20130207115A1 (en) | 2010-09-21 | 2013-08-15 | Sharp Kabushiki Kaisha | Semiconductor device and process for production thereof |
WO2014054483A1 (ja) | 2012-10-02 | 2014-04-10 | シャープ株式会社 | 半導体装置及び表示装置 |
JP2015046561A (ja) | 2012-11-28 | 2015-03-12 | 株式会社半導体エネルギー研究所 | 表示装置 |
CN105304645A (zh) | 2015-10-16 | 2016-02-03 | 京东方科技集团股份有限公司 | 一种阵列基板、其静电释放方法及相应装置 |
CN105810677A (zh) | 2016-05-16 | 2016-07-27 | 京东方科技集团股份有限公司 | 静电释放组件、阵列基板及其制备方法、显示面板 |
CN205450520U (zh) | 2016-04-06 | 2016-08-10 | 京东方科技集团股份有限公司 | 阵列基板和显示装置 |
WO2017128738A1 (en) | 2016-01-25 | 2017-08-03 | Boe Technology Group Co., Ltd. | Substrate and display device containing the same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4961819B2 (ja) * | 2006-04-26 | 2012-06-27 | 株式会社日立製作所 | 電界効果トランジスタ及びその製造方法 |
KR100878439B1 (ko) * | 2007-08-30 | 2009-01-13 | 주식회사 실리콘웍스 | 출력 드라이버단의 esd 보호 장치 |
CN202332851U (zh) * | 2011-11-22 | 2012-07-11 | 京东方科技集团股份有限公司 | 一种静电保护电路、阵列基板和液晶显示器 |
US9172244B1 (en) * | 2012-03-08 | 2015-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self biased electro-static discharge clamp (ESD) for power rail |
KR101661015B1 (ko) * | 2013-11-28 | 2016-09-28 | 엘지디스플레이 주식회사 | 대면적 유기발광 다이오드 표시장치 |
CN104113053B (zh) * | 2014-04-21 | 2017-05-24 | 京东方科技集团股份有限公司 | 静电放电保护电路、显示基板和显示装置 |
CN105448224B (zh) * | 2015-12-31 | 2018-05-25 | 上海中航光电子有限公司 | 显示面板及显示装置 |
CN205810810U (zh) * | 2016-07-26 | 2016-12-14 | 京东方科技集团股份有限公司 | 一种静电保护电路、阵列基板及显示装置 |
-
2017
- 2017-10-23 CN CN201710994724.6A patent/CN109698192B/zh active Active
-
2018
- 2018-08-02 JP JP2019563387A patent/JP7278965B2/ja active Active
- 2018-08-02 US US16/340,186 patent/US11495594B2/en active Active
- 2018-08-02 EP EP18865335.6A patent/EP3703125B1/en active Active
- 2018-08-02 WO PCT/CN2018/098275 patent/WO2019080577A1/zh unknown
-
2022
- 2022-08-29 US US17/897,302 patent/US20240072039A1/en active Pending
-
2023
- 2023-05-09 JP JP2023077361A patent/JP2023103336A/ja active Pending
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050151462A1 (en) | 2003-12-17 | 2005-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
JP2005203351A (ja) | 2003-12-17 | 2005-07-28 | Semiconductor Energy Lab Co Ltd | 表示装置及びその作製方法 |
US20100065887A1 (en) | 2008-09-15 | 2010-03-18 | Andreas Goebel | Field effect transistor source or drain with a multi-facet surface |
US20130207115A1 (en) | 2010-09-21 | 2013-08-15 | Sharp Kabushiki Kaisha | Semiconductor device and process for production thereof |
JP2013251284A (ja) | 2010-09-21 | 2013-12-12 | Sharp Corp | 半導体装置およびその製造方法 |
CN202550507U (zh) | 2012-03-15 | 2012-11-21 | 京东方科技集团股份有限公司 | 静电保护电路、阵列基板及显示装置 |
US20150221680A1 (en) | 2012-10-02 | 2015-08-06 | Sharp Kabushiki Kaisha | Semiconductor device and display device |
WO2014054483A1 (ja) | 2012-10-02 | 2014-04-10 | シャープ株式会社 | 半導体装置及び表示装置 |
JP2015046561A (ja) | 2012-11-28 | 2015-03-12 | 株式会社半導体エネルギー研究所 | 表示装置 |
CN109449170A (zh) | 2012-11-28 | 2019-03-08 | 株式会社半导体能源研究所 | 显示装置 |
CN105304645A (zh) | 2015-10-16 | 2016-02-03 | 京东方科技集团股份有限公司 | 一种阵列基板、其静电释放方法及相应装置 |
US20170110478A1 (en) | 2015-10-16 | 2017-04-20 | Boe Technology Group Co., Ltd. | Array substrate, electro-static discharge method thereof and display device |
WO2017128738A1 (en) | 2016-01-25 | 2017-08-03 | Boe Technology Group Co., Ltd. | Substrate and display device containing the same |
CN205450520U (zh) | 2016-04-06 | 2016-08-10 | 京东方科技集团股份有限公司 | 阵列基板和显示装置 |
US20180204829A1 (en) | 2016-04-06 | 2018-07-19 | Boe Technology Group Co., Ltd. | Array substrate and display device |
CN105810677A (zh) | 2016-05-16 | 2016-07-27 | 京东方科技集团股份有限公司 | 静电释放组件、阵列基板及其制备方法、显示面板 |
US20180204830A1 (en) | 2016-05-16 | 2018-07-19 | Boe Technology Group Co., Ltd. | Electro-static discharge assembly, array substrate and fabrication method thereof, and display panel |
Also Published As
Publication number | Publication date |
---|---|
EP3703125A4 (en) | 2021-07-28 |
JP2023103336A (ja) | 2023-07-26 |
JP2021500736A (ja) | 2021-01-07 |
US20210398970A1 (en) | 2021-12-23 |
US11495594B2 (en) | 2022-11-08 |
CN109698192A (zh) | 2019-04-30 |
EP3703125A1 (en) | 2020-09-02 |
US20240072039A1 (en) | 2024-02-29 |
EP3703125B1 (en) | 2023-11-22 |
WO2019080577A1 (zh) | 2019-05-02 |
CN109698192B (zh) | 2021-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106684155B (zh) | 双栅薄膜晶体管及其制备方法、阵列基板及显示装置 | |
JP2023103336A (ja) | 静電気保護回路、アレイ基板、及び表示装置 | |
CN108803173B (zh) | 阵列基板及其制造方法、显示装置 | |
US9230951B2 (en) | Antistatic device of display device and method of manufacturing the same | |
US9711544B2 (en) | Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, display device | |
US11562997B2 (en) | Electrostatic protection circuit, array substrate and display apparatus | |
JP2015504533A (ja) | 表示装置、薄膜トランジスター、アレイ基板及びその製造方法 | |
US9588389B2 (en) | Array substrate and method for manufacturing the same, and display device | |
WO2013155830A1 (zh) | 阵列基板的制造方法、阵列基板及显示装置 | |
US10141345B2 (en) | Array substrate, manufacturing method thereof, and display device | |
US8164094B2 (en) | Pixel structure and fabricating method thereof | |
US9740053B2 (en) | Array substrate, fabrication method thereof, and display device | |
JP2006338008A (ja) | 開口率が向上したアレイ基板、その製造方法及びそれを含む表示装置。 | |
US9741746B2 (en) | Array substrate, manufacturing method thereof and display device | |
US10381384B2 (en) | Array substrate, method for manufacturing array substrate, display panel and display device | |
US20160181278A1 (en) | Array substrate, method for manufacturing the same, and display device | |
CN109613772B (zh) | 显示基板及其制造方法、修复方法、显示装置 | |
KR102102903B1 (ko) | 박막 트랜지스터 어레이 기판 및 이의 제조 방법 | |
US11901354B2 (en) | Array substrate, manufacturing method thereof and display device | |
US10763283B2 (en) | Array substrate, manufacturing method thereof, display panel and manufacturing method thereof | |
KR20110070607A (ko) | 유기발광다이오드 표시장치 및 이의 제조 방법 | |
JP2016134469A (ja) | 薄膜トランジスタの製造方法 | |
CN106298808B (zh) | 阵列基板及其制造方法、显示装置 | |
US11927858B2 (en) | Array substrate and display device | |
KR20080049256A (ko) | 액정표시장치 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210802 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210802 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20220823 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220912 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20221207 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20230410 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20230510 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7278965 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |