WO2019080577A1 - 静电保护电路、阵列基板及显示装置 - Google Patents

静电保护电路、阵列基板及显示装置

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Publication number
WO2019080577A1
WO2019080577A1 PCT/CN2018/098275 CN2018098275W WO2019080577A1 WO 2019080577 A1 WO2019080577 A1 WO 2019080577A1 CN 2018098275 W CN2018098275 W CN 2018098275W WO 2019080577 A1 WO2019080577 A1 WO 2019080577A1
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WIPO (PCT)
Prior art keywords
transistor
signal line
pole
array substrate
wire
Prior art date
Application number
PCT/CN2018/098275
Other languages
English (en)
French (fr)
Inventor
龙春平
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2019563387A priority Critical patent/JP7278965B2/ja
Priority to US16/340,186 priority patent/US11495594B2/en
Priority to EP18865335.6A priority patent/EP3703125B1/en
Publication of WO2019080577A1 publication Critical patent/WO2019080577A1/zh
Priority to US17/897,302 priority patent/US20240072039A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere

Definitions

  • the present disclosure relates to an electrostatic protection circuit, an array substrate, and a display device.
  • the signal lines disposed on the array substrate of the display device become denser and denser, and the spacing between adjacent signal lines is also smaller and smaller, so that the adjacent signal lines are also more Defects such as leakage or short circuit caused by static electricity are prone to occur.
  • an electrostatic protection device connected to the signal line is disposed on the array substrate.
  • the electrostatic protection device in the related art generally includes a plurality of transistors and at least one electrostatic protection wire such as a common electrode wire or a short-circuit ring or the like. Each transistor can be respectively connected to a signal line and the static protection line to discharge static electricity generated on the signal line to the static protection line in time.
  • the electrostatic protection device in the related art needs to additionally arrange an electrostatic protection line on the array substrate, which results in a large space occupied by the electrostatic protection device, which is disadvantageous for the realization of the narrow bezel display panel.
  • the present disclosure provides an electrostatic protection circuit, an array substrate, and a display device.
  • the technical solutions are as follows:
  • an electrostatic protection circuit including: at least one first transistor and at least one second transistor; a gate and a first pole of the first transistor are connected to a first signal line, a second pole of the first transistor is connected to the second signal line; a gate and a first pole of the second transistor are connected to the second signal line, and a second pole of the second transistor is opposite to the first The signal line is connected; wherein the first signal line and the second signal line are any two adjacent signal lines on the array substrate.
  • the first transistor and the second transistor are thin film transistors; a gate of the first transistor is disposed in the same layer as the first signal line; a gate of the second transistor is The second signal line is set in the same layer.
  • the first transistor and the second transistor are thin film transistors; the first and second poles of the first transistor are disposed in the same layer as the first signal line; and the second transistor is The first pole and the second pole are disposed in the same layer as the second signal line.
  • the first transistor is a thin film transistor;
  • the first signal line includes a first wire and a second wire disposed in different layers, and a lead portion of the first wire passes through a via hole disposed in the lead region a lead portion of the second wire is connected;
  • a gate of the first transistor is formed by a lead portion of the first wire, and a first electrode of the first transistor is formed by a lead portion of the second wire
  • the second pole of the first transistor is formed by a lead portion of the second signal line.
  • the second transistor is a thin film transistor;
  • the second signal line includes a third wire and a fourth wire disposed in different layers, and a lead portion of the third wire passes through a via hole disposed in the lead region a lead portion of the fourth wire is connected;
  • a gate of the second transistor is formed by a lead portion of the third wire, and a first electrode of the second transistor is formed by a lead portion of the fourth wire
  • the second pole of the second transistor is formed by a lead portion of the first signal line.
  • the width to length ratio of the channel of each transistor is less than or equal to a quarter.
  • the orthographic projection of the channel of each transistor on the array substrate is a meandering serpentine shape.
  • an orthographic projection of a channel of the first transistor on the array substrate is located in an orthographic projection of the first signal line in the array substrate; a channel of the second transistor is in the array An orthographic projection on the substrate is located within the orthographic projection of the second signal line within the array substrate.
  • an orthographic projection of the first pole of the first transistor on the array substrate is located in an orthographic projection of the first signal line in the array substrate; a first pole of the second transistor is in the An orthographic projection on the array substrate is located in the orthographic projection of the second signal line in the array substrate.
  • an orthographic projection of at least one of the first pole and the second pole of each transistor near the end of the channel on the array substrate is triangular or trapezoidal, and a tip end of the triangle faces the channel,
  • the upper base of the trapezoid is adjacent to the channel with respect to the lower base.
  • the orthographic projection of the end of the transistor adjacent to the first pole on the array substrate is triangular or trapezoidal, the tip end of the triangle faces the first pole, and the upper base of the trapezoid is opposite to the bottom Adjacent to the first pole; and/or an orthographic projection of an end of each transistor near the second pole on the array substrate is triangular or trapezoidal, the tip of the triangle facing the second pole, the trapezoid
  • the upper base is adjacent to the second pole with respect to the lower base.
  • a method of fabricating an electrostatic protection circuit comprising:
  • the signal line is any two adjacent signal lines on the array substrate.
  • the first transistor and the second transistor are thin film transistors; a gate of the first transistor and the first signal line are formed by one patterning process; a gate of the second transistor is The second signal line is formed by one patterning process.
  • the first transistor and the second transistor are both thin film transistors; the first and second poles of the first transistor and the first signal line are formed by one patterning process; the second The first and second poles of the transistor and the second signal line are formed by one patterning process.
  • the first transistor is a thin film transistor;
  • the first signal line includes a first wire and a second wire formed on different layers, and a lead portion of the first wire passes through a via formed in the lead region a lead portion of the second wire is connected;
  • a gate of the first transistor is formed by a lead portion of the first wire, and a first electrode of the first transistor is formed by a lead portion of the second wire
  • the second pole of the first transistor is formed by a lead portion of the second signal line.
  • an array substrate comprising: the electrostatic protection circuit of the above aspect.
  • the array substrate is provided with a plurality of signal lines, and the electrostatic protection circuit is disposed between each two adjacent ones of the plurality of signal lines.
  • a display device comprising: the array substrate of the above aspect.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a flow chart of a method for manufacturing an electrostatic protection circuit according to an embodiment of the present disclosure.
  • the transistors employed in the embodiments of the present disclosure may all be thin film transistors, and the transistors employed in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiments of the present disclosure, the source may be referred to as a first pole and the drain as a second pole. Alternatively, the source may be referred to as a second pole and the drain as a first pole. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • Embodiments of the present disclosure provide an electrostatic protection circuit that can be applied to an array substrate.
  • the electrostatic protection circuit can include at least one first transistor and at least one second transistor.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the present disclosure.
  • 2 is an equivalent circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure.
  • the first protection transistor M1 and a second transistor M2 may be included in the electrostatic protection circuit.
  • FIG. 3 is an equivalent circuit diagram of another electrostatic protection circuit according to an embodiment of the present disclosure. As shown in FIG. 3, the first protection transistor M1 and the two second transistors M2 may be included in the electrostatic protection circuit.
  • the gate 11 and the first pole 12 of the first transistor M1 are connected to the first signal line P1, and the second pole 13 of the first transistor M1 is connected to the second signal line P2.
  • the gate 21 and the first pole 22 of the second transistor M2 are connected to the second signal line P2, and the second pole 23 of the second transistor M2 is connected to the first signal line P1.
  • the first signal line P1 and the second signal line P2 may be any two adjacent signal lines on the array substrate.
  • the at least one first transistor M1 is turned on, and the first signal line P1 is connected to the second signal line P2, so that the static electricity generated on the first signal line P1 can be released.
  • the second signal line P2 Up to the second signal line P2.
  • the at least one second transistor M2 is turned on, and the second signal line P2 is connected to the first signal line P1, so that the second signal line P2 can be generated.
  • the static electricity is discharged to the first signal line P1. Thereby, it is possible to release the static electricity accumulated on the signal line to the adjacent signal line, thereby reducing the probability that the static electricity causes a defect such as a short circuit of the signal line.
  • the electrostatic protection circuit when the first protection transistor M1 and the second transistor M2 are included in the electrostatic protection circuit, the electrostatic protection circuit has a simple structure and a small occupied area.
  • the plurality of first transistors M1 and the plurality of second transistors M2 when one of the first transistors or a certain second transistor fails, the other transistors can also ensure that the electrostatic protection circuit works normally. Therefore, the reliability of the electrostatic protection circuit can be effectively improved.
  • the number of the first transistor and the second transistor in the electrostatic protection circuit can be flexibly selected according to the application requirements, which is not limited in the embodiment of the present disclosure.
  • the electrostatic protection circuit includes: at least one first transistor and at least one second transistor, the gate and the first pole of the first transistor are connected to the first signal line, and the first transistor is The two poles are connected to the second signal line.
  • the gate and the first pole of the second transistor are connected to the second signal line, and the second pole of the second transistor is connected to the first signal line. Therefore, when static electricity is generated on any one of the first signal line and the second signal line, the transistor connected to the static generating signal line can discharge the static electricity to the other signal line, thereby realizing effective static electricity. Release, thereby reducing the probability that static electricity will cause defects such as short circuits on the signal line.
  • the electrostatic protection circuit does not need to be additionally wired on the array substrate, and takes up less space, which is beneficial to the realization of the narrow bezel display panel.
  • the first transistor M1 and the second transistor M2 may both be thin film transistors.
  • the gate 11 of the first transistor M1 may be disposed in the same layer as the first signal line P1.
  • the gate 21 of the second transistor M2 can also be disposed in the same layer as the second signal line P2.
  • first pole 12 and the second pole 13 of the first transistor M1 may be disposed in the same layer as the first signal line P1.
  • the first pole 22 and the second pole 23 of the second transistor M2 may also be disposed in the same layer as the second signal line P2.
  • the gate 11 and the first pole 12 of the first transistor M1 are both part of the first signal line P1
  • the gate 21 and the first pole 22 of the second transistor M2 are both A portion of the second signal line P2. This can avoid extra space occupied by each transistor and improve the space utilization of the array substrate.
  • the electrostatic protection circuit provided by the embodiment of the present disclosure may be disposed in a non-display area of the array substrate.
  • it may be disposed in a lead region (also referred to as a fan-out region) of the array substrate, and the lead region is provided with lead portions of the respective signal lines.
  • the first signal line P1 may include a first wire P11 and a second wire P12 disposed in different layers.
  • the lead portion of the first wire P11 is connected to the lead portion of the second wire P12 through a via hole 14 provided in the lead portion.
  • a conductive layer 15 may be formed in the via hole 14.
  • the lead portion of the second wire P12 is connected to the conductive layer 15.
  • the conductive layer 15 is connected to the first wire P11, thereby implementing the second wire P12.
  • the conductive layer 15 may be made of indium tin oxide (ITO).
  • the gate 11 of the first transistor M1 may be formed by a lead portion of the first wire P11, and the first electrode 12 of the first transistor M1 may be formed by a lead portion of the second wire P12, and the second electrode 13 of the first transistor M1 It may be constituted by a lead portion of the second signal line P2.
  • the second signal line P2 may also include a third wire P21 and a fourth wire P22 disposed in different layers.
  • the lead portion of the third wire P21 is connected to the lead portion of the fourth wire P22 through a via hole 24 provided in the lead portion.
  • a conductive layer 25 (for example, an ITO layer) is formed in the via hole 24, and a lead portion of the fourth wire P22 is connected to the conductive layer 25, and the conductive layer 25 is connected to the third wire P21, thereby achieving the An effective connection of the four wires P22 to the third wire P21.
  • the gate 21 of the second transistor M2 may be formed by the lead portion of the third wire P21, the first electrode 22 of the second transistor M2 may be formed by the lead portion of the fourth wire P22, and the second electrode 23 of the second transistor may be It is composed of a lead portion of the first signal line P1.
  • the first wire P11 of the first signal line P1 and the third wire P21 of the second signal line P2 may be disposed in the same layer, and the second wire P12 of the first signal line P1 and the second wire
  • the fourth wire P22 of the signal line P2 may be disposed in the same layer.
  • the second electrode 13 of the first transistor M1 may be formed by the lead portion of the fourth wire P22
  • the second electrode 23 of the second transistor M2 may be formed by the lead portion of the second wire P12. .
  • the second wire P12 may be located on a side of the first wire P11 away from the array substrate, and the fourth wire P22 is also located on the third wire P21. Keep away from the side of the array substrate. If the transistors in the electrostatic protection circuit are transistors of a top gate structure, the second wire P12 may be located on a side of the first wire P11 adjacent to the array substrate, and the fourth wire P22 is also located on a side of the third wire P21 adjacent to the array substrate.
  • the relative positional relationship of the two segments of the wires in each of the signal lines can be adaptively adjusted according to the specific structure of the transistor, which is not limited in the embodiment of the present disclosure.
  • each of the wires in each of the signal lines may include a lead portion located in the lead region and a wire portion extending toward the peripheral region.
  • the first wire P11 of the first signal line P1 may include a lead portion P111 located in the lead region, and a wire portion extending to a peripheral region (eg, a crimp region, also referred to as a PAD region).
  • the second wire P12 may include a lead portion P121 located in the lead portion, and a wire portion P122 extending toward the peripheral region.
  • the third wire P21 of the second signal line P2 may include a lead portion P211 and a wire portion P212
  • the fourth wire P22 may include a lead portion P221 and a wire portion P222.
  • one of the wires of each of the signal lines may include a lead portion located in the lead region and a wire portion extending toward the peripheral region.
  • the other wire may include only the lead portion located in the lead region.
  • the first wire P11 of the first signal line P1 may include only the lead portion located in the lead region, and the second wire P12 may include the lead portion P121 located in the lead region, and A wire portion P122 in which the peripheral region extends.
  • the third wire P21 of the second signal line P2 may include only the lead portion, and the fourth wire P22 may include the lead portion P221 and the wire portion P222.
  • the first wire P11 of the first signal line P1 may include a lead portion P111 located in the lead region, and a wire portion P112 extending to the peripheral region; and the second wire P12 may include only The lead portion located in the lead area.
  • the third wire P21 of the second signal line P2 may include the lead portion P211 and the wire portion P212, and the fourth wire P22 includes only the lead portion.
  • the width to length ratio of the channel of each transistor may be less than or equal to a quarter.
  • the aspect ratio of the channel may refer to the ratio of the width of the channel to the length of the channel, and the leakage current of the transistor is proportional to the width to length ratio of the transistor channel, that is, the larger the aspect ratio of the channel, the transistor The leakage current is greater.
  • the leakage current of each transistor in the electrostatic protection circuit can be effectively reduced, that is, the output of each transistor is reduced to the phase.
  • the current of the adjacent signal line can effectively improve the electrostatic protection capability of the electrostatic protection circuit.
  • the orthographic projection of the channel of each transistor on the array substrate may be a curved serpentine shape. Therefore, when the channel width is constant, the length of the channel can be effectively increased, thereby effectively reducing the aspect ratio of the channel and reducing the leakage current of the transistor.
  • a top view of the channel of each transistor is shown in FIG. As can be seen from FIG. 1, the channel 16 of the first transistor M1 and the channel 26 of the second transistor M2 each have a meandering serpentine shape.
  • the orthographic projection of the channel 16 of the first transistor M1 on the array substrate can be located within the orthographic projection of the first signal line P1 within the array substrate.
  • the orthographic projection of the channel 26 of the second transistor M2 on the array substrate may also be located in the orthographic projection of the second signal line P2 within the array substrate.
  • the orthographic projection of the first pole 12 of the first transistor M1 on the array substrate may be located in the orthographic projection of the first signal line P1 in the array substrate.
  • the orthographic projection of the first pole 22 of the second transistor M2 on the array substrate may also be located in the orthographic projection of the second signal line P2 in the array substrate.
  • the transistor in the electrostatic protection circuit can be prevented from occupying too much space, effectively improving the space utilization ratio of the array substrate, and facilitating the narrow frame.
  • an orthographic projection of at least one of the first pole and the second pole of each transistor near the end of the channel on the array substrate may be triangular or trapezoidal, and the tip of the triangle Facing the channel, the upper base of the trapezoid is adjacent to the channel with respect to the lower base.
  • FIG. 7 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • the orthographic projections of the first pole and the second pole of each transistor near the channel on the array substrate are all triangular, that is, the first pole and the second pole of each transistor are close to one end of the channel. They are all tip-shaped, so the leakage current when each transistor is turned on is small.
  • the orthographic projection of the channel of each transistor near the first pole on the array substrate may be triangular or trapezoidal, and the tip end of the triangle faces the first pole, and the upper base of the trapezoid is close to the bottom.
  • the first pole the orthographic projection of the channel of each transistor near the second pole on the array substrate may also be triangular or trapezoidal, and the tip end of the triangle faces the second pole, and the upper base of the trapezoid is close to the lower bottom.
  • the second pole thereby, the contact area of the transistor channel with the first pole and the contact area of the channel with the second pole can be further reduced, thereby further reducing the leakage current when the transistor is turned on.
  • the orthographic projection of the end of each transistor near the first pole on the array substrate, and the orthographic projection of the end near the second pole on the array substrate are triangular, thus each When the transistor is turned on, the leakage current is small, and the electrostatic protection circuit has a strong electrostatic protection capability.
  • the embodiments of the present disclosure provide an electrostatic protection circuit including at least one first transistor and at least one second transistor disposed between two adjacent signal lines, the first transistor capable of The static electricity generated by the first signal line is released to the second signal line, and the second transistor is capable of releasing the static electricity generated by the second signal line to the first signal line, thereby effectively avoiding defects such as short circuit caused by static electricity, and
  • the electrostatic protection circuit does not need to be additionally wired on the array substrate, and takes up less space, which is beneficial to the realization of the narrow bezel display panel.
  • FIG. 9 is a flowchart of a method of manufacturing an electrostatic protection circuit according to an embodiment of the present disclosure.
  • the method can be used to manufacture the electrostatic protection circuit provided by the above embodiments.
  • the method can include the following work process:
  • step 101 a substrate is provided.
  • the base substrate may be a transparent glass substrate.
  • step 102 at least one first transistor and at least one second transistor are formed on the base substrate.
  • the gate and the first pole of the first transistor are connected to the first signal line, and the second pole of the first transistor is connected to the second signal line.
  • the gate and the first pole of the second transistor are connected to the second signal line, and the second pole of the second transistor is connected to the first signal line.
  • the first signal line and the second signal line may be any two adjacent signal lines on the array substrate.
  • the first transistor and the second transistor in the electrostatic protection circuit may be thin film transistors.
  • the gate of the first transistor may be formed by the one-time patterning process with the first signal line.
  • the gate of the second transistor may be formed by the one-time patterning process with the second signal line.
  • the gates of the respective first transistors can be formed by one patterning process.
  • the first pole and the second pole of the first transistor may be formed by a patterning process with the first signal line.
  • the first and second poles of the second transistor may be formed by the one patterning process with the second signal line.
  • the first pole and the second pole of each transistor can be formed by one patterning process.
  • a metal thin film may be first formed on the substrate by magnetron sputtering or evaporation. The metal film can then be patterned using a photolithography process to form the gates of the individual transistors and the individual signal lines.
  • the lithography process may include steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • the material of the metal thin film may be a film layer formed of a low-resistance metal material, and may be, for example, molybdenum (Mo), aluminum (Al), aluminum-nickel alloy, chromium (Cr) or copper (Cu), titanium (Ti).
  • Mo molybdenum
  • Al aluminum
  • Al-nickel alloy chromium
  • Cu copper
  • Ti titanium
  • the first signal line may include a first wire and a second wire formed on different layers, and a lead portion of the first wire may be connected to a lead portion of the second wire through a via formed in the lead region.
  • a gate of the first transistor may be formed by a lead portion of the first wire
  • a first pole of the first transistor may be formed by a lead portion of the second wire
  • a second pole of the first transistor may be formed by the second signal line The lead portion is formed.
  • the second signal line may also include a third wire and a fourth wire disposed in different layers, and the lead portion of the third wire may pass through a via hole disposed in the lead region The lead portions of the fourth wire are connected.
  • a gate of the second transistor is formed by a lead portion of the third wire, a first electrode of the second transistor is formed by a lead portion of the fourth wire, and a second electrode of the second transistor is formed by a lead portion of the first signal line .
  • the materials forming the first and second poles of each transistor may be similar to the material forming the gate, and the manufacturing process of forming the first and second poles of each transistor may also be combined with forming the gate. The manufacturing process is similar and will not be described here.
  • An embodiment of the present disclosure provides an array substrate, which may include an electrostatic protection circuit as shown in any of FIGS. 1 to 8.
  • a plurality of signal lines may be disposed on the array substrate.
  • an electrostatic protection circuit can be disposed between every two adjacent signal lines of the plurality of signal lines. If a signal line is adjacent to two signal lines respectively, two transistors may be disposed in a region covered by the signal line, and the two transistors are respectively connected to an adjacent signal line.
  • a second transistor M2 and a first transistor M1 are disposed in a region covered by the second signal line P2.
  • the second transistor M2 is for connecting the first signal line P1 on the left side of the second signal line P2
  • the first transistor M1 is for connecting the signal line on the right side of the second signal line P2.
  • the gate connected to the electrostatically generated signal line can be turned on, and the static generated signal line is adjacent to the adjacent one.
  • the signal lines are connected to discharge static electricity to the adjacent signal lines. If the static electricity is discharged from the signal line that generates static electricity, the transistor whose gate is connected to the adjacent signal line can also be driven to turn on, thereby releasing the static electricity to another signal line until a certain signal line is released. The static electricity can no longer drive the transistor to turn on. Thereby, the effective release of static electricity on each signal line can be realized, and the probability that the signal line is leaky or short-circuited due to static electricity is reduced.
  • the signal lines on the array substrate may include any one of signal lines such as a gate line, a data line, a common electrode line, a clock signal line of the gate driving circuit, a test line of the array substrate, or a repair line.
  • the adjacent signal lines may be the same type of signal lines, or may be different types of signal lines, which are not limited by the embodiments of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, which may include an array substrate, which may include an electrostatic protection circuit as shown in any of FIGS. 1 to 8.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.

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Abstract

提供了一种静电保护电路、阵列基板及显示装置。该静电保护电路包括：至少一个第一晶体管(M1)和至少一个第二晶体管(M2)；第一晶体管(M1)的栅极(11)和第一极(12)与第一信号线(P1)连接，第一晶体管(M1)的第二极(13)与第二信号线(P2)连接；第二晶体管(M2)的栅极(21)和第一极(22)与第二信号线(P2)连接，第二晶体管(M2)的第二极(23)与第一信号线(P1)连接。由于第一晶体管(M1)能将第一信号线(P1)产生的静电释放至第二信号线(P2)，第二晶体管(M2)能将第二信号线(P2)产生的静电释放至第一信号线(P1)，因此可以避免静电引起的短路等缺陷，而且该静电保护电路无需在阵列基板上额外布线，占用空间较小。

Description

静电保护电路、阵列基板及显示装置
本公开要求于2017年10月23日提交中国国家知识产权局、申请号为201710994724.6、发明名称为“静电保护电路、阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及一种静电保护电路、阵列基板及显示装置。
背景技术
随着显示装置的分辨率越来越高，显示装置的阵列基板上设置的信号线越来越密集，相邻信号线之间的间距也越来越小，因此相邻信号线之间也更加容易发生静电引起的漏电或短路等缺陷。为了保证各种信号线的正常工作，阵列基板上会设置与信号线连接的静电保护器件。
相关技术中的静电保护器件一般包括多个晶体管以及至少一条静电防护线，例如公共电极线或者短路环等。每个晶体管可以分别与一条信号线和该静电防护线连接，以将信号线上产生的静电及时释放至该静电防护线。
但是，相关技术中的静电保护器件需要在阵列基板上额外布置静电防护线，导致静电保护器件占用的空间较大，不利于窄边框显示面板的实现。
发明内容
本公开提供了一种静电保护电路、阵列基板及显示装置。技术方案如下：
一方面，提供了一种静电保护电路，所述静电保护电路包括：至少一个第一晶体管和至少一个第二晶体管；所述第一晶体管的栅极和第一极与第一信号线连接，所述第一晶体管的第二极与第二信号线连接；所述第二晶体管的栅极和第一极与所述第二信号线连接，所述第二晶体管的第二极与所述第一信号线连接；其中，所述第一信号线和所述第二信号线为阵列基板上任意两条相邻的信号线。
可选的，所述第一晶体管和所述第二晶体管均为薄膜晶体管；所述第一晶 体管的栅极与所述第一信号线同层设置；所述第二晶体管的栅极与所述第二信号线同层设置。
可选的，所述第一晶体管和所述第二晶体管均为薄膜晶体管；所述第一晶体管的第一极和第二极与所述第一信号线同层设置；所述第二晶体管的第一极和第二极与所述第二信号线同层设置。
可选的，所述第一晶体管为薄膜晶体管；所述第一信号线包括设置在不同层的第一导线和第二导线，所述第一导线的引线部分通过设置在引线区的过孔与所述第二导线的引线部分连接；所述第一晶体管的栅极由所述第一导线的引线部分构成，所述第一晶体管的第一极由所述第二导线的引线部分构成，所述第一晶体管的第二极由所述第二信号线的引线部分构成。
可选的，所述第二晶体管为薄膜晶体管；所述第二信号线包括设置在不同层的第三导线和第四导线，所述第三导线的引线部分通过设置在引线区的过孔与所述第四导线的引线部分连接；所述第二晶体管的栅极由所述第三导线的引线部分构成，所述第二晶体管的第一极由所述第四导线的引线部分构成，所述第二晶体管的第二极由所述第一信号线的引线部分构成。
可选的，每个晶体管的沟道的宽长比小于或等于四分之一。
可选的，每个晶体管的沟道在所述阵列基板上的正投影呈弯折的蛇形。
可选的，所述第一晶体管的沟道在所述阵列基板上的正投影位于所述第一信号线在所述阵列基板的正投影内；所述第二晶体管的沟道在所述阵列基板上的正投影位于所述第二信号线在所述阵列基板的正投影内。
可选的，所述第一晶体管的第一极在所述阵列基板上的正投影位于所述第一信号线在所述阵列基板的正投影内；所述第二晶体管的第一极在所述阵列基板上的正投影位于所述第二信号线在所述阵列基板的正投影内。
可选的，每个晶体管的第一极和第二极中的至少一极靠近沟道的一端在阵列基板上的正投影呈三角形或者梯形，所述三角形的尖端朝向所述沟道，所述梯形的上底相对于下底靠近所述沟道。
可选的，每个晶体管的沟道靠近第一极的一端在阵列基板上的正投影呈三角形或者梯形，所述三角形的尖端朝向所述第一极，所述梯形的上底相对于下底靠近所述第一极；和/或，每个晶体管的沟道靠近第二极的一端在阵列基板上的正投影呈三角形或者梯形，所述三角形的尖端朝向所述第二极，所述梯形的 上底相对于下底靠近所述第二极。
另一方面，提供了一种静电保护电路的制造方法，所述方法包括：
形成至少一个第一晶体管和至少一个第二晶体管；其中，所述第一晶体管的栅极和第一极与第一信号线连接，所述第一晶体管的第二极与第二信号线连接；所述第二晶体管的栅极和第一极与所述第二信号线连接，所述第二晶体管的第二极与所述第一信号线连接；所述第一信号线和所述第二信号线为阵列基板上任意两条相邻的信号线。
可选的，所述第一晶体管和所述第二晶体管均为薄膜晶体管；所述第一晶体管的栅极与所述第一信号线通过一次构图工艺形成；所述第二晶体管的栅极与所述第二信号线通过一次构图工艺形成。
可选的，所述第一晶体管和所述第二晶体管均为薄膜晶体管；所述第一晶体管的第一极和第二极与所述第一信号线通过一次构图工艺形成；所述第二晶体管的第一极和第二极与所述第二信号线通过一次构图工艺形成。
可选的，所述第一晶体管为薄膜晶体管；所述第一信号线包括形成在不同层的第一导线和第二导线，所述第一导线的引线部分通过形成在引线区的过孔与所述第二导线的引线部分连接；所述第一晶体管的栅极由所述第一导线的引线部分形成，所述第一晶体管的第一极由所述第二导线的引线部分形成，所述第一晶体管的第二极由所述第二信号线的引线部分形成。
又一方面，提供了一种阵列基板，所述阵列基板包括：如上述方面所述的静电保护电路。
可选的，所述阵列基板上设置有多条信号线，所述多条信号线中每两条相邻的信号线之间设置有所述静电保护电路。
再一方面，提供了一种显示装置，所述显示装置包括：如上述方面所述的阵列基板。
附图说明
图1是本公开实施例提供的一种静电保护电路的结构示意图；
图2是本公开实施例提供的一种静电保护电路的等效电路图；
图3是本公开实施例提供的另一种静电保护电路的等效电路图；
图4是本公开实施例提供的另一种静电保护电路的结构示意图；
图5是本公开实施例提供的又一种静电保护电路的结构示意图；
图6是本公开实施例提供的再一种静电保护电路的结构示意图；
图7是本公开实施例提供的再一种静电保护电路的结构示意图；
图8是本公开实施例提供的再一种静电保护电路的结构示意图；
图9是本公开实施例提供的一种静电保护电路的制造方法流程图。
具体实施方式
为使本公开的原理和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开实施例中采用的晶体管可以均为薄膜晶体管，根据在电路中的作用本公开实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，可以将其中源极称为第一极，漏极称为第二极。或者也可以将其中源极称为第二极，漏极称为第一极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。
本公开实施例提供了一种静电保护电路，该静电保护电路可以应用于阵列基板中。该静电保护电路可以包括：至少一个第一晶体管和至少一个第二晶体管。图1是本公开实施例提供的一种静电保护电路的结构示意图。图2是本公开实施例提供的一种静电保护电路的等效电路图。如图1和图2所示，该静电保护电路中可以包括一个第一晶体管M1以及一个第二晶体管M2。图3是本公开实施例提供的另一种静电保护电路的等效电路图。如图3所示，该静电保护电路中可以包括两个第一晶体管M1以及两个第二晶体管M2。
结合图1至图3可以看出，第一晶体管M1的栅极11和第一极12与第一信号线P1连接，第一晶体管M1的第二极13与第二信号线P2连接。第二晶体管M2的栅极21和第一极22与该第二信号线P2连接，第二晶体管M2的第二极23与该第一信号线P1连接。
该第一信号线P1和该第二信号线P2可以为阵列基板上任意两条相邻的信号线。当该第一信号线P1上产生静电时，该至少一个第一晶体管M1开启，将该第一信号线P1与第二信号线P2连通，从而可以将该第一信号线P1上产生的 静电释放至第二信号线P2上。相应的，当该第二信号线P2上产生静电时，该至少一个第二晶体管M2开启，将该第二信号线P2与第一信号线P1连通，从而可以将该第二信号线P2上产生的静电释放至第一信号线P1上。由此可以实现将信号线上累积的静电释放至相邻的信号线，从而降低静电导致信号线出现短路等缺陷的概率。
在本公开实施例中，当静电保护电路中包括一个第一晶体管M1和一个第二晶体管M2时，该静电保护电路的结构较为简单，占用面积较小。在静电保护电路中包括多个第一晶体管M1和多个第二晶体管M2的情况下，当某个第一晶体管或者某个第二晶体管失效时，其他晶体管还可以保证该静电保护电路正常工作，因此可以有效提高该静电保护电路的可靠性。在本公开实施例中，可以根据应用需求，灵活选择静电保护电路中第一晶体管和第二晶体管的数量，本公开实施例对此不做限定。
综上所述，本公开实施例提供的静电保护电路包括：至少一个第一晶体管和至少一个第二晶体管，第一晶体管的栅极和第一极与第一信号线连接，第一晶体管的第二极与第二信号线连接。第二晶体管的栅极和第一极与第二信号线连接，第二晶体管的第二极与第一信号线连接。因此，当该第一信号线和第二信号线中任一信号线上产生静电时，栅极与该产生静电的信号线连接的晶体管可以将静电释放至另一信号线，实现了静电的有效释放，从而降低了静电导致信号线出现短路等缺陷的概率。并且，该静电保护电路无需在阵列基板上额外布线，占用空间较小，有利于窄边框显示面板的实现。
可选的，在本公开实施例中，第一晶体管M1和第二晶体管M2可以均为薄膜晶体管。
第一晶体管M1的栅极11可以与该第一信号线P1同层设置。并且第二晶体管M2的栅极21也可以与该第二信号线P2同层设置。
可替换的，第一晶体管M1的第一极12和第二极13可以与该第一信号线P1同层设置。并且第二晶体管M2的第一极22和第二极23也可以与该第二信号线P2同层设置。
示例的，如图1所示，该第一晶体管M1的栅极11和第一极12均为该第一信号线P1的一部分，该第二晶体管M2的栅极21和第一极22均为该第二信号线P2的一部分。由此可以避免各晶体管额外占用过多的空间，提高阵列基板的 空间利用率。
可选的，本公开实施例提供的静电保护电路可以设置在阵列基板的非显示区域。例如可以设置在阵列基板的引线区(也称为fan-out区)，该引线区设置有各条信号线的引线部分。
可选的，在本公开实施例中，如图1所示，该第一信号线P1可以包括设置在不同层的第一导线P11和第二导线P12。该第一导线P11的引线部分通过设置在引线区的过孔14与该第二导线P12的引线部分连接。示例的，该过孔14中可以形成有导电层15，该第二导线P12的引线部分与该导电层15连接，该导电层15与第一导线P11连接，由此即可实现第二导线P12与第一导线P11的有效连接。该导电层15可以由氧化铟锡(Indium tin oxide，ITO)制成。
第一晶体管M1的栅极11可以由该第一导线P11的引线部分构成，第一晶体管M1的第一极12可以由该第二导线P12的引线部分构成，第一晶体管M1的第二极13可以由该第二信号线P2的引线部分构成。
可选的，如图1所示，该第二信号线P2也可以包括设置在不同层的第三导线P21和第四导线P22。该第三导线P21的引线部分通过设置在引线区的过孔24与该第四导线P22的引线部分连接。示例的，该过孔24中形成有导电层25(例如ITO层)，该第四导线P22的引线部分与该导电层25连接，该导电层25与第三导线P21连接，由此可以实现第四导线P22与第三导线P21的有效连接。
第二晶体管M2的栅极21可以由该第三导线P21的引线部分构成，第二晶体管M2的第一极22可以由该第四导线P22的引线部分构成，第二晶体管的第二极23可以由该第一信号线P1的引线部分构成。
在本公开实施例中，该第一信号线P1的第一导线P11与该第二信号线P2的第三导线P21可以同层设置，该第一信号线P1的第二导线P12与该第二信号线P2的第四导线P22可以同层设置。相应的，如图1所示，第一晶体管M1的第二极13可以由该第四导线P22的引线部分构成，第二晶体管M2的第二极23可以由该第二导线P12的引线部分构成。
当该静电保护电路中各晶体管为底栅结构的晶体管时，如图1所示，该第二导线P12可以位于第一导线P11远离阵列基板的一侧，第四导线P22也位于第三导线P21远离阵列基板的一侧。若静电保护电路中各晶体管为顶栅结构的 晶体管，则该第二导线P12可以位于第一导线P11靠近阵列基板的一侧，第四导线P22也位于第三导线P21靠近阵列基板的一侧。在本公开实施例中，根据晶体管具体结构的不同，每条信号线中两段导线的相对位置关系可以适应性调整，本公开实施例对此不做限定。
在本公开实施例一种可选的实现方式中，每条信号线中的每条导线可以包括位于引线区的引线部分，以及向外围区域延伸的导线部分。
示例的，如图4所示，第一信号线P1的第一导线P11可以包括位于该引线区的引线部分P111，以及向外围区域(例如压接区域，也称为PAD区域)延伸的导线部分P112。并且，该第二导线P12可以包括位于该引线区的引线部分P121，以及向外围区域延伸的导线部分P122。相应的，第二信号线P2的第三导线P21可以包括引线部分P211和导线部分P212，第四导线P22可以包括引线部分P221和导线部分P222。
在本公开实施例另一种可选的实现方式中，每条信号线中的一条导线可以包括位于引线区的引线部分，以及向外围区域延伸的导线部分。另一条导线则可以仅包括位于引线区的引线部分。
示例的，如图5所示，第一信号线P1的第一导线P11可以仅包括位于该引线区的引线部分，而该第二导线P12则可以包括位于该引线区的引线部分P121，以及向外围区域延伸的导线部分P122。相应的，第二信号线P2的第三导线P21可以仅包括引线部分，第四导线P22则可以包括引线部分P221和导线部分P222。
可选的，如图6所示，第一信号线P1的第一导线P11可以包括位于该引线区的引线部分P111，以及向外围区域延伸的导线部分P112；而该第二导线P12可以仅包括位于该引线区的引线部分。相应的，第二信号线P2的第三导线P21可以包括引线部分P211和导线部分P212，而第四导线P22则仅包括引线部分。
在本公开实施例中，每个晶体管的沟道的宽长比可以小于或等于四分之一。其中，沟道的宽长比可以是指沟道的宽度与沟道的长度的比值，晶体管的漏电流与晶体管沟道的宽长比成正比，即沟道的宽长比越大，晶体管的漏电流就越大。在本公开实施例中，通过控制每个晶体管的沟道的宽长比小于或等于四分之一，可以有效降低静电保护电路中各个晶体管的漏电流，也即是降低每个晶体管输出至相邻信号线的电流大小，进而可以有效提升静电保护电路的静电保护能力。
可选的，本公开实施例提供的静电保护电路中，每个晶体管的沟道在该阵列基板上的正投影可以呈弯折的蛇形。由此可以在沟道宽度一定的情况下，有效增大沟道的长度，进而有效减小沟道的宽长比，降低晶体管的漏电流。示例的，图1中示出了各个晶体管的沟道的俯视形态。从图1可以看出，第一晶体管M1的沟道16以及第二晶体管M2的沟道26均呈弯折的蛇形。
从图1还可以看出，第一晶体管M1的沟道16在阵列基板上的正投影可以位于第一信号线P1在该阵列基板的正投影内。第二晶体管M2的沟道26在该阵列基板上的正投影也可以位于该第二信号线P2在该阵列基板的正投影内。
可选的，第一晶体管M1的第一极12在阵列基板上的正投影可以位于该第一信号线P1在该阵列基板的正投影内。第二晶体管M2的第一极22在该阵列基板上的正投影也可以位于该第二信号线P2在该阵列基板的正投影内。
通过在阵列基板上信号线的覆盖区域内设置晶体管的沟道以及晶体管的第一极，可以避免静电保护电路中的晶体管额外占用过多空间，有效提高阵列基板的空间利用率，有利于窄边框显示面板的实现。
可选的，在本公开实施例中，每个晶体管的第一极和第二极中的至少一极靠近沟道的一端在阵列基板上的正投影可以呈三角形或者梯形，且该三角形的尖端朝向沟道，该梯形的上底相对于下底靠近沟道。由此可以减小晶体管第一极与沟道的接触面积，或者减小晶体管第二极与沟道的接触面积，从而可以进一步减小晶体管的漏电流，提升静电保护电路的静电保护能力。
图7是本公开实施例提供的再一种静电保护电路的结构示意。如图7所示，每个晶体管的第一极和第二极靠近沟道的一端在阵列基板上的正投影均为三角形，即每个晶体管的第一极和第二极靠近沟道的一端均呈尖端状，因此每个晶体管开启时的漏电流均较小。
可选的，每个晶体管的沟道靠近第一极的一端在阵列基板上的正投影可以呈三角形或者梯形，并且该三角形的尖端朝向该第一极，该梯形的上底相对于下底靠近该第一极。相应的，每个晶体管的沟道靠近第二极的一端在阵列基板上的正投影也可以呈三角形或者梯形，并且该三角形的尖端朝向该第二极，该梯形的上底相对于下底靠近该第二极。由此可以进一步减小晶体管沟道与第一极的接触面积，以及沟道与第二极的接触面积，进而进一步减小晶体管开启时的漏电流。
示例的，如图8所示，每个晶体管的沟道靠近第一极的一端在阵列基板上的正投影，以及靠近第二极的一端在阵列基板上的正投影均呈三角形，因此每个晶体管开启时的漏电流较小，该静电保护电路的静电保护能力较强。
综上所述，本公开实施例提供了一种静电保护电路，该静电保护电路包括设置在相邻两条信号线之间的至少一个第一晶体管和至少一个第二晶体管，该第一晶体管能够将第一信号线产生的静电释放至第二信号线，而第二晶体管则能够将第二信号线产生的静电释放至第一信号线，由此可以有效避免静电引起的短路等缺陷，而且该静电保护电路无需在阵列基板上额外布线，占用空间较小，有利于窄边框显示面板的实现。
图9是本公开实施例提供的一种静电保护电路的制造方法的流程图。该方法可以用于制造上述实施例提供的静电保护电路。参考图9，该方法可以包括如下工作过程：
在步骤101中，提供一衬底基板。
该衬底基板可以为透明的玻璃基板。
在步骤102中，在该衬底基板上形成至少一个第一晶体管和至少一个第二晶体管。
第一晶体管的栅极和第一极与第一信号线连接，第一晶体管的第二极与第二信号线连接。第二晶体管的栅极和第一极与该第二信号线连接，第二晶体管的第二极与该第一信号线连接。该第一信号线和该第二信号线可以为阵列基板上任意两条相邻的信号线。
可选的，该静电保护电路中的第一晶体管和第二晶体管可以均为薄膜晶体管。
作为一种可选的实现方式，在上述步骤102中，第一晶体管的栅极可以与该第一信号线通过一次构图工艺形成。第二晶体管的栅极可以与该第二信号线通过一次构图工艺形成。并且，各个第一晶体管的栅极均可以通过一次构图工艺形成。
作为另一种可选的实现方式，在上述步骤102中，第一晶体管的第一极和第二极可以与第一信号线通过一次构图工艺形成。第二晶体管的第一极和第二极可以与该第二信号线通过一次构图工艺形成。并且，各个晶体管的第一极和 第二极均可以通过一次构图工艺形成。
在本发明实施例中，在形成各个晶体管的栅极以及该信号线时，可以先采用磁控溅射或蒸发等工艺在衬底基板上制备一层金属薄膜。然后可以采用光刻工艺对该金属薄膜进行图形化处理，以形成各个晶体管的栅极以及各条信号线。
该光刻工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离等步骤。该金属薄膜的材料可以是由低电阻金属材料形成的膜层，例如可以是由钼(Mo)、铝(Al)、铝镍合金、铬(Cr)或、铜(Cu)、钛(Ti)或AlNd等材料形成的单层金属薄膜，或者也可以是Mo/Al/Mo或Ti/Al/Ti形成的多层金属薄膜。
可选的，该第一信号线可以包括形成在不同层的第一导线和第二导线，该第一导线的引线部分可以通过形成在引线区的过孔与该第二导线的引线部分连接。第一晶体管的栅极可以由该第一导线的引线部分形成，第一晶体管的第一极可以由该第二导线的引线部分形成，第一晶体管的第二极可以由该第二信号线的引线部分形成。
可选的，与该第一信号线类似，该第二信号线也可以包括设置在不同层的第三导线和第四导线，该第三导线的引线部分可以通过设置在引线区的过孔与该第四导线的引线部分连接。
第二晶体管的栅极由该第三导线的引线部分形成，第二晶体管的第一极由该第四导线的引线部分形成，第二晶体管的第二极由该第一信号线的引线部分形成。
在本发明实施例中，形成各个晶体管的第一极和第二极的材料可以与形成栅极的材料类似，形成各个晶体管的第一极和第二极的制造工艺也可以与形成栅极的制造工艺类似，此处不再赘述。
本公开实施例提供了一种阵列基板，该阵列基板可以包括：如图1至图8任一所示的静电保护电路。
可选的，该阵列基板上可以设置有多条信号线。参考图1、图4至图8可以看出，该多条信号线中每两条相邻的信号线之间可以均设置有静电保护电路。若某条信号线分别与两条信号线相邻，则该信号线所覆盖的区域内可以设置有两个晶体管，该两个晶体管分别与一条相邻的信号线连接。例如图8所示的结 构中，第二信号线P2覆盖的区域内设置有一个第二晶体管M2，以及一个第一晶体管M1。该第二晶体管M2用于连接第二信号线P2左侧的第一信号线P1，该第一晶体管M1用于连接第二信号线P2右侧的信号线。
当阵列基板上多条信号线中的任一信号线上产生静电时，静电保护电路中，栅极与该产生静电的信号线连接的晶体管可以开启，将该产生静电的信号线与相邻的信号线连通，从而将静电释放至该相邻的信号线。若该产生静电的信号线释放的静电较大，则栅极与该相邻的信号线连接的晶体管也可以被驱动开启，从而将静电再释放至另一信号线，直至某条信号线上释放的静电无法再驱动晶体管开启为止。由此可以实现每条信号线上静电的有效释放，降低了信号线因静电而产生漏电或者短路等缺陷的概率。
在本公开实施例中，该阵列基板上的信号线可以包括栅线、数据线、公共电极线、栅极驱动电路的时钟信号线、阵列基板的测试线或维修线等任一种信号线。且相邻的信号线可以为同种类型的信号线，也可以为不同类型的信号线，本公开实施例对此不做限定。
本公开实施例还提供一种显示装置，该显示装置可以包括阵列基板，该阵列基板可以包括如图1至图8任一所示的静电保护电路。该显示装置可以为：液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的示例性实施例，并不用以限制本公开的范围，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开所附权利要求限定的保护范围之内。

Claims (20)

  1. 一种静电保护电路，包括：至少一个第一晶体管和至少一个第二晶体管；
    所述第一晶体管的栅极和第一极与第一信号线连接，所述第一晶体管的第二极与第二信号线连接；
    所述第二晶体管的栅极和第一极与所述第二信号线连接，所述第二晶体管的第二极与所述第一信号线连接；
    其中，所述第一信号线和所述第二信号线为阵列基板上任意两条相邻的信号线。
  2. 根据权利要求1所述的静电保护电路，其中，所述第一晶体管和所述第二晶体管均为薄膜晶体管；
    所述第一晶体管的栅极与所述第一信号线同层设置；
    所述第二晶体管的栅极与所述第二信号线同层设置。
  3. 根据权利要求1所述的静电保护电路，其中，所述第一晶体管和所述第二晶体管均为薄膜晶体管；
    所述第一晶体管的第一极和第二极与所述第一信号线同层设置；
    所述第二晶体管的第一极和第二极与所述第二信号线同层设置。
  4. 根据权利要求1所述的静电保护电路，其中，所述第一晶体管为薄膜晶体管；
    所述第一信号线包括设置在不同层的第一导线和第二导线，所述第一导线的引线部分通过设置在引线区的过孔与所述第二导线的引线部分连接；
    所述第一晶体管的栅极由所述第一导线的引线部分构成，所述第一晶体管的第一极由所述第二导线的引线部分构成，所述第一晶体管的第二极由所述第二信号线的引线部分构成。
  5. 根据权利要求1所述的静电保护电路，其中，所述第二晶体管为薄膜晶体管；
    所述第二信号线包括设置在不同层的第三导线和第四导线，所述第三导线的引线部分通过设置在引线区的过孔与所述第四导线的引线部分连接；
    所述第二晶体管的栅极由所述第三导线的引线部分构成，所述第二晶体管的第一极由所述第四导线的引线部分构成，所述第二晶体管的第二极由所述第一信号线的引线部分构成。
  6. 根据权利要求1至5任一所述的静电保护电路，其中，每个晶体管的沟道的宽长比小于或等于四分之一。
  7. 根据权利要求1至5任一所述的静电保护电路，其中，每个晶体管的沟道在所述阵列基板上的正投影呈弯折的蛇形。
  8. 根据权利要求1至5任一所述的静电保护电路，其中，
    所述第一晶体管的沟道在所述阵列基板上的正投影位于所述第一信号线在所述阵列基板的正投影内；
    所述第二晶体管的沟道在所述阵列基板上的正投影位于所述第二信号线在所述阵列基板的正投影内。
  9. 根据权利要求1至5任一所述的静电保护电路，其中，
    所述第一晶体管的第一极在所述阵列基板上的正投影位于所述第一信号线在所述阵列基板的正投影内；
    所述第二晶体管的第一极在所述阵列基板上的正投影位于所述第二信号线在所述阵列基板的正投影内。
  10. 根据权利要求1至5任一所述的静电保护电路，其中，每个晶体管的第一极和第二极中的至少一极靠近沟道的一端在阵列基板上的正投影呈三角形或者梯形，所述三角形的尖端朝向所述沟道，所述梯形的上底相对于下底靠近所述沟道。
  11. 根据权利要求1至5任一所述的静电保护电路，其中，每个晶体管的 沟道靠近第一极的一端在阵列基板上的正投影呈三角形或者梯形，所述三角形的尖端朝向所述第一极，所述梯形的上底相对于下底靠近所述第一极。
  12. 根据权利要求1至5任一所述的静电保护电路，其中，每个晶体管的沟道靠近第二极的一端在阵列基板上的正投影呈三角形或者梯形，所述三角形的尖端朝向所述第二极，所述梯形的上底相对于下底靠近所述第二极。
  13. 根据权利要求1至5任一所述的静电保护电路，其中，
    每个晶体管的沟道靠近第一极的一端在阵列基板上的正投影呈三角形或者梯形，所述三角形的尖端朝向所述第一极，所述梯形的上底相对于下底靠近所述第一极；以及
    每个晶体管的沟道靠近第二极的一端在阵列基板上的正投影呈三角形或者梯形，所述三角形的尖端朝向所述第二极，所述梯形的上底相对于下底靠近所述第二极。
  14. 一种静电保护电路的制造方法，包括：
    形成至少一个第一晶体管和至少一个第二晶体管；
    其中，每个所述第一晶体管的栅极和第一极与第一信号线连接，每个所述第一晶体管的第二极与第二信号线连接；每个所述第二晶体管的栅极和第一极与所述第二信号线连接，每个所述第二晶体管的第二极与所述第一信号线连接；所述第一信号线和所述第二信号线为阵列基板上任意两条相邻的信号线。
  15. 根据权利要求14所述的方法，其中，每个所述第一晶体管和每个所述第二晶体管均为薄膜晶体管；
    每个所述第一晶体管的栅极与所述第一信号线通过一次构图工艺形成；
    每个所述第二晶体管的栅极与所述第二信号线通过一次构图工艺形成。
  16. 根据权利要求14所述的方法，其中，每个所述第一晶体管和每个所述第二晶体管均为薄膜晶体管；
    每个所述第一晶体管的第一极和第二极与所述第一信号线通过一次构图工 艺形成；
    每个所述第二晶体管的第一极和第二极与所述第二信号线通过一次构图工艺形成。
  17. 根据权利要求14所述的静电保护电路，其中，每个所述第一晶体管为薄膜晶体管；
    所述第一信号线包括形成在不同层的第一导线和第二导线，所述第一导线的引线部分通过形成在引线区的过孔与所述第二导线的引线部分连接；
    每个所述第一晶体管的栅极由所述第一导线的引线部分形成，每个所述第一晶体管的第一极由所述第二导线的引线部分形成，每个所述第一晶体管的第二极由所述第二信号线的引线部分形成。
  18. 一种阵列基板，包括：
    如权利要求1至13任一所述的静电保护电路。
  19. 根据权利要求18所述的阵列基板，其中，
    所述阵列基板上设置有多条信号线，所述多条信号线中每两条相邻的信号线之间设置有所述静电保护电路。
  20. 一种显示装置，包括：如权利要求18或19所述的阵列基板。
PCT/CN2018/098275 2017-10-23 2018-08-02 静电保护电路、阵列基板及显示装置 WO2019080577A1 (zh)

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