JP7150609B2 - 短チャネルのトレンチパワーmosfet - Google Patents
短チャネルのトレンチパワーmosfet Download PDFInfo
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- JP7150609B2 JP7150609B2 JP2018552752A JP2018552752A JP7150609B2 JP 7150609 B2 JP7150609 B2 JP 7150609B2 JP 2018552752 A JP2018552752 A JP 2018552752A JP 2018552752 A JP2018552752 A JP 2018552752A JP 7150609 B2 JP7150609 B2 JP 7150609B2
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- 239000004065 semiconductor Substances 0.000 claims description 162
- 238000000034 method Methods 0.000 claims description 37
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 31
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 16
- 238000009413 insulation Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 description 13
- 238000005530 etching Methods 0.000 description 8
- 230000005669 field effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Description
本発明は、短チャネルのトレンチパワーMOSFETに関し、これを製造するための方法に関する。
US2014/0159053A1から公知である炭化珪素トレンチゲートトランジスタは、n型ドレイン領域と、n型ドレイン領域上に形成されたn型ドリフト領域と、n型ドリフト領域上に形成されたp型ベース領域と、p型ベース領域上に形成されたn型ソース領域と、ゲートトレンチと、ソース領域の下であってゲートトレンチの側壁上のベース領域に位置するn型埋込みチャネル領域とを含む。埋込みチャネル領域は30nm~80nmの厚さを有するものとして記載されている。
本発明の目的は、如何なる短チャネル効果をも防止するとともにサブスレッショルドスロープを小さくしながらも、オン状態の抵抗が低いパワー半導体装置を提供することである。
例示的な実施形態においては、補償層の厚さは2nm~5nmの範囲である。
本発明の詳細な実施形態を、添付の図面に関連付けて以下に説明する。
図1には、本発明の実施形態に従ったパワー半導体装置の断面図が示される。図2は、図1の拡大部分を示す。本発明の実施形態に従ったパワー半導体装置は、トレンチパワー金属酸化膜半導体電界効果トランジスタ(MOSFET)1であり、第1の主面3と第2の主面4とを有する炭化珪素(SiC)ウェハ2を含む。明細書全体にわたって、炭化珪素という語は、如何なるポリタイプの炭化珪素を指していてもよく、特に、4H-SiCまたは6H-SiCを指すこともある。SiCウェハ2は、第1の主面3から第2の主面4の順に、n+ドープされたソース層5、pドープされたボディ層6、n-ドープされたドリフト層7およびn+ドープされたドレイン層8を含む。ドリフト層7およびドレイン層8はnドープされた基板層9を形成する。ソース層5は、ボディ層6によってドリフト層7から隔てられており、ボディ層6はドリフト層7によってドレイン層8から隔てられている。複数の導電性ゲート電極10はボディ層6を貫通している。各々のゲート電極10は、ゲート電極10に電位を与える際にボディ層6におけるチャネル領域の導電性を電界によって制御するように構成されている。この場合、各々のチャネル領域は、ソース層5からドリフト層7にまで延在するボディ層6の一部である。MOSチャネルが、ソース層5からチャネル領域を通ってドリフト層7にまで形成されてもよい。ゲート絶縁層11は、ドリフト層7、ボディ層6およびソース層5からゲート電極10を電気的に絶縁している。
1 トレンチパワー金属酸化膜半導体電界効果トランジスタ(MOSFET)、2 炭化珪素(SiC)ウェハ、3、23 第1の主面、4、24 第2の主面、5 (n+ドープされた)ソース層、6 (pドープされた)ボディ層、7 (n-ドープされた)ドリフト層、8 (n+ドープされた)ドレイン層、9 (nドープされた)基板層、10 ゲート電極、11 ゲート絶縁層、15 (nドープされた)補償層、17 ソース電極、18 ドレイン電極、20 (nドープされた)第1の半導体層、23 第1の主面、24 第2の主面、25 n+ドープされたSiC層、26 n-ドープされたSiC層、27 (pドープされた)第2の半導体層、28 第1のn型不純物、29 注入マスク、30 (n+ドープされた)第3の半導体層、31 開口部、35 トレンチ、35′ 深くされたトレンチ、37 エッチングマスク、38 第2のn型不純物、39 nドープされた半導体領域、42 pドープされたウェル領域、45 絶縁層、50 電極層、Lch チャネル長、tCOMP 補償層15の厚さ。
Claims (13)
- パワー半導体装置を製造するための方法であって、
前記パワー半導体装置は、
第1導電型を有する基板層(9)と、
前記基板層(9)上に設けられ、第1導電型とは異なる第2導電型を有するボディ層(6)と、
前記ボディ層(6)上に設けられ、第1導電型を有するソース層(5)とを備え、前記ボディ層(6)は、前記ソース層(5)から前記基板層(9)に延在するチャネル領域を含み、前記パワー半導体装置はさらに、
前記ボディ層(6)を貫通するとともに前記チャネル領域の導電性を制御するための導電性ゲート電極(10)と、
前記基板層(9)、前記ボディ層(6)および前記ソース層(5)から前記ゲート電極(10)を電気的に絶縁させるゲート絶縁層(11)と、
第1導電型の補償層(15)とを備え、前記補償層(15)は、前記チャネル領域に直接隣接している前記基板層(9)と前記ソース層(5)との間において前記ゲート絶縁層(11)上において直接延在しており、前記チャネル領域は、前記補償層(15)から0.1μm未満の距離を空けて前記ボディ層(6)の一部として規定されており、
Lchはチャネル長であり、εCRは前記チャネル領域の誘電率であり、εGIは前記ゲート絶縁層(11)の誘電率であり、tCOMPは、前記ゲート絶縁層(11)と前記補償層(15)との間の界面に対して垂直な方向における前記補償層(15)の厚さであり、tGIは前記ゲート絶縁層(11)の厚さであり、
前記補償層(15)の前記厚さtCOMPは1nmから10nmの範囲であり、
前記方法は、
第1導電型の第1の半導体層(20)を設けるステップを含み、前記第1の半導体層(20)は、第1の主面(23)と、前記第1の主面(23)とは反対側の第2の主面(24)とを有し、前記第1の半導体層(20)は、前記パワー半導体装置(1)において前記基板層(9)を形成し、前記方法はさらに、
第2導電型の第2の半導体層(27)を、前記第1の半導体層(20)と直接接触するように前記第1の半導体層(20)の前記第1の主面(23)上に形成するステップを含み、前記第2の半導体層(27)は、前記パワー半導体装置(1)において前記ボディ層を形成し、前記方法はさらに、
第1導電型の第3の半導体層(30)を形成するステップを含み、前記第3の半導体層(30)は、前記第2の半導体層(27)と直接接触するとともに前記第2の半導体層(27)によって前記第1の半導体層(20)から隔てられており、前記第3の半導体層(30)は、前記パワー半導体装置(1)において前記ソース層(5)を形成し、前記方法はさらに、
前記第3の半導体層(30)の材料および前記第2の半導体層(27)の材料を除去することにより、前記第3の半導体層(30)を通って前記第2の半導体層(27)内に貫通する少なくとも1つのトレンチ(35)を形成するステップと、
第1導電型の半導体領域(39)を形成するように、前記少なくとも1つのトレンチ(35)の側壁内に第1導電型の不純物(38)を添加するステップとを含み、前記半導体領域(39)は前記第3の半導体層(30)を前記第1の半導体層(20)に接続しており、前記半導体領域(39)は、前記パワー半導体装置(1)において前記補償層(15)を形成し、前記方法はさらに、
前記第2の半導体層(27)の材料および前記第1の半導体層(20)の材料を除去することにより前記トレンチ(35)を深くするステップを含み、前記深くするステップは、深くされたトレンチ(35′)が前記第1の半導体層(20)内に貫通するように行われ、前記方法はさらに、
前記側壁と前記少なくとも1つの深くされたトレンチ(35′)の底部とを覆う絶縁層(45)を形成するステップとを含み、前記絶縁層(45)は、前記パワー半導体装置(1)において前記ゲート絶縁層(11)を形成し、前記方法はさらに、
前記少なくとも1つの深くされたトレンチ(35′)に電極層(50)を形成するステップを含み、前記電極層(50)は、前記絶縁層(45)によって、前記第1の半導体層(20)、前記第2の半導体層(27)、前記第3の半導体層(30)および前記第1導電型の前記半導体領域(39)から電気的に絶縁されており、前記電極層(50)は、前記パワー半導体装置(1)において前記ゲート電極(10)を形成する、方法。 - 前記少なくとも1つのトレンチ(35)の前記側壁内に第1導電型の前記不純物(38)を添加するステップは、角度を付けてイオン注入することによって実行される、請求項1に記載の、パワー半導体装置を製造するための方法。
- 前記少なくとも1つのトレンチ(35)の前記側壁内に第1導電型の前記不純物(38)を添加するステップはプラズマイオン注入によって実行される、請求項1に記載の、パワー半導体装置を製造するための方法。
- 第2導電型の不純物を前記少なくとも1つの深くされたトレンチ(35′)の底部を通過して前記第1の半導体層(20)内に添加することによって、前記少なくとも1つの深くされたトレンチ(35′)の前記底部よりも下方に第2導電型の半導体ウェル領域(42)が形成される、請求項1から3のいずれか1項に記載の、パワー半導体装置を製造するための方法。
- 前記第3の半導体層(30)は、第1導電型の不純物を前記第2の半導体層(27)内に添加することによって形成される、請求項1から4のいずれか1項に記載の、パワー半導体装置を製造するための方法。
- 前記チャネル長(Lch)は0.5μm未満である、請求項1に記載の、パワー半導体装置を製造するための方法。
- 前記チャネル長(Lch)は0.3μm未満である、請求項1に記載の、パワー半導体装置を製造するための方法。
- 前記補償層(15)におけるドーピング濃度は少なくとも1・1018cm-3である、請求項1に記載の、パワー半導体装置を製造するための方法。
- 前記補償層(15)におけるドーピング濃度は少なくとも5・1018cm-3である、請求項8に記載の、パワー半導体装置を製造するための方法。
- 前記チャネル領域におけるドーピング濃度は少なくとも5・1017cm-3である、請求項1に記載の、パワー半導体装置を製造するための方法。
- 前記チャネル領域におけるドーピング濃度は、少なくとも1・1018cm-3または少なくとも5・1018cm-3である、請求項1に記載の、パワー半導体装置を製造するための方法。
- 前記基板層(9)、前記ボディ層(6)、前記補償層(15)および前記ソース層(5)は炭化珪素層である、請求項1に記載の、パワー半導体装置を製造するための方法。
- 第2導電型のウェル領域(42)を備え、前記ウェル領域(42)は、前記ゲート電極(10)の底部よりも下方において前記ゲート絶縁層(11)に直接隣接している、請求項1に記載の、パワー半導体装置を製造するための方法。
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