CN109314142A - 短沟道沟槽功率mosfet - Google Patents

短沟道沟槽功率mosfet Download PDF

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CN109314142A
CN109314142A CN201780035730.7A CN201780035730A CN109314142A CN 109314142 A CN109314142 A CN 109314142A CN 201780035730 A CN201780035730 A CN 201780035730A CN 109314142 A CN109314142 A CN 109314142A
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semiconductor
semiconductor device
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power semiconductor
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CN109314142B (zh
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R.米娜米萨瓦
L.诺勒
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Hitachi Energy Co ltd
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ABB Technology AG
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Abstract

本发明的一个目的是提供一种功率半导体装置，其具有低接通状态电阻，同时避免任何短沟道效应并且具有低阈值下斜率。为了达到这个目的，本发明提供一种沟槽功率半导体装置，其包括第一导电类型的补偿层(15)，其中补偿层(15)与第二导电类型的沟道区直接相邻地在第一导电类型的源极层(5)与第一导电类型的衬底层(9)之间在栅极绝缘层(11)上延伸，并且其中：。在以上不等式中，L ch 是沟道长度，ε CR 是沟道区的电容率，ε GI 是栅极绝缘层的电容率，t COMP 是补偿层(15)的厚度，以及t GI 是栅极绝缘层(11)的厚度。

Description

短沟道沟槽功率MOSFET
技术领域
本发明涉及短沟道沟槽功率MOSFET，并且涉及用于制造短沟道沟槽功率MOSFET的方法。
背景技术
从US 2014/0159053 A1已知一种碳化硅沟槽栅极晶体管，其包括n型漏极区、在n型漏极区上形成的n型漂移区、在n型漂移区上形成的p型基极区、在p型基极区上形成的n型源极区、栅极沟槽、以及位于源极区下面并且在栅极沟槽的侧壁上的基极区中的n型嵌入式沟道区。嵌入式沟道区被描述为具有30至80 nm的厚度。
从US 2014/0110723 A1已知一种半导体装置，其包括：半导体衬底；位于半导体衬底的主表面的第一碳化硅半导体层，第一碳化硅半导体层包括第一导电类型的漂移区、第二导电类型的体区、和第一导电类型的杂质区；沟槽，其被设置在第一碳化硅半导体层中以便达到漂移区的内部；第一导电类型的第二碳化硅半导体层，其至少位于沟槽的侧表面上以便与杂质区和漂移区相接触；栅极绝缘膜；栅极电极；第一欧姆电极；以及第二欧姆电极。体区包括：第一体区，其与沟槽的侧表面上的第二碳化硅半导体层相接触；以及第二体区，其与漂移区相接触，并且具有比第一体区更小的平均杂质浓度。公开了在从20 nm至70 nm的范围中的第二碳化硅半导体层的厚度。
在功率金属氧化物半导体场效应晶体管(MOSFET)装置的不同结构之中，沟槽功率MOSFET具有接通状态电阻相对低的优点。在沟槽功率MOSFET中，电流从晶圆的第一主侧(即，第一主侧表面)上的源极电极被垂直传导到晶圆中与第一主侧相对的第二主侧(即，第二主侧表面)上的漏极电极。为了取得高驱动能力，多个沟槽穿透晶圆的第一主侧之下的p掺杂体区。在每个沟槽的内部，形成了栅极电介质和栅极电极，以通过场效应控制从n掺杂源极区经过与沟槽相邻的p掺杂体区中的沟道区到n-掺杂漂移区的电流传导。每个沟槽对应于MOSFET单元。所有MOSFET单元被并联连接在源极电极与漏极电极之间，以便减少接通状态电阻。多个MOSFET单元的沟道区和与漏极电极接触的n+掺杂漏极层之间的n-掺杂漂移区在断开状态条件中允许大电压。在接通状态条件中，载荷子因跨n+掺杂漏极层的电位差而经过n-漂移区朝n+掺杂漏极层漂移。
功率半导体工业正朝按比例缩放而强力推动，这要求装置静电学的改进。减少已知沟槽功率MOSFET中的沟道长度能够强力减少接通状态损耗，但是以阈值电压Vth的偏移为代价并且以反向阻断中的过早击穿为代价。
对于高反向阻断能力，按照避免尚未耗尽的漏失电流（leakage current underdepletion）到n+掺杂源极区的方式来设计p掺杂体区是至关重要的。在常见沟槽功率MOSFET中，p掺杂体区被实现为具有大约1 μm的典型厚度和大约1017 cm-3的中等掺杂浓度的半导体层。减少p掺杂体区的层厚度并且因而减少沟道长度将不可避免地要求更高掺杂，这进而将因库仑散射以及Vth朝正极性的显著偏移而使沟道迁移率降级。
从现有技术文献US 8476697 B1已知一种碳化硅(SiC)功率双扩散金属氧化物半导体场效应晶体管(DMOSFET)，其具有大约0.5 μm的沟道长度。P掺杂体区具有大约1·1018cm-3至3·1018 cm-3的峰值浓度，以便避免穿通。p掺杂体区的掺杂分布（doping profile）是逆行性掺杂分布，其在沟道区中具有大约2.5·1017 cm-3或更大的p型掺杂浓度以及在p掺杂体区与n-掺杂漂移区之间的p-n结附近具有大约1·1018 cm-3至3·1018 cm-3的掺杂浓度。为了避免在阈值处的高氧化物场，用掺杂浓度为大约3·1017 cm-3至8·1017 cm-3的n型掺杂剂来对沟道区进行补偿掺杂（counter dope），由此在补偿之后，表面为具有净掺杂浓度为大约1·1017 cm-3至3·1017 cm-3的n型（直到60 nm的补偿掺杂深度）。还描述了一种碳化硅UMOSFET装置，其中通过在沟槽蚀刻之后的到沟槽侧壁中的倾斜离子注入来得到表面n型层。但是，US 8476697 B1中公开的功率MOSFET遭受短沟道效应和高阈值下斜率（highsubthreshold slope）。
发明内容
本发明的一个目的是提供一种功率半导体装置，其具有低接通状态电阻，同时避免任何短沟道效应并具有低阈值下斜率。
本发明的所述目的通过根据权利要求1的功率半导体装置来达到。根据本发明的功率半导体装置是一种沟槽功率场效应晶体管，其包括第一导电类型的补偿层，其中补偿层与沟道区直接相邻地在源极层与衬底层之间在栅极绝缘层上延伸，并且其中：
， (1)
在以上不等式(1)中，L ch 是沟道长度，ε CR 是沟道区的电容率，ε GI 是栅极绝缘层的电容率，t COMP 是补偿层沿与栅极绝缘层和补偿层之间的界面正交的方向的厚度，以及t GI 是栅极绝缘层的厚度。在其中，沟道长度被定义为沿栅极绝缘层从源极层到衬底层的最短路径的长度。由于具有与源极层相同的导电类型的补偿层，可能难以判定在什么深度(即，在离晶圆的第一主侧表面的什么距离)，源极层结束并且补偿层开始。为了便于确定沟道长度，源极层结束并且补偿层开始于的深度因此被假定为在离栅极绝缘层0.1 μm的横向距离处在源极层与体层之间的p-n结的深度。同样，为了便于确定沟道长度，补偿层结束并且衬底层开始于的深度被假定为在离栅极绝缘层0.1 μm的横向距离处在体层与衬底层之间的p-n结的深度。过程本说明书，术语“横向”指与晶圆的第一主侧平行的方向。
通过满足不等式(1)，补偿层能够避免具有低阈值下斜率和最佳阈值电压的沟槽功率场效应晶体管装置中的短沟道效应（甚至对于其中现有技术沟槽功率场效应晶体管呈现显著短沟道效应的短沟道长度）。
在本发明的功率半导体装置中，补偿层的厚度处于从1 nm至10 nm的范围中。沿与栅极绝缘层正交的方向来测量所述厚度。1 nm的下限确保阈值电压Vth的高效减少以及沟道载流子迁移率的增加，而上限确保能够特别高效地减少短沟道效应。
在从属权利要求中规定了本发明的其它发展。
在示范性实施例中，补偿层的厚度处于从2 nm至5 nm的范围中。
在示范性实施例中，沟道长度小于0.5 μm或者小于0.3 μm。这种短沟道长度引起低接通状态电压，即，引起低接通状态损耗。
在示范性实施例中，补偿层中的掺杂浓度为至少1·1018 cm-3或者为至少5·1018cm-3。补偿层的这种高掺杂浓度引起通过补偿层的短沟道效应的最高效减少以及阈值电压的减少。过程本说明书，层或区的掺杂浓度应指层的峰值净掺杂浓度，即，指这个层的最大净掺杂浓度，除非它涉及掺杂分布。如果它涉及掺杂分布，则术语“掺杂浓度”应指局部净掺杂浓度。
在示范性实施例中，沟道区中的掺杂浓度为至少5·1017 cm-3或者为至少1·1018cm-3或者为至少5·1018 cm-3。沟道区中的这种高掺杂浓度能够高效地避免在高反向电压的阻断状态中的穿通。
在示范性实施例中，衬底层、体层、补偿层和源极层是碳化硅层。碳化硅(SiC)具有比硅(Si)高大约九倍的击穿强度，从而引起针对基于SiC的装置的更低得多的损耗。
在示范性实施例中，功率半导体装置包括第二导电类型的阱区，其中阱区在栅极电极的底部之下与栅极绝缘层直接相邻。这种阱区能够高效地保护栅极绝缘层免受高电场。
本发明的功率半导体装置可通过根据权利要求11的方法来制造。仅在将第一导电类型的杂质施加到至少一个沟槽的侧壁中的步骤之后才执行通过移除第二半导体层的材料和第一半导体层的材料来加深沟槽以使得经加深沟槽穿入第一半导体层中的步骤允许将第一导电类型的杂质仅施加到第二半导体层和第三半导体层中，而避免将第一导电类型的杂质施加到第一半导体层中。
在示范性实施例中，通过倾斜离子注入或者通过等离子体浸入离子注入(PIII)来执行将第一导电类型的杂质施加到至少一个沟槽的侧壁。等离子体浸入离子注入允许形成沿与沟槽的侧壁平行的方向而具有均质掺杂浓度分布的补偿层，即，与沟槽中的深度几乎无关的掺杂浓度分布。此外，等离子体浸入离子注入仅创建极少缺陷，这进一步减少短沟道效应。
附图说明
下面将参照附图来解释本发明的详细实施例，在附图中：
图1示出按照本发明的实施例的功率半导体装置的部分截面图；
图2示出图1中的截面图的放大部分；以及
图3A至图3G示出部分截面图，其示出用于制造图1的功率半导体装置的方法的不同步骤。
在参考标号列表中概括了附图中使用的参考标号及其含意。一般来说，贯穿本说明书，相似元件具有相同参考标号。所描述的实施例意在作为示例而不应限制本发明的范畴。
具体实施方式
在图1中示出了按照本发明的实施例的功率半导体装置的截面图。图2示出了图1的放大部分。按照本发明的实施例的功率半导体装置是沟槽功率金属氧化物半导体场效应晶体管(MOSFET)1。它包括碳化硅(SiC)晶圆2，其具有第一主侧3和第二主侧4。贯穿本说明书，术语“碳化硅”可指碳化硅的任何多型，具体来说，它可指4H-SiC或6H-SiC。按照从第一主侧3到第二主侧4的顺序，SiC晶圆2包括n+掺杂源极层5、p掺杂体层6、n-掺杂漂移层7和n+掺杂漏极层8。漂移层7和漏极层8形成n掺杂衬底层9。源极层5通过体层6与漂移层7分隔，以及体层6通过漂移层7与漏极层8分隔。多个电传导栅极电极10穿透体层6。每个栅极电极10配置成在将电位施加到栅极电极10时通过电场来控制体层6中的沟道区的电传导率。在其中，每个沟道区是体层6的一部分，其从源极层5延伸到漂移层7。MOS沟道可经由沟道区从源极层5形成到漂移层7。栅极绝缘层11使栅极电极10与漂移层7、与体层6并且与源极层5电绝缘。
与沟道区直接相邻，n掺杂补偿层15在源极层5与漂移层7之间在栅极绝缘层11上延伸。补偿层15沿与栅极绝缘层11和补偿层15之间的界面正交的方向的厚度t COMP 、沟道长度L ch (其被定义为在栅极绝缘层11与补偿层15之间的界面上从源极层5到漂移层7的最短路径的长度)、以及栅极绝缘层11沿与栅极绝缘层11和补偿层15之间的界面正交的方向的厚度t GI 满足以下不等式：
(1)，
其中，ε CR 是沟道区的电容率，以及ε GI 是栅极绝缘层11的电容率。如上所指示的，由于具有与源极层5相同的导电类型的补偿层15，可能难以判定在什么深度(即，在离SiC晶圆2的第一主侧3的什么距离)，源极层5结束并且补偿层15开始。为了便于确定沟道长度L ch ，源极层5结束并且补偿层15开始于的深度被假定为在离栅极绝缘层11有0.1 μm的横向距离处在源极层5与体层6之间的p-n结的深度。同样，为了便于确定沟道长度L ch ，补偿层15结束并且漂移层7开始于的深度被假定为在离栅极绝缘层11有0.1 μm的横向距离处在体层6与漂移层7之间的p-n结的深度。沟道区被定义为体层6的一部分，其电传导率能够通过将电位施加到栅极电极10来控制。示范性地，沟道区被定义为体层的一部分，其具有离补偿层15小于0.1 μm的距离。
补偿层15的厚度t COMP 处于从1 nm至10 nm的范围中，示范性地处于从2 nm至5 nm的范围中。沟道长度L ch 可小于0.5 μm，示范性地小于0.3 μm。在按照本实施例的功率半导体装置中，栅极绝缘层11与补偿层15之间的界面与第一主侧3垂直。在这种情况下，沟道长度L ch 对应于在离栅极绝缘层11有0.1 μm的横向距离处在源极层5与漂移层7之间的距离，其是体层6在离栅极绝缘层11有0.1 μm的横向距离处沿与第一主侧3正交的方向的厚度。
补偿层15中的掺杂浓度可以为至少1·1018 cm-3，示范性地为至少5·1018 cm-3。沟道区中的掺杂浓度可以为至少5·1017 cm-3，示范性地为至少1·1018 cm-3，更示范性地为至少5·1018 cm-3。
漂移层7的厚度取决于标称电压（针对其来设计装置），即，取决于沿相反方向的最大阻断电压。例如，1 kV的标称阻断电压要求大约6 μm的漂移层7的厚度，以及5 kV的标称阻断电压要求大约36 μm的漂移层7的厚度。漂移层7的理想掺杂浓度也取决于标称电压，并且示范性地处于1·1015 cm-3与5·1016 cm-3之间的范围中。源极层5的厚度示范性地处于0.5 μm与5 μm之间的范围中，而源极层5的掺杂浓度示范性地为1·1018 cm-3或更多。
源极电极17被布置在SiC晶圆2的第一主侧3上。它形成到源极层5的欧姆接触部。为了避免由体层6、源极层5和漂移层7所形成的寄生双极晶体管的触发，体层6还被电连接到源极电极17。在SiC晶圆2的第二主侧4上，布置了漏极电极18，其形成到漏极层8的欧姆接触部。
在每个栅极电极10之下，形成了在栅极电极10底部之下与栅极绝缘层11直接相邻的p掺杂阱区42。阱区42通过漂移层7与体层6分隔。阱区42能够高效地保护栅极绝缘层11免受高电场。
在与第一主侧3平行并且在其之下的平面中，栅极电极10可具有任何形状的截面，示范性地为纵线形状、蜂窝形状、多边形形状、圆形形状、或椭圆形状。
参照图3A至图3G，在下面描述了用于制造图1和图2中所示的按照本发明的实施例的功率半导体装置的方法。在第一方法步骤中，如图3A中所示的，提供n掺杂第一半导体层20。第一半导体层20具有第一主侧23以及与第一主侧23相对的第二主侧24。它包括：n+掺杂SiC层25，其形成最终沟槽功率MOSFET 1中的漏极层8；以及n-掺杂SiC层26，其形成最终沟槽功率MOSFET 1中的漂移层7。n+掺杂SiC层25可以是SiC衬底晶圆，在其上通过例如化学气相沉积(CVD)外延地(epitactically)沉积n-掺杂SiC层26。备选地，n-掺杂SiC层26可以是衬底晶圆，在其上通过例如CVD外延地沉积n+掺杂SiC层25，或者在其中可通过例如离子注入而施加p型掺杂剂来形成n+掺杂SiC层25。
在此之后，如图3B中所示，p掺杂第二半导体层27在第一半导体层20的第一主侧23上被形成以与第一半导体层20直接接触。第二半导体层27可通过例如CVD外延地沉积到n-掺杂SiC层26上，或者它可通过例如离子注入而将n型掺杂剂从第一半导体层20的第一主侧23施加到第一半导体层20中来形成。通过离子注入来形成第二半导体层27要求通过热处理对所注入杂质进行后续激活。在最终沟槽功率MOSFET 1中，第二半导体层27形成p掺杂体层6。
在此之后，如图3C中所示，形成n+掺杂第三半导体层30(其与第二半导体层27直接接触，并且其通过第二半导体层27与第一半导体层20分隔)。具体来说，可使用如图3B中所示的注入掩模29通过离子注入而将第一n型杂质28施加到第二半导体层27中，来形成第三半导体层30。通过离子注入来形成第三半导体层30要求通过热处理对所注入杂质进行后续激活。第三半导体层30具有如图3C中所示的开口31，通过其而暴露第二半导体层27，以用于在后一阶段形成到源极电极17的电接触部(参见图1)。在最终沟槽功率MOSFET 1中，第三半导体层30形成源极层5。
在下一方法步骤中，在第一至第三半导体层20、27和30的堆叠中形成多个沟槽35，使得通过移除第二半导体层27的材料和第三半导体层30的材料，沟槽35穿透第三半导体层30到第二半导体层27中。移除第二半导体层27的材料和第三半导体层30的材料能够示范性地通过使用如图3C和图3D中所示的蚀刻掩模37对第二半导体层27和第三半导体层30进行选择性蚀刻来进行。沟槽35具有处于或接近第一半导体层20与第二半导体层27之间的界面的深度。
如图3D和图3E中所示，在形成沟槽35之后，第二n型杂质38被施加到每个沟槽35的侧壁中，以形成n掺杂半导体区39，其从第三半导体层30延伸到第一半导体层20。沟槽35的深度必须足够接近第一半导体层20与第二半导体层27之间的界面，以形成n掺杂半导体区39来从第三半导体层30延伸到第一半导体层20。在另一侧，将第二n型杂质38施加到第一半导体层20中应当被避免或者被减少到最小。为了取得后一目标，沟槽30不应当延伸到第一半导体层20中。第二n型杂质38可通过倾斜离子注入或者通过等离子体浸入离子注入而被施加到每个沟槽35的侧壁中。图3D中的斜箭头指倾斜离子注入。图3D中的箭头仅沿一个方向而被定向。但是，当使用倾斜离子注入时，分别使用多个不同角度来取得沿沟槽35的侧壁的均质掺杂浓度分布。
如图3F中所示，在将第二n型杂质38施加到每个沟槽35的侧壁中的步骤之后，通过移除第二半导体层27的材料和第一半导体层20的材料来加深沟槽35，使得经加深沟槽35'分别穿入第一半导体层20中。移除第二半导体层27的材料和第一半导体层20的材料可通过使用蚀刻掩模37的蚀刻步骤来执行。如图3E和图3F中所示，可通过经过每个经加深沟槽35'的底部将p型杂质41施加到第一半导体层20中而在每个经加深沟槽35'的底部之下形成p掺杂半导体阱区42。
在下一方法步骤中，绝缘层45被形成为覆盖每个经加深沟槽35'的侧壁和底部，并且在此之后，如图3G中所示，在绝缘层45上在经加深沟槽35'中形成电极层50。在其中，电极层50通过绝缘层45而与第一半导体层20、第二半导体层27、第三半导体层30和n掺杂半导体区39电绝缘。在形成绝缘层45之前，通过例如选择性蚀刻来移除蚀刻掩模37。电极层50可以是例如多晶硅层，以及绝缘层可以是例如氧化硅层。在图1和图2中所示的最终沟槽功率MOSFET 1中，电极层50形成栅极电极10，以及绝缘层45形成栅极绝缘层11。
随后，电极层50被构建(即，移除不是最终装置1中的栅极电极10的材料的电极层50的任何材料)并且被附加绝缘层所覆盖，在第三半导体层30上形成源极电极17，以及在第一半导体层20的第二主侧24上形成漏极电极18，以得到如图1和图2中所示的最终沟槽功率MOSFET 1。
在以上描述中，描述了具体实施例。但是，以上描述的实施例的备选和修改是可能的。
在用于制造图1中所示的功率半导体装置的以上描述的方法中，使用如图3B中所示的注入掩模29通过例如离子注入而将第一n型杂质28施加到第二半导体层27中来形成第三半导体层30。但是，还有可能通过其它方法(诸如通过例如CDV在第二半导体层27上外延地)来形成第三半导体层30。
在本发明的以上描述的实施例中，沟槽功率MOSFET 1包括p掺杂阱区42，以用于保护栅极绝缘层11免受高电场。但是，在修改实施例中，沟槽功率MOSFET 1不包括p掺杂阱区42。
在以上描述中，沟槽功率MOSFET 1作为本发明的功率半导体装置的实施例而被描述。但是，本发明不局限于沟槽功率MOSFET。例如，本发明的功率半导体装置的另一实施例是沟槽绝缘栅极双极晶体管(IGBT)。这种沟槽IGBT与以上描述的沟槽功率MOSFET 1在SiC晶圆2的第二主侧4上的附加p掺杂层的方面有所不同。
以上实施例采用特定导电类型来解释。可能交换以上描述的实施例中的半导体层的导电类型，使得在具体实施例中，被描述为p型层的所有层将是n型层，而被描述为n型层的使用层将是p型层。例如，在修改实施例中，源极层5可以是p掺杂层，体层6可以是n掺杂层，以及衬底层9可以是p掺杂层。
应当注意，术语“包括”不排除其它元素或步骤，并且不定冠词“一（a或an）”不排除多个。还可组合与不同实施例关联描述的元素。
参考标号列表
1 沟槽功率金属氧化物半导体场效应晶体管(MOSFET)
2 碳化硅(SiC)晶圆
3、23 第一主侧
4、24 第二主侧
5 (n+掺杂)源极层
6 (p掺杂)体层
7 (n-掺杂)漂移层
8 (n+掺杂)漏极层
9 (n掺杂)衬底层
10 栅极电极
11 栅极绝缘层
15 (n掺杂)补偿层
17 源极电极
18 漏极电极
20 (n掺杂)第一半导体层
23 第一主侧
24 第二主侧
25 n+掺杂SiC层
26 n-掺杂SiC层，
27 (p掺杂)第二半导体层
28 第一n型杂质
29 注入掩模
30 (n+掺杂)第三半导体层
31 开口
35 沟槽
35' 经加深沟槽
37 蚀刻掩模
38 第二n型杂质
39 n掺杂半导体区
42 p掺杂阱区
45 绝缘层
50 电极层
L ch 沟道长度
t COMP 补偿层15的厚度

Claims (15)

1.一种功率半导体装置，包括：
具有第一导电类型的衬底层(9)；
体层(6)，所述体层(6)被设置在所述衬底层(9)上，并且具有与所述第一导电类型不同的第二导电类型；
源极层(5)，所述源极层(5)被设置在所述体层(6)上，并且具有所述第一导电类型，其中所述体层(6)包括从所述源极层(5)延伸到所述衬底层(9)的沟道区，
电传导栅极电极(10)，所述电传导栅极电极(10)穿透所述体层(6)，用于控制所述沟道区的电传导率，
栅极绝缘层(11)，所述栅极绝缘层(11)使所述栅极电极(10)与所述衬底层(9)、与所述体层6并且与所述源极层(5)电绝缘，
所述第一导电类型的补偿层(15)，所述补偿层(15)与所述沟道区直接相邻地在所述源极层(5)与所述衬底层(9)之间在所述栅极绝缘层(11)上直接延伸，所述沟道区被定义为具有离所述补偿层(15)小于0.1 μm的距离的所述体层(6)的一部分，其中：
，
其中，L ch 是沟道长度，ε CR 是所述沟道区的电容率，ε GI 是所述栅极绝缘层(11)的电容率，t COMP 是所述补偿层(15)沿与所述栅极绝缘层(11)和所述补偿层(15)之间的界面正交的方向的厚度，以及t GI 是所述栅极绝缘层(11)的厚度，
其特征在于，所述补偿层(15)的所述厚度t COMP 处于从1 nm至10 nm的范围中。
2. 根据权利要求1所述的功率半导体装置，其中，所述补偿层(15)的所述厚度t COMP 处于从2 nm至5 nm的范围中。
3. 根据权利要求1或2所述的功率半导体装置，其中，所述沟道长度L ch 小于0.5 μm。
4. 根据权利要求1或2所述的功率半导体装置，其中，所述沟道长度(L ch )小于0.3 μm。
5. 根据权利要求1至4中任一项所述的功率半导体装置，其中，所述补偿层(15)中的掺杂浓度为至少1·1018 cm-3。
6. 根据权利要求5所述的功率半导体装置，其中，所述补偿层(15)中的掺杂浓度为至少5·1018 cm-3。
7. 根据权利要求1至6中任一项所述的功率半导体装置，其中，所述沟道区中的掺杂浓度为至少5·1017 cm-3。
8. 根据权利要求1至6中任一项所述的功率半导体装置，其中，所述沟道区中的掺杂浓度为至少1·1018 cm-3或者为至少5·1018 cm-3。
9.根据权利要求1至8中任一项所述的功率半导体装置，其中，所述衬底层(9)、所述体层(6)、所述补偿层(15)和所述源极层(5)是碳化硅层。
10.根据权利要求1至9中任一项所述的功率半导体装置，包括所述第二导电类型的阱区(42)，其中所述阱区(42)在所述栅极电极(10)的底部之下与所述栅极绝缘层(11)直接相邻。
11.一种用于制造根据权利要求1至10中任一项的功率半导体装置的方法，所述方法包括下列步骤：
提供第一导电类型的第一半导体层(20)，其中所述第一半导体层(20)具有第一主侧(23)以及与所述第一主侧(23)相对的第二主侧(24)，其中所述第一半导体层(20)形成所述功率半导体装置(1)中的衬底层(9)；
在所述第一半导体层(20)的所述第一主侧(23)上形成第二导电类型的第二半导体层(27)，所述第二半导体层(27)将与所述第一半导体层(20)直接接触，其中所述第二半导体层(27)形成所述功率半导体装置(1)中的体层；
形成所述第一导电类型的第三半导体层(30)，所述第三半导体层(30)与所述第二半导体层(20)直接接触，并且通过所述第二半导体层(27)与所述第一半导体层(20)分隔，其中所述第三半导体层(30)形成所述功率半导体装置(1)中的源极层(5)；
通过移除所述第三和第二半导体层(30，27)的材料来形成穿透所述第三半导体层(30)到所述第二半导体层(27)中的至少一个沟槽(35)；
将所述第一导电类型的杂质(38)施加到所述至少一个沟槽(35)的侧壁中，以形成所述第一导电类型的半导体区(38)，所述半导体区(38)将所述第三半导体层(30)与所述第一半导体层(20)相连接，其中所述半导体区(38)形成所述功率半导体装置(1)中的补偿层(15)；
通过移除所述第二和第一半导体层(20，27)的材料来加深所述沟槽(35)，使得经加深沟槽(35')穿入所述第一半导体层(20)中；
形成覆盖所述至少一个经加深沟槽(35')的所述侧壁和底部的绝缘层(45)，其中所述绝缘层(45)形成所述功率半导体装置(1)中的栅极绝缘层(11)；以及
在所述至少一个经加深沟槽(35')中形成电极层(50)，所述电极层(50)通过所述绝缘层(45)与所述第一半导体层(20)、所述第二半导体层(27)、所述第三半导体层(30)和所述第一导电类型的所述半导体区(38)电绝缘，其中所述电极层(50)形成所述功率半导体装置(1)中的栅极电极(10)。
12.根据权利要求11所述的用于制造功率半导体装置的方法，其中，通过倾斜离子注入来执行将所述第一导电类型的所述杂质(38)施加到所述至少一个沟槽(35)的所述侧壁中。
13.根据权利要求11所述的用于制造功率半导体装置的方法，其中，通过等离子体浸入离子注入来执行将所述第一导电类型的所述杂质(38)施加到所述至少一个沟槽(35)的所述侧壁中。
14.根据权利要求11至13中任一项所述的用于制造功率半导体装置的方法，其中，通过经过所述至少一个经加深沟槽(35')的所述底部将所述第二导电类型的杂质施加到所述第一半导体层(20)中而在所述至少一个经加深沟槽(35')的底部之下形成所述第二导电类型的半导体阱区(42)。
15.根据权利要求11至14中任一项所述的用于制造功率半导体装置的方法，其中，通过将所述第一导电类型的杂质施加到所述第二半导体层(27)中来形成所述第三半导体层(30)。
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JP2014239146A (ja) * 2013-06-07 2014-12-18 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法

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