JP7121237B2 - 閾値シフトの低減のためのシリコン窒化プロセス - Google Patents

閾値シフトの低減のためのシリコン窒化プロセス Download PDF

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JP7121237B2
JP7121237B2 JP2018567698A JP2018567698A JP7121237B2 JP 7121237 B2 JP7121237 B2 JP 7121237B2 JP 2018567698 A JP2018567698 A JP 2018567698A JP 2018567698 A JP2018567698 A JP 2018567698A JP 7121237 B2 JP7121237 B2 JP 7121237B2
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silicon nitride
nitride layer
nitrogen
substrate
rich
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JP2019519937A (ja
JP2019519937A5 (enExample
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ステファン デラス ニコラス
ティピルネニ ナヴィーン
セアップ リー ドン
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テキサス インスツルメンツ インコーポレイテッド
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
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    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2018567698A 2016-06-23 2017-06-23 閾値シフトの低減のためのシリコン窒化プロセス Active JP7121237B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/191,500 US9741557B1 (en) 2016-06-23 2016-06-23 Silicon nitride process for reduction of threshold shift
US15/191,500 2016-06-23
PCT/US2017/039150 WO2017223541A1 (en) 2016-06-23 2017-06-23 Silicon nitride process for reduction of threshold shift

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JP2019519937A JP2019519937A (ja) 2019-07-11
JP2019519937A5 JP2019519937A5 (enExample) 2020-07-30
JP7121237B2 true JP7121237B2 (ja) 2022-08-18

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US (1) US9741557B1 (enExample)
JP (1) JP7121237B2 (enExample)
CN (1) CN109219887B (enExample)
WO (1) WO2017223541A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016066641A (ja) * 2014-09-22 2016-04-28 株式会社東芝 半導体装置及び半導体装置の製造方法
US11037851B2 (en) * 2019-08-30 2021-06-15 Applied Materials, Inc. Nitrogen-rich silicon nitride films for thin film transistors
US11819847B2 (en) 2020-07-20 2023-11-21 Applied Materials, Inc. Nanofluidic device with silicon nitride membrane

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205392A (ja) 2007-02-22 2008-09-04 Fujitsu Ltd 半導体装置及びその製造方法
JP2009200306A (ja) 2008-02-22 2009-09-03 Eudyna Devices Inc 半導体装置の製造方法
US20110298060A1 (en) 2010-06-02 2011-12-08 International Business Machines Corporation Interface structure for channel mobility improvement in high-k metal gate stack
JP2015103780A (ja) 2013-11-28 2015-06-04 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972804A (en) * 1997-08-05 1999-10-26 Motorola, Inc. Process for forming a semiconductor device
US6709928B1 (en) * 2001-07-31 2004-03-23 Cypress Semiconductor Corporation Semiconductor device having silicon-rich layer and method of manufacturing such a device
JP2004111447A (ja) * 2002-09-13 2004-04-08 Handotai Rikougaku Kenkyu Center:Kk 半導体装置及びその製造方法
KR100560654B1 (ko) * 2004-01-08 2006-03-16 삼성전자주식회사 질화실리콘막을 형성을 위한 질소화합물 및 이를 이용한질화실리콘 막의 형성방법
CN102915952B (zh) * 2011-08-04 2014-11-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN103632968B (zh) * 2012-08-21 2016-10-05 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US9614105B2 (en) * 2013-04-22 2017-04-04 Cypress Semiconductor Corporation Charge-trap NOR with silicon-rich nitride as a charge trap layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205392A (ja) 2007-02-22 2008-09-04 Fujitsu Ltd 半導体装置及びその製造方法
JP2009200306A (ja) 2008-02-22 2009-09-03 Eudyna Devices Inc 半導体装置の製造方法
US20110298060A1 (en) 2010-06-02 2011-12-08 International Business Machines Corporation Interface structure for channel mobility improvement in high-k metal gate stack
JP2015103780A (ja) 2013-11-28 2015-06-04 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

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JP2019519937A (ja) 2019-07-11
CN109219887A (zh) 2019-01-15
US9741557B1 (en) 2017-08-22
WO2017223541A1 (en) 2017-12-28
CN109219887B (zh) 2022-11-01

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