JP7089144B2 - 側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入 - Google Patents

側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入 Download PDF

Info

Publication number
JP7089144B2
JP7089144B2 JP2018538593A JP2018538593A JP7089144B2 JP 7089144 B2 JP7089144 B2 JP 7089144B2 JP 2018538593 A JP2018538593 A JP 2018538593A JP 2018538593 A JP2018538593 A JP 2018538593A JP 7089144 B2 JP7089144 B2 JP 7089144B2
Authority
JP
Japan
Prior art keywords
oxide
field
region
gate
drift region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018538593A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019503085A5 (enExample
JP2019503085A (ja
Inventor
リッツマン エドワーズ ヘンリー
フー ビンホワ
ロバート トッド ジェームズ
Original Assignee
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by テキサス インスツルメンツ インコーポレイテッド filed Critical テキサス インスツルメンツ インコーポレイテッド
Publication of JP2019503085A publication Critical patent/JP2019503085A/ja
Publication of JP2019503085A5 publication Critical patent/JP2019503085A5/ja
Priority to JP2021201393A priority Critical patent/JP7429090B2/ja
Application granted granted Critical
Publication of JP7089144B2 publication Critical patent/JP7089144B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/118Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2252Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65Lateral DMOS [LDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65Lateral DMOS [LDMOS] FETs
    • H10D30/655Lateral DMOS [LDMOS] FETs having edge termination structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • H10D62/116Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393Body regions of DMOS transistors or IGBTs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/111Field plates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144Manufacturing their gate insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109Reduced surface field [RESURF] PN junction structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351Substrate regions of field-effect devices
    • H10D62/357Substrate regions of field-effect devices of FETs
    • H10D62/364Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
JP2018538593A 2016-01-21 2017-01-23 側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入 Active JP7089144B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021201393A JP7429090B2 (ja) 2016-01-21 2021-12-13 側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/003,776 US9583612B1 (en) 2016-01-21 2016-01-21 Drift region implant self-aligned to field relief oxide with sidewall dielectric
US15/003,776 2016-01-21
PCT/US2017/014581 WO2017127813A1 (en) 2016-01-21 2017-01-23 Drift region implant self-aligned to field relief oxide with sidewall dielectric

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2021201393A Division JP7429090B2 (ja) 2016-01-21 2021-12-13 側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入

Publications (3)

Publication Number Publication Date
JP2019503085A JP2019503085A (ja) 2019-01-31
JP2019503085A5 JP2019503085A5 (enExample) 2020-02-27
JP7089144B2 true JP7089144B2 (ja) 2022-06-22

Family

ID=58056574

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2018538593A Active JP7089144B2 (ja) 2016-01-21 2017-01-23 側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入
JP2021201393A Active JP7429090B2 (ja) 2016-01-21 2021-12-13 側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2021201393A Active JP7429090B2 (ja) 2016-01-21 2021-12-13 側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入

Country Status (5)

Country Link
US (4) US9583612B1 (enExample)
EP (1) EP3430647A4 (enExample)
JP (2) JP7089144B2 (enExample)
CN (1) CN108475678B (enExample)
WO (1) WO2017127813A1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711402B1 (en) * 2016-03-08 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming contact metal
US10361296B2 (en) 2017-06-29 2019-07-23 Monolith Semiconductor Inc. Metal oxide semiconductor (MOS) controlled devices and methods of making the same
US10424647B2 (en) * 2017-10-19 2019-09-24 Texas Instruments Incorporated Transistors having gates with a lift-up region
US10566200B2 (en) * 2018-04-03 2020-02-18 Texas Instruments Incorporated Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings
US11152505B2 (en) * 2018-06-28 2021-10-19 Texas Instruments Incorporated Drain extended transistor
US10707296B2 (en) 2018-10-10 2020-07-07 Texas Instruments Incorporated LOCOS with sidewall spacer for different capacitance density capacitors
US10529812B1 (en) 2018-10-10 2020-01-07 Texas Instruments Incorporated Locos with sidewall spacer for transistors and other devices
US11355596B2 (en) * 2019-12-17 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. High power device with self-aligned field plate
US11152381B1 (en) * 2020-04-13 2021-10-19 HeFeChip Corporation Limited MOS transistor having lower gate-to-source/drain breakdown voltage and one-time programmable memory device using the same
US11114140B1 (en) 2020-04-23 2021-09-07 HeFeChip Corporation Limited One time programmable (OTP) bits for physically unclonable functions
US11437082B2 (en) 2020-05-17 2022-09-06 HeFeChip Corporation Limited Physically unclonable function circuit having lower gate-to-source/drain breakdown voltage
CN113410139B (zh) * 2020-07-02 2025-06-03 台积电(中国)有限公司 半导体结构及其形成方法
US11398552B2 (en) * 2020-08-26 2022-07-26 Vanguard International Semiconductor Corporation High-voltage semiconductor device and method of forming the same
WO2022092035A1 (ja) * 2020-10-29 2022-05-05 ローム株式会社 半導体装置
US12288796B2 (en) 2021-01-27 2025-04-29 Samsung Electronics Co., Ltd. Semiconductor device and image sensor including the same
US11862670B2 (en) * 2021-05-13 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method for manufacturing the same
US11594630B2 (en) 2021-05-25 2023-02-28 Texas Instruments Incorporated Rugged LDMOS with reduced NSD in source
TWI792495B (zh) * 2021-08-16 2023-02-11 立錡科技股份有限公司 功率元件及其製造方法
US11876134B2 (en) * 2021-09-29 2024-01-16 Texas Instruments Incorporated Transistor device with buffered drain
US12464761B2 (en) * 2022-11-30 2025-11-04 Texas Instruments Incorporated LOCOS fillet for drain reduced breakdown in high voltage transistors
US20250040179A1 (en) * 2023-07-30 2025-01-30 Texas Instruments Incorporated Semiconductor device with a high k field relief dielectric structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100102388A1 (en) 2008-10-29 2010-04-29 Tower Semiconductor Ltd. LDMOS Transistor Having Elevated Field Oxide Bumps And Method Of Making Same

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4795716A (en) 1987-06-19 1989-01-03 General Electric Company Method of making a power IC structure with enhancement and/or CMOS logic
JP2609619B2 (ja) 1987-08-25 1997-05-14 三菱電機株式会社 半導体装置
JP3148227B2 (ja) * 1990-10-03 2001-03-19 セイコーインスツルメンツ株式会社 半導体装置の製造方法
US5322804A (en) 1992-05-12 1994-06-21 Harris Corporation Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps
JP3424694B2 (ja) * 1993-03-08 2003-07-07 セイコーインスツルメンツ株式会社 高耐圧絶縁ゲート型電界効果トランジスタ及び半導体集積回路装置
JP3802935B2 (ja) 1993-07-16 2006-08-02 三菱電機株式会社 高耐圧型半導体装置
US5517046A (en) * 1993-11-19 1996-05-14 Micrel, Incorporated High voltage lateral DMOS device with enhanced drift region
JPH0955502A (ja) 1995-08-14 1997-02-25 Sony Corp トランジスタ及びその製造方法
KR0167273B1 (ko) * 1995-12-02 1998-12-15 문정환 고전압 모스전계효과트렌지스터의 구조 및 그 제조방법
KR100468342B1 (ko) * 1996-05-15 2005-06-02 텍사스 인스트루먼츠 인코포레이티드 자기-정렬resurf영역을가진ldmos장치및그제조방법
KR100225411B1 (ko) * 1997-03-24 1999-10-15 김덕중 LDMOS(a lateral double-diffused MOS) 트랜지스터 소자 및 그의 제조 방법
US6110803A (en) * 1998-12-10 2000-08-29 United Microelectronics Corp. Method for fabricating a high-bias device
JP3443355B2 (ja) * 1999-03-12 2003-09-02 三洋電機株式会社 半導体装置の製造方法
US6392274B1 (en) * 2000-04-04 2002-05-21 United Microelectronics Corp. High-voltage metal-oxide-semiconductor transistor
JP3831598B2 (ja) * 2000-10-19 2006-10-11 三洋電機株式会社 半導体装置とその製造方法
US7719054B2 (en) * 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
CN1268005C (zh) * 2002-10-24 2006-08-02 松下电器产业株式会社 半导体装置及其制造方法
JP4801323B2 (ja) * 2004-02-13 2011-10-26 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2006202810A (ja) * 2005-01-18 2006-08-03 Sharp Corp 横型二重拡散型mosトランジスタおよびその製造方法
JP3897801B2 (ja) * 2005-08-31 2007-03-28 シャープ株式会社 横型二重拡散型電界効果トランジスタおよびそれを備えた集積回路
KR100660909B1 (ko) * 2006-01-06 2006-12-26 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8017486B2 (en) * 2007-06-22 2011-09-13 Macronix International Co., Ltd. Method of fabricating low on-resistance lateral double-diffused MOS device
US20090023046A1 (en) 2007-07-20 2009-01-22 Chao-Yang Wang Porous Transport Structures for Direct-Oxidation Fuel Cell System Operating with Concentrated Fuel
US7977715B2 (en) * 2008-03-17 2011-07-12 Fairchild Semiconductor Corporation LDMOS devices with improved architectures
US8119507B2 (en) * 2008-10-23 2012-02-21 Silergy Technology Lateral double-diffused metal oxide semiconductor (LDMOS) transistors
US9484454B2 (en) * 2008-10-29 2016-11-01 Tower Semiconductor Ltd. Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure
JP2010278312A (ja) * 2009-05-29 2010-12-09 Sanyo Electric Co Ltd 半導体装置
JP5534298B2 (ja) * 2009-06-16 2014-06-25 ルネサスエレクトロニクス株式会社 半導体装置
JP5457902B2 (ja) 2010-03-26 2014-04-02 旭化成エレクトロニクス株式会社 半導体装置及びその製造方法
US20110241114A1 (en) * 2010-04-02 2011-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage mos transistor
US8304830B2 (en) * 2010-06-10 2012-11-06 Macronix International Co., Ltd. LDPMOS structure for enhancing breakdown voltage and specific on resistance in biCMOS-DMOS process
US20130087828A1 (en) 2010-06-21 2013-04-11 Renesas Electronics Corporation Semiconductor device and method for manufacturing same
US8269277B2 (en) * 2010-08-11 2012-09-18 Fairchild Semiconductor Corporation RESURF device including increased breakdown voltage
US9171916B1 (en) * 2011-10-13 2015-10-27 Maxim Integrated Products, Inc. LDMOS with thick interlayer-dielectric layer
US8592274B2 (en) 2012-03-27 2013-11-26 Alpha And Omega Semiconductor Incorporated LDMOS with accumulation enhancement implant
CN103489912B (zh) * 2012-06-12 2016-02-24 无锡华润上华半导体有限公司 一种高压结型场效应晶体管
US8624322B1 (en) 2012-07-17 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage device with a parallel resistor
US9299831B2 (en) * 2012-10-16 2016-03-29 Asahi Kasei Microdevices Corporation Field effect transistor and semiconductor device
US9000517B2 (en) * 2013-01-11 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Power MOSFETs and methods for forming the same
US9653561B2 (en) * 2013-03-12 2017-05-16 Macronix International Co., Ltd. Low on resistance semiconductor device
US9379541B2 (en) * 2013-09-26 2016-06-28 Globalfoundries Inc. EOS protection circuit with FET-based trigger diodes
US9337330B2 (en) * 2013-12-19 2016-05-10 Texas Instruments Incorporated Scheme to align LDMOS drain extension to moat
CN104241384B (zh) * 2014-09-23 2018-02-23 矽力杰半导体技术(杭州)有限公司 横向双扩散金属氧化物半导体晶体管的制造方法
KR101699585B1 (ko) * 2014-09-24 2017-01-24 주식회사 동부하이텍 고전압 반도체 소자 및 그 제조 방법
US10050115B2 (en) * 2014-12-30 2018-08-14 Globalfoundries Inc. Tapered gate oxide in LDMOS devices
US9876071B2 (en) * 2015-02-28 2018-01-23 Texas Instruments Incorporated Structures to avoid floating RESURF layer in high voltage lateral devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100102388A1 (en) 2008-10-29 2010-04-29 Tower Semiconductor Ltd. LDMOS Transistor Having Elevated Field Oxide Bumps And Method Of Making Same

Also Published As

Publication number Publication date
CN108475678A (zh) 2018-08-31
US20170213895A1 (en) 2017-07-27
CN108475678B (zh) 2023-08-15
JP7429090B2 (ja) 2024-02-07
US10497787B2 (en) 2019-12-03
JP2022031913A (ja) 2022-02-22
US10096685B2 (en) 2018-10-09
EP3430647A4 (en) 2019-09-18
US10861948B2 (en) 2020-12-08
WO2017127813A1 (en) 2017-07-27
US20170213893A1 (en) 2017-07-27
EP3430647A1 (en) 2019-01-23
US9583612B1 (en) 2017-02-28
JP2019503085A (ja) 2019-01-31
US20200083336A1 (en) 2020-03-12

Similar Documents

Publication Publication Date Title
JP7429090B2 (ja) 側壁誘電体を備えるフィールド緩和酸化物に自己整合されるドリフト領域注入
US9466700B2 (en) Semiconductor device and method of fabricating same
US6426279B1 (en) Epitaxial delta doping for retrograde channel profile
US7560755B2 (en) Self aligned gate JFET structure and method
CN112913002B (zh) 用于晶体管及其它装置的具有侧壁间隔件的locos
JP4597531B2 (ja) チャネル領域のドーパント分布がレトログレードな半導体デバイスおよびそのような半導体デバイスの製造方法
CN101159289B (zh) 绝缘体上硅fet及其方法
JP2005094012A (ja) 半導体基体にdmosトランジスタを作製する方法
US9806190B2 (en) High voltage drain extension on thin buried oxide SOI
US8748980B2 (en) U-shape RESURF MOSFET devices and associated methods of manufacturing
JPH10200110A (ja) 半導体装置及びその製造方法
US9184163B1 (en) Low cost transistors
WO2012011225A1 (ja) 半導体装置及びその製造方法
US20050260818A1 (en) Semiconductor device and method for fabricating the same
CN107799418A (zh) 半导体结构及其形成方法
US20250006836A1 (en) Semiconductor device with nitrogen doped field relief dielectric layer
CN106548943A (zh) 晶体管及其形成方法
KR20100020688A (ko) Ldmos 반도체 소자와 그 제조 방법
KR101063567B1 (ko) Mos 디바이스 및 그 제조방법
CN107546276A (zh) 带有注入式背栅的集成jfet结构
US20240178283A1 (en) Ldmos device and method of fabrication of same
KR20120120038A (ko) 모스 반도체 디바이스 및 그 제조 방법
KR100778861B1 (ko) Ldmos 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20180723

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200120

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200120

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20210218

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210323

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210602

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210616

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20210915

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20211115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211213

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220511

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220511

R150 Certificate of patent or registration of utility model

Ref document number: 7089144

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250