JP7080322B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7080322B2 JP7080322B2 JP2020529912A JP2020529912A JP7080322B2 JP 7080322 B2 JP7080322 B2 JP 7080322B2 JP 2020529912 A JP2020529912 A JP 2020529912A JP 2020529912 A JP2020529912 A JP 2020529912A JP 7080322 B2 JP7080322 B2 JP 7080322B2
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- thick copper
- wiring pattern
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 334
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 172
- 229910052802 copper Inorganic materials 0.000 claims description 172
- 239000010949 copper Substances 0.000 claims description 172
- 239000002184 metal Substances 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 229920005989 resin Polymers 0.000 claims description 39
- 239000011347 resin Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 22
- 238000007789 sealing Methods 0.000 claims description 10
- 239000000919 ceramic Substances 0.000 claims description 9
- 239000003822 epoxy resin Substances 0.000 claims description 9
- 229920000647 polyepoxide Polymers 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 description 41
- 239000000463 material Substances 0.000 description 36
- 238000010586 diagram Methods 0.000 description 13
- 230000017525 heat dissipation Effects 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000004891 communication Methods 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000010295 mobile communication Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000003063 flame retardant Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 239000007784 solid electrolyte Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6611—Wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6644—Packaging aspects of high-frequency amplifiers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6683—High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0243—Printed circuits associated with mounted high frequency components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10166—Transistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/10886—Other details
- H05K2201/10924—Leads formed from a punched metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
図1は、実施の形態1に係る半導体装置の断面の模式図である。図2は図1の半導体装置の表面側の部品配置を示す図であり、図3は図1の半導体装置の裏面を示す図である。図1の断面の模式図は、図2におけるA-Aの断面の模式図である。実施の形態1の半導体装置50は、プリント基板3と、半導体チップ1、2と、電子部品4と、プリント基板3の裏面に形成された厚銅部材14と、半導体チップ1、2、電子部品4及びプリント基板3の表面(裏面と反対側の面)を封止するキャップ10とを備えている。プリント基板3は一般的に用いられる汎用のプリント基板である。プリント基板3は、FR-4(Flame Retardant Type 4)、FR-5(Flame Retardant Type 5)等の樹脂をベースとした材料を用いた樹脂基材23と、その樹脂基材23の表面又は内層に配線パターン21により形成された高周波回路と、プリント基板3の一部に貫通した穴である開口部29とを備えている。厚銅部材14は100μm以上の厚みを持つ厚銅であり、厚銅部材14により外部電極端子5、6が形成されている。外部電極端子5は半導体チップ1、2を搭載する外部電極端子であり、外部電極端子6は外部電極端子5の外周側に配置された外部電極端子である。プリント基板3の開口部29は、外部電極端子5の表面の一部を露出するように形成されている。半導体チップ1は、周波数1GHz以上の高周波信号を処理し、1W以上の電力を出力する、すなわち高電力密度で能動的な動作を行う半導体素子(能動素子)が形成された半導体チップである。半導体チップ1に形成された能動素子は、例えば、高電力密度のGaN素子である。半導体チップ2は、半導体装置50に搭載される高周波回路の一部を構成する伝送線路等の受動素子が形成された半導体チップである。半導体チップ2は、例えばGaAsなどの半導体のチップである。
図5は、実施の形態2に係る半導体装置の断面の模式図である。実施の形態1の半導体装置50と同一構成要素には同一符号を付して重複する説明を省略する。なお、他の実施の形態においても、実施の形態1の半導体装置50と同一構成要素には同一符号を付して重複する説明を省略する。実施の形態2の半導体装置50は、プリント基板3の開口部29の側面に凹部11が形成されている、すなわち開口部29の側面に凹部11を有する点で、実施の形態1の半導体装置50と異なる。なお、凹部11は、開口部29の側面のどの位置にあってもよい。
図6は、実施の形態3に係る半導体装置の断面の模式図である。実施の形態3の半導体装置50は、プリント基板3の表面に形成された第一配線パターン22aの厚銅部材14を基準にした高さが、半導体チップ1、2の厚銅部材14を基準にした高さの-10%から+10%である点で、実施の形態1の半導体装置50と異なる。図6では、プリント基板3の表面に形成された第一配線パターン22aの厚銅部材14を基準にした高さが半導体チップ1、2の厚銅部材14を基準にした高さと等しい例、すなわちプリント基板3の表面に形成された第一配線パターン22aの表面位置と半導体チップ1、2との表面位置が等しい例を示した。図6に示したように厚銅部材14を基準にした第一配線パターン22aの表面位置と半導体チップ1、2との表面位置とが等しくなっている。実施の形態3の半導体装置50は、厚銅部材14を基準にした第一配線パターン22aの表面位置と半導体チップ1、2との表面位置とが等しくなっているので、プリント基板3の第一配線パターン22aと半導体チップ1、2とを接続する金属ワイヤ12の長さを最短で形成することができる。
図7は、実施の形態4に係る半導体装置の断面の模式図である。実施の形態4の半導体装置50は、プリント基板3が多層プリント基板であり、階段状に形成された開口部29により露出された内部の第二配線パターン22bの厚銅部材14を基準にした高さが、半導体チップ1、2の厚銅部材14を基準にした高さの-10%から+10%である点で、実施の形態1の半導体装置50と異なる。図7では、階段状に形成された開口部29により露出された内部の第二配線パターン22bの厚銅部材14を基準にした高さが半導体チップ1、2の厚銅部材14を基準にした高さと等しい例、すなわち階段状に形成された開口部29により露出された内部の第二配線パターン22bの表面位置と半導体チップ1、2との表面位置が等しい例を示した。図7に示したように厚銅部材14を基準にしたプリント基板3の内部の第二配線パターン22bの表面位置と半導体チップ1、2との表面位置とが等しくなっている。実施の形態4の半導体装置50は、厚銅部材14を基準にしたプリント基板3の内部の第二配線パターン22bの表面位置と半導体チップ1、2との表面位置とが等しくなっているので、プリント基板3の第二配線パターン22bと半導体チップ1、2とを接続する金属ワイヤ12の長さを最短で形成することができる。
図8は、実施の形態5に係る半導体装置の断面の模式図である。図9は図8の接続部材の第一例を示す図であり、図10は図8の接続部材の第二例を示す図である。図11は、図8の半導体装置の裏面を示す図である。実施の形態5の半導体装置50は、厚銅部材14の表面側(半導体チップ1、2の実装面側)に配置された第一のプリント基板(表面側プリント基板)3aと、厚銅部材14の裏面側(半導体チップ1、2の実装面と反対の面側)に第二のプリント基板(裏面側プリント基板)3bとを備えた点で、実施の形態1の半導体装置50と異なる。実施の形態5の半導体装置50は、図1に示した構成において厚銅部材14の裏面に更に第二のプリント基板3bが配置されている。
図12は、実施の形態6に係る半導体装置の断面の模式図である。実施の形態6の半導体装置50は、第二のプリント基板3bが半導体チップ1の直下領域を含むように形成された開口部29と開口部29を埋める銅層24とを備える点で、実施の形態5の半導体装置50と異なる。厚銅部材14の裏面側(半導体チップ1、2の実装面と反対の面側)に配置された第二のプリント基板3bは、能動素子が形成された半導体チップ1の直下領域を含むように開口部29が形成されている。すなわち、第二のプリント基板3bに形成された開口部29は、半導体チップ1が実装された領域が厚銅部材14を基準にした対称の位置である半導体チップ対称領域を含むように形成されている。銅層24は、第二のプリント基板3bに形成された開口部29を埋めるように形成されており、すなわち半導体チップ1が実装された領域が厚銅部材14を基準にした対称の位置である半導体チップ対称領域を覆うように配置されている。図12では、第一のプリント基板3aに形成された開口部29よりも、広い範囲で第二のプリント基板3bの開口部29が形成されている例を示した。第二のプリント基板3bの開口部29は、第二のプリント基板3bの開口部形成工程にて形成される。第二のプリント基板3bの開口部形成工程は、最表面(裏面側の露出面)の第一配線パターン22aが形成される前に、レーザ或いはドリルで厚銅部材14に達する開口部29を形成する。その後、開口部29に例えばめっきにより銅層24を第一配線パターン22aの形成前の樹脂基材23と同一面になるように成長させる。樹脂基材23及び銅層24の露出面に第一配線パターン22aを形成する(外部電極端子形成工程)。外部電極端子5、6は、第二のプリント基板3bの露出面の第一配線パターン22aに形成されている。
Claims (7)
- 実装される実装対象装置に接続する複数の外部電極端子が裏面に形成されると共に、高周波信号を処理する半導体チップが搭載された半導体装置であって、
前記半導体チップが実装される厚銅部材と、
前記厚銅部材の表面に配置されると共に、前記厚銅部材の表面の一部を露出する開口部と、配線パターンと、前記配線パターンと前記厚銅部材とを接続する導電性のビアと、を備えたプリント基板と、
前記厚銅部材の裏面に配置されると共に、他の配線パターンと、前記他の配線パターンと前記厚銅部材とを接続する導電性の他のビアと、を備えた他のプリント基板であって、前記厚銅部材と逆側に露出するように形成された前記他の配線パターンが複数の前記外部電極端子を構成している裏面側プリント基板と、
前記配線パターンと前記他の配線パターンとを接続する導電性の接続部材と、
前記開口部により露出された前記厚銅部材の表面に実装されると共に、前記配線パターンに金属ワイヤで接続された前記半導体チップと、
前記厚銅部材と逆側である前記プリント基板の表面に実装されると共に前記配線パターンに接続された電子部品と、
前記厚銅部材と逆側である前記プリント基板の表面、前記半導体チップ、前記電子部品、前記金属ワイヤを封止するキャップ又はエポキシ樹脂と、を備え、
前記裏面側プリント基板は、前記厚銅部材と反対側の表面に形成された一つの前記外部電極端子と前記厚銅部材の裏面とを接続する銅層を備え、
前記銅層は、前記半導体チップが実装された領域が前記厚銅部材を基準にした対称の位置である半導体チップ対称領域を含むように、かつ前記裏面側プリント基板に形成された開口部を埋めるように形成されており、
前記銅層により埋められた前記裏面側プリント基板の開口部は、前記プリント基板の前記開口部よりも広く形成されていることを特徴とする半導体装置。 - 前記接続部材は、外周側に形成された絶縁性の樹脂と、前記樹脂の内側に形成された金属の層と、前記金属の層の内側に形成された導電性樹脂と、を備えたことを特徴とする請求項1記載の半導体装置。
- 前記接続部材は、外周側に形成された絶縁性の樹脂と、前記樹脂の内側に形成された金属の層と、前記金属の層の内側に形成された絶縁性の樹脂と、を備えたことを特徴とする請求項1記載の半導体装置。
- 前記プリント基板は、前記開口部の側面に凹部を有することを特徴とする請求項1から3のいずれか1項に記載の半導体装置。
- 前記厚銅部材と逆側である前記プリント基板の表面に形成された前記配線パターンは、前記厚銅部材を基準にした高さが、前記厚銅部材を基準にした前記半導体チップの高さの-10%から+10%の高さであることを特徴とする請求項1から4のいずれか1項に記載の半導体装置。
- 前記プリント基板は多層プリント基板であり、
前記プリント基板の前記開口部は、内部に形成された前記配線パターンの一部を露出するように階段状に形成されており、
前記開口部により露出された前記配線パターンは、前記厚銅部材を基準にした高さが、前記厚銅部材を基準にした前記半導体チップの高さの-10%から+10%の高さであることを特徴とする請求項1から4のいずれか1項に記載の半導体装置。 - 前記半導体チップは、能動素子が形成されており、
受動素子が形成された他の半導体チップ又はセラミック基板をさらに備え、
前記他の半導体チップ又は前記セラミック基板は、前記開口部により露出された前記厚銅部材の表面に実装されると共に、前記配線パターン及び前記半導体チップに金属ワイヤで接続されており、
前記他の半導体チップ又は前記セラミック基板は、前記キャップ又はエポキシ樹脂により封止されていることを特徴とする請求項1から6のいずれか1項に記載の半導体装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2018/026324 WO2020012598A1 (ja) | 2018-07-12 | 2018-07-12 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2020012598A1 JPWO2020012598A1 (ja) | 2021-04-30 |
JP7080322B2 true JP7080322B2 (ja) | 2022-06-03 |
Family
ID=69142358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020529912A Active JP7080322B2 (ja) | 2018-07-12 | 2018-07-12 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11557554B2 (ja) |
JP (1) | JP7080322B2 (ja) |
CN (1) | CN112335034A (ja) |
TW (1) | TWI725426B (ja) |
WO (1) | WO2020012598A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4089731A4 (en) * | 2020-01-10 | 2024-01-10 | Sumitomo Electric Industries, Ltd. | HIGH FREQUENCY AMPLIFIER |
US20240145330A1 (en) | 2021-05-27 | 2024-05-02 | Mitsubishi Electric Corporation | Semiconductor device |
US11862688B2 (en) * | 2021-07-28 | 2024-01-02 | Apple Inc. | Integrated GaN power module |
US12063763B2 (en) * | 2021-09-14 | 2024-08-13 | Hamilton Sundstrand Corporation | Cooling in conductors for chips |
JP7471538B2 (ja) | 2022-04-28 | 2024-04-19 | 三菱電機株式会社 | 半導体装置 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003046022A (ja) | 2001-05-22 | 2003-02-14 | Hitachi Ltd | 電子装置 |
JP2004031812A (ja) | 2002-06-27 | 2004-01-29 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
JP2006147822A (ja) | 2004-11-19 | 2006-06-08 | Murata Mfg Co Ltd | 多層セラミック基板およびその製造方法 |
JP2007096083A (ja) | 2005-09-29 | 2007-04-12 | Sanyo Electric Co Ltd | 混成集積回路装置 |
JP2008153400A (ja) | 2006-12-15 | 2008-07-03 | Fujitsu Ltd | 回路基板、その製造方法及び半導体装置 |
JP2010186880A (ja) | 2009-02-12 | 2010-08-26 | Hitachi Metals Ltd | 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 |
JP2010219554A (ja) | 2010-06-04 | 2010-09-30 | Hitachi Automotive Systems Ltd | 半導体装置及びそれを用いた電子制御装置 |
JP2011166029A (ja) | 2010-02-12 | 2011-08-25 | Panasonic Corp | 配線基板、それを用いた電子装置、及び配線基板の製造方法 |
JP2015035495A (ja) | 2013-08-08 | 2015-02-19 | 住友電工デバイス・イノベーション株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6376908B1 (en) * | 1997-12-10 | 2002-04-23 | Mitsubishi Gas Chemical Company, Inc. | Semiconductor plastic package and process for the production thereof |
JP2001250881A (ja) | 2000-03-07 | 2001-09-14 | Oki Business Co Ltd | 電力増幅器の実装基板 |
JP2002076637A (ja) * | 2000-08-29 | 2002-03-15 | Matsushita Electric Ind Co Ltd | チップ部品内蔵基板及びその製造方法 |
US6744135B2 (en) | 2001-05-22 | 2004-06-01 | Hitachi, Ltd. | Electronic apparatus |
US6683512B2 (en) | 2001-06-21 | 2004-01-27 | Kyocera Corporation | High frequency module having a laminate board with a plurality of dielectric layers |
US6873529B2 (en) * | 2002-02-26 | 2005-03-29 | Kyocera Corporation | High frequency module |
DE102004016399B4 (de) * | 2003-03-27 | 2013-06-06 | Kyocera Corp. | Hochfrequenzmodul und Funkvorrichtung |
US8345433B2 (en) * | 2004-07-08 | 2013-01-01 | Avx Corporation | Heterogeneous organic laminate stack ups for high frequency applications |
JP4736451B2 (ja) | 2005-02-03 | 2011-07-27 | パナソニック株式会社 | 多層配線基板とその製造方法、および多層配線基板を用いた半導体パッケージと電子機器 |
JP4155985B2 (ja) | 2005-08-29 | 2008-09-24 | 三洋電機株式会社 | 回路基板およびそれを用いた回路装置 |
US7683266B2 (en) | 2005-07-29 | 2010-03-23 | Sanyo Electric Co., Ltd. | Circuit board and circuit apparatus using the same |
JP5100081B2 (ja) * | 2006-10-20 | 2012-12-19 | 新光電気工業株式会社 | 電子部品搭載多層配線基板及びその製造方法 |
-
2018
- 2018-07-12 WO PCT/JP2018/026324 patent/WO2020012598A1/ja active Application Filing
- 2018-07-12 CN CN201880094847.7A patent/CN112335034A/zh active Pending
- 2018-07-12 US US17/050,567 patent/US11557554B2/en active Active
- 2018-07-12 JP JP2020529912A patent/JP7080322B2/ja active Active
-
2019
- 2019-05-16 TW TW108116892A patent/TWI725426B/zh active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003046022A (ja) | 2001-05-22 | 2003-02-14 | Hitachi Ltd | 電子装置 |
JP2004031812A (ja) | 2002-06-27 | 2004-01-29 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
JP2006147822A (ja) | 2004-11-19 | 2006-06-08 | Murata Mfg Co Ltd | 多層セラミック基板およびその製造方法 |
JP2007096083A (ja) | 2005-09-29 | 2007-04-12 | Sanyo Electric Co Ltd | 混成集積回路装置 |
JP2008153400A (ja) | 2006-12-15 | 2008-07-03 | Fujitsu Ltd | 回路基板、その製造方法及び半導体装置 |
JP2010186880A (ja) | 2009-02-12 | 2010-08-26 | Hitachi Metals Ltd | 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法 |
JP2011166029A (ja) | 2010-02-12 | 2011-08-25 | Panasonic Corp | 配線基板、それを用いた電子装置、及び配線基板の製造方法 |
JP2010219554A (ja) | 2010-06-04 | 2010-09-30 | Hitachi Automotive Systems Ltd | 半導体装置及びそれを用いた電子制御装置 |
JP2015035495A (ja) | 2013-08-08 | 2015-02-19 | 住友電工デバイス・イノベーション株式会社 | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20210242144A1 (en) | 2021-08-05 |
TWI725426B (zh) | 2021-04-21 |
US11557554B2 (en) | 2023-01-17 |
CN112335034A (zh) | 2021-02-05 |
JPWO2020012598A1 (ja) | 2021-04-30 |
TW202006900A (zh) | 2020-02-01 |
WO2020012598A1 (ja) | 2020-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7080322B2 (ja) | 半導体装置 | |
KR100579621B1 (ko) | 레드리스 멀티-다이 캐리어의 구조 및 제조방법 | |
KR100612425B1 (ko) | 안테나가 내장된 무연 칩 캐리어의 구조 및 제조방법 | |
JP6440917B1 (ja) | 半導体装置 | |
KR100786001B1 (ko) | 인덕터가 내장된 무연 칩 캐리어의 구조 및 제조방법 | |
US7411281B2 (en) | Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same | |
KR100839067B1 (ko) | 전자 회로 모듈과 그 제조 방법 | |
US20080315396A1 (en) | Mold compound circuit structure for enhanced electrical and thermal performance | |
US20140251658A1 (en) | Thermally enhanced wiring board with built-in heat sink and build-up circuitry | |
JP3426842B2 (ja) | 高周波用電力増幅器 | |
US6787896B1 (en) | Semiconductor die package with increased thermal conduction | |
US20140355215A1 (en) | Embedded Heat Slug to Enhance Substrate Thermal Conductivity | |
US9018741B2 (en) | Semiconductor package and manufacturing method thereof | |
CN107123601B (zh) | 一种高散热器件封装结构和板级制造方法 | |
JP5577694B2 (ja) | 部品内蔵モジュール | |
JP2000323610A (ja) | フィルムキャリア型半導体装置 | |
KR100693168B1 (ko) | 인쇄회로기판 및 그 제조방법 | |
JP2005340713A (ja) | マルチチップモジュール | |
KR20050073678A (ko) | 비지에이 타입 패키지의 제조방법 | |
WO2004073064A1 (ja) | 半導体装置 | |
JP2000353770A (ja) | 集積回路パッケージ、ミリ波集積回路パッケージ、及び集積回路パッケージを基板に組立及び実装する方法 | |
KR20030060268A (ko) | 본딩패드 접속용 비아홀을 이용한 비지에이 반도체패키지의 제조방법 및 그 구조 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20201007 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20201007 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20210831 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20211007 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220308 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220407 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220426 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220524 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 7080322 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |