JP6998740B2 - 液晶表示パネル - Google Patents
液晶表示パネル Download PDFInfo
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- JP6998740B2 JP6998740B2 JP2017221316A JP2017221316A JP6998740B2 JP 6998740 B2 JP6998740 B2 JP 6998740B2 JP 2017221316 A JP2017221316 A JP 2017221316A JP 2017221316 A JP2017221316 A JP 2017221316A JP 6998740 B2 JP6998740 B2 JP 6998740B2
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- liquid crystal
- crystal display
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Description
まず、液晶表示パネルLCPを用いた液晶表示装置LCD1の概略構成について、図1及び図2を用いて説明する。図1は、実施の形態1に係る液晶表示装置LCD1の概略構成を模式的に示す図である。図2は、実施の形態1に係る液晶表示パネルLCPの画素回路を示す図である。
次に、実施の形態2に係る液晶表示装置LCD2について、図13、図14A及び図14Bを用いて説明する。図13は、実施の形態2に係る液晶表示装置LCD2の概略構成を模式的に示す図である。図14Aは、実施の形態2に係る液晶表示装置LCD2における第1液晶表示パネルLCP1の画素のレイアウトを示す図である。図14Bは、実施の形態2に係る液晶表示装置LCD2における第2液晶表示パネルLCP2の画素のレイアウトを示す図である。
以上、本開示に係る液晶表示パネル及び液晶表示装置について、実施の形態に基づいて説明したが、本開示は、上記実施の形態に限定されるものではない。
LCP 液晶表示パネル
LCP1 第1液晶表示パネル
LCP2 第2液晶表示パネル
BL バックライト
PDC 液晶表示パネル駆動回路
SDC ソースドライバ
SDC1 第1ソースドライバ
SDC2 第2ソースドライバ
GDC ゲートドライバ
GDC1 第1ゲートドライバ
GDC2 第2ゲートドライバ
IPU 画像処理部
TC1 第1タイミングコントローラ
TC2 第2タイミングコントローラ
DSP 画像表示領域
DSP1 第1画像表示領域
DSP2 第2画像表示領域
PIX 画素
PIX1 第1画素
PIX2 第2画素
PIXR 赤色用画素
PIXG 緑色用画素
PIXB 青色用画素
SL 映像信号線
SL1 第1映像信号線
SL2 第2映像信号線
GL 走査線
GL1 第1走査線
GL2 第2走査線
PIT 画素電極
PIT1 第1画素電極
PIT2 第2画素電極
PITL ライン電極
PITC 連結電極
MIT 共通電極
CMT コモン線
TR トランジスタ
D ドレイン電極
G ゲート電極
S ソース電極
SC 半導体層
GI ゲート絶縁層
SUB1 第1基板
SUB2 第2基板
LCL 液晶層
TSUB1 第1透明基材
TSUB2 第2透明基材
BM 遮光層
PI 配向膜
MET 金属電極
IL 絶縁層
PAS 第1絶縁膜
OPAS 第2絶縁膜
UPS 第3絶縁膜
CH コンタクトホール
CH1 コンタクト部
CH2 延伸部
LDL リード線
LDLC 共通リード線
LDL1 第1個別リード線
LDL2 第2個別リード線
STF 積層膜
STF1 第1の膜
STF2 第2の膜
PS1 第1スペーサ
PS2 第2スペーサ
STS1 第1積層構造体
STS11 第1の膜
STS12 第2の膜
STS13 第3の膜
STS2 第2積層構造体
STS21 第1の膜
STS22 第2の膜
STS23 第3の膜
STS24 第4の膜
STS25 第5の膜
CNCT 接続電極
Claims (17)
- マトリクス状に配列された複数の画素を有する液晶表示パネルであって、
前記複数の画素の各々に複数ずつ設けられた画素電極及びトランジスタと、
第1方向に配列された前記複数の画素の各々における複数の前記トランジスタと接続された走査線と、
前記第1方向に隣り合う2つの前記画素の境界部ごとに設けられ、前記第1方向に直交する第2方向に延在する映像信号線と、
前記複数の画素の各々において、前記映像信号線と前記複数のトランジスタとを接続するリード線と、
前記複数の画素の各々において前記複数の画素電極と対向し、前記複数の画素にわたって設けられた共通電極と、
前記複数の画素電極の各々と前記共通電極との間に設けられた金属電極と、
前記第2方向に延在し、前記共通電極の直上に設けられたコモン線とを備え、
前記複数の画素電極と前記複数のトランジスタとは一対一で接続されており、
前記複数の画素の各々において、複数の前記画素電極及び複数の前記トランジスタの各々は、前記第1方向に並んでおり、
前記リード線は、前記映像信号線から前記第1方向に延在する共通リード線と、前記共通リード線と前記複数のトランジスタの各々のソース電極及びドレイン電極の一方とに接続された複数の第1個別リード線とを有し、
前記金属電極は、前記コモン線と同層に形成されている、
液晶表示パネル。 - 前記第1個別リード線の少なくとも一部は、平面視において、他の導電部材と重なっていない、
請求項1に記載の液晶表示パネル。 - 前記共通リード線は、平面視において、前記走査線と重なっていない、
請求項1又は2に記載の液晶表示パネル。 - 前記複数のトランジスタと前記複数の画素電極との間に設けられた絶縁層を備え、
前記絶縁層には、複数のコンタクトホールが形成され、
前記複数のトランジスタの各々と前記複数の画素電極の各々とは前記複数のコンタクトホールの各々を介して接続され、
前記複数のコンタクトホールの各々の近傍における前記絶縁層の上には、島状の積層膜が形成され、
前記積層膜は、前記共通電極と同層に形成された第1の膜と、前記第1の膜の上に積層され且つ前記コモン線と同層に形成された第2の膜とを有し、
前記第1個別リード線は、隣り合う2つの前記積層膜の間に設けられている、
請求項1~3のいずれか1項に記載の液晶表示パネル。 - 前記リード線及び前記走査線を覆う遮光層を備える、
請求項1~4のいずれか1項に記載の液晶表示パネル。 - 前記複数の画素の各々において、前記複数の画素電極の各々と前記複数のトランジスタの各々の前記ソース電極及び前記ドレイン電極の他方とを接続する複数の第2個別リード線を備える、
請求項1~5のいずれか1項に記載の液晶表示パネル。 - 前記第2個別リード線の少なくとも一部は、平面視において、他の導電部材と重なっていない、
請求項6に記載の液晶表示パネル。 - 前記複数の画素電極の各々の幅は、200μm以下である、
請求項1~7のいずれか1項に記載の液晶表示パネル。 - 前記画素電極の画素容量をCPIXとし、前記トランジスタのゲートソース間容量をCgsとしたときに、前記複数の画素の各々における前記複数の画素電極と前記複数のトランジスタの全てについて、画素容量比率を示すCPIX/Cgsが±10%以内である、
請求項1~8のいずれか1項に記載の液晶表示パネル。 - 一つの前記画素に含まれる前記複数の画素電極のうちの少なくとも一つは、当該画素内に含まれる他の画素電極とは形状が異なる、
請求項9に記載の液晶表示パネル。 - 前記複数の画素電極のうち隣り合う2つの前記画素電極を電気的に接続する接続電極を備える、
請求項1~10のいずれか1項に記載の液晶表示パネル。 - マトリクス状に配列された複数の画素を有する液晶表示パネルであって、
前記複数の画素の各々に複数ずつ設けられた画素電極及びトランジスタと、
第1方向に配列された前記複数の画素の各々における複数の前記トランジスタと接続された走査線とを備え、
前記複数の画素の各々において、複数の前記画素電極及び複数の前記トランジスタの各々は、前記第1方向に並んでおり、
前記複数の画素電極と前記複数のトランジスタとは一対一で接続されており、
前記複数の画素電極のうち隣り合う2つの前記画素電極を電気的に接続する接続電極を
備え、
前記接続電極は、平面視において、隣り合う2つの前記画素電極の各々の一部と重なり、かつ、前記画素電極に対向する共通電極と重なっていない、
液晶表示パネル。 - 前記共通電極には、平面視において前記接続電極と重なるように切り欠き部が形成されている、
請求項12に記載の液晶表示パネル。 - 前記接続電極は、前記トランジスタのソース電極及びドレイン電極と同層に形成される、
請求項12又は13に記載の液晶表示パネル。 - 前記金属電極は、前記共通電極の直上に位置し、且つ、前記画素電極と対向している、
請求項1~11のいずれか1項に記載の液晶表示パネル。 - 前記金属電極は、当該金属電極により前記画素電極と前記共通電極とを接続することで前記画素電極と前記共通電極とを短絡させる短絡用電極である、
請求項1~11、15のいずれか1項に記載の液晶表示パネル。 - 前記画素電極は、複数本のライン電極と、前記複数本のライン電極を連結する連結電極とを有し、
前記金属電極は、前記画素電極ごとに形成されており、且つ、前記連結電極と対向している、
請求項1~11、15、16のいずれか1項に記載の液晶表示パネル。
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