TWI548923B - 顯示面板及其畫素陣列 - Google Patents

顯示面板及其畫素陣列 Download PDF

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TWI548923B
TWI548923B TW104119373A TW104119373A TWI548923B TW I548923 B TWI548923 B TW I548923B TW 104119373 A TW104119373 A TW 104119373A TW 104119373 A TW104119373 A TW 104119373A TW I548923 B TWI548923 B TW I548923B
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黃玄驊
林建宏
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友達光電股份有限公司
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Priority to CN201510458519.9A priority patent/CN105068344B/zh
Priority to US15/047,650 priority patent/US9778526B2/en
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Description

顯示面板及其畫素陣列
本發明係關於一種顯示面板及其畫素陣列,尤指一種具有半源極驅動(half source driver, HSD)架構且資料線的連接部貫穿子畫素的顯示面板及其畫素陣列。
隨著液晶顯示技術不斷的提升,液晶顯示面板已廣泛地被應用在平面電視、筆記型電腦、智慧型手機與各類型的消費型電子產品上。習知液晶顯示器之驅動方式是利用源極驅動電路(source driver)與閘極驅動電路(gate driver)來驅動畫素以顯示影像。由於源極驅動電路的成本較閘極驅動電路高,為了降低源極驅動電路的使用量,衍生出具有半源極驅動(half source driver, HSD)架構的顯示面板,將源極驅動電路的資料線數目減半,而將閘極驅動電路的閘極線數目加倍,以減少生產成本。在習知具有半源極驅動架構之顯示面板的畫素陣列中,資料線需與對應之畫素的主動開關元件(active switching element)電性連接,因此影響兩相鄰畫素列的相鄰兩條閘極線之間的佈線空間,進而導致畫素的開口率偏低。
本發明之目的之一在於提供一種具有半源極驅動架構且資料線的連接部貫穿子畫素的顯示面板及其畫素陣列,以增加顯示面板的開口率。
為達上述目的,本發明提供一種畫素陣列,設置於一陣列基板上。畫素陣列包括複數個畫素列,各畫素列包括一第一閘極線、一第二閘極線、複數個子畫素以及複數條資料線。第一閘極線與第二閘極線係沿一第一方向依序排列。子畫素沿一第二方向設置於第一閘極線與第二閘極線之間,其中一部分之子畫素係與第一閘極線電性連接,且另一部分之子畫素係與第二閘極線電性連接。各資料線包括一主幹部、一分支部以及一連接部。資料線之主幹部係沿第二方向依序排列並與第一閘極線與第二閘極線相交。資料線之分支部係與主幹部沿第二方向交替排列,且各子畫素設置於任兩相鄰的主幹部與分支部之間。各資料線之連接部係設置於第一閘極線與第二閘極線之間並與主幹部與分支部電性連接,且各連接部沿第二方向貫穿對應之子畫素。
為達上述目的,本發明另提供一種顯示面板,其包括上述畫素陣列、對向基板以及顯示介質層。對向基板與陣列基板相對設置,以及顯示介質層設置於陣列基板與對向基板之間。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明,下文特列舉本發明之較佳實施例,並配合所附圖式,詳細說明本發明的構成內容及所欲達成之功效。
請一併參考第1圖與第2圖,第1圖繪示了本發明之第一實施例之畫素陣列之示意圖,第2圖繪示了本發明之第一實施例之畫素陣列之剖面示意圖,且第2圖是對應第1圖之顯示面板之畫素陣列之示意圖中A-A’線之剖面示意圖。如第1圖與第2圖所示,本實施例之畫素陣列102設置於陣列基板100上,畫素陣列102包括複數個畫素列104,且各畫素列104包括第一閘極線106、第二閘極線108、複數個子畫素110以及複數條資料線112。第一閘極線106與第二閘極線108係沿第一方向D1依序排列。子畫素110係沿第二方向D2設置於第一閘極線106與第二閘極線108之間,其中一部分之子畫素110係與第一閘極線106電性連接,且另一部分之子畫素110係與第二閘極線108電性連接。在本實施例中,第一方向D1例如為第1圖之縱向方向,第二方向D2為第1圖之橫向方向,但不以此為限。
各資料線112包括主幹部114、分支部116以及連接部118。資料線112之主幹部114係沿第二方向D2依序排列並與第一閘極線106與第二閘極線108相交。詳細而言,資料線112之主幹部114係在垂直投影方向Z上與第一閘極線106與第二閘極線108部分重疊。資料線112之分支部116係與主幹部114沿第二方向D2交替排列,且各子畫素110設置於任兩相鄰的主幹部114與分支部116之間。各資料線112之連接部118係設置於第一閘極線106與第二閘極線108之間並與主幹部114與分支部116電性連接,且各連接部118沿第二方向D2貫穿對應之子畫素110,藉此各資料線112之主幹部114、分支部116以及連接部118可組合成”H”字型結構,但不以此為限。在本實施例中,各畫素列104中的第一閘極線106、第二閘極線108與資料線112之連接部118可以是互相平行的,且各畫素列104中資料線112之主幹部114與分支部116可以是互相平行的,但不以此為限。另外,各畫素列104之資料線112之分支部116是設置於與其對應的畫素列104中的第一閘極線106與第二閘極線108之間。本實施例之畫素陣列102係選用具有半源極驅動架構的畫素陣列,因此部分子畫素係共用同一條資料線而可將資料線的數量減半。此外,在本實施例的畫素陣列102中,資料線112的連接部118貫穿子畫素110並與分支部116以及主幹部114電性連接。藉此,本實施例之畫素陣列102中資料線112的分支電極116不需佔用相鄰兩畫素列104之相鄰第一閘極線106與第二閘極線108之間的佈線空間即可與兩相鄰子畫素110的主動開關元件136電性連接,進而可有效縮短相鄰兩畫素列104之相鄰第一閘極線106與第二閘極線108之間的佈線空間,以提升顯示面板的開口率。值得一提的是,在畫素陣列102中子畫素110中間的區域是顯示面板中液晶效率較差的區域,因此本實施例之資料線112之連接部118可遮住液晶效率較差的區域,進而提升顯示面板的液晶效率。
此外,在本實施例之畫素陣列102中,各資料線112之主幹部114與各資料線112之分支部116係為ㄑ字型的電極,但不以此為限。在其他變化實施例中,各資料線112之主幹部114與分支部116可為沿相同方向(例如第一方向D1)延伸的直線型的電極。另值得一提的是,在本實施例中畫素列104可包括第一畫素列132與第二畫素列134,其中第一畫素列132之資料線112之連接部118係貫穿第一畫素列132之第偶數個子畫素110,以及第二畫素列134之資料線112之連接部118係貫穿第二畫素列134之第奇數個子畫素110,但不以此為限。在其他變化實施例中,第一畫素列132之資料線112之連接部118亦可係貫穿第一畫素列132之第奇數個子畫素110,以及第二畫素列134之資料線112之連接部118係貫穿第二畫素列134之第偶數個子畫素110。
在本實施例中,各子畫素110包括主動開關元件136與畫素電極138,主動開關元件136包括閘極140、汲極142與源極144,且畫素電極138係與對應之主動開關元件136之汲極142電性連接。此外,資料線112之分支部116係與在第二方向D2上與其相鄰的兩子畫素110的主動開關元件136之源極144電性連接。舉例而言,各資料線112之分支部116的一端可與相鄰的兩子畫素110之其中一者的主動開關元件136之源極144電性連接,而各資料線112之分支部116的另一端可與相鄰的兩子畫素110之其中另一者的主動開關元件136之源極144電性連接,但不以此為限。詳細而言,各畫素列104上之第6n-5個子畫素110的主動開關元件136之閘極140、第6n-2個子畫素110的主動開關元件136之閘極140與第6n個子畫素110的主動開關元件136之閘極140係與第一閘極線106電性連接,各畫素列104上之第6n-4個子畫素110的主動開關元件136之閘極140、第6n-3個子畫素110的主動開關元件136之閘極140與第6n-1個子畫素110的主動開關元件136之閘極140係與第二閘極線108電性連接,其中n為大於0之整數,但不以此為限。此外,子畫素110可包括用以提供不同顏色之子畫素,並藉由子畫素110所提供不同顏色的光進行混色以達到全彩顯示的效果。子畫素110例如可包括紅色子畫素、綠色子畫素與藍色子畫素,且紅色子畫素、綠色子畫素與藍色子畫素可為條狀(stripe)方式排列,但不以此為限。舉例而言,各畫素列104之第6n-5個與第6n-2個子畫素110可以為藍色子畫素、第6n-4個與第6n-1個子畫素110可以為紅色子畫素以及第6n-3個與第6n個子畫素110可以為綠色子畫素,藉此子畫素110所提供不同顏色的光可進行混色以達到全彩顯示的效果,但不以此為限。在其他變化實施例中,各畫素列104之第6n-5個與第6n-2個子畫素110可以為紅色子畫素、第6n-4個與第6n-1個子畫素110可以為綠色子畫素以及第6n-3個與第6n個子畫素110可以為藍色子畫素。另值得一提的是,本實施例之畫素陣列102可以行反轉(column inversion)的方式驅動,但不以此為限。
請繼續參考第2圖,在本實施例中主動開關元件136可為薄膜電晶體,例如非晶矽薄膜電晶體、氧化物半導體薄膜電晶體或其它材料之薄膜電晶體,且薄膜電晶體可選用頂閘極型薄膜電晶體、底閘極型薄膜電晶體或其它型式薄膜電晶體。本實施例係使用底閘極型的非晶矽薄膜電晶體作為主動開關元件136,其包括閘極140、汲極142、源極144、閘極絕緣層146、通道層148與保護層150。閘極140設置於陣列基板100上並與第一閘極線106或第二閘極線108電性連接。閘極絕緣層146設置於閘極140與陣列基板100上。通道層148可例如為非晶矽通道層設置於閘極絕緣層146上且於垂直投影方向Z上與閘極140重疊。通道層148的材料不以非晶矽為限,而可為其它適合的半導體,例如其它半導體層(例如多晶矽、微晶矽),氧化物半導體層例如氧化銦鎵鋅(IGZO)或其它適合的半導體材料。汲極142與源極144設置於通道層148與閘極絕緣層146上,且源極144與資料線112電性連接。保護層150設置於汲極142、源極144、通道層148以及閘極絕緣層146上,其中保護層150可為單層或雙層結構。在本實施例中,保護層150可為雙層結構,例如可為第一保護層152與第二保護層154依序堆疊,其中第一保護層152的材料可包括無機絕緣材料例如氧化矽、氮化矽或氮氧化矽,但不以此為限,且第二保護層154的材料可包括有機絕緣材料例如壓克力或環氧樹脂,但不以此為限。第二保護層154可設置於第一保護層152上,且第二保護層154的厚度較佳可大於第一保護層152的厚度,且第二保護層154的厚度較佳約為2微米(μm),但不以此為限。此外,本實施例之畫素陣列102另包括共通電極156、絕緣層158與畫素電極138。共通電極156係設置於保護層150上,畫素電極138係設置於共通電極156上,且絕緣層158係設置於共通電極156與畫素電極138之間,但不以此為限。本實施例之畫素陣列102具有厚度約2微米的保護層150,可有效降低資料線112與畫素電極138之間的寄生電容,使畫素電極138可在垂直投影方向Z上與資料線112重疊而不會受到寄生電容的影響,因此可有效提升顯示面板102的開口率。在本實施例中,第一閘極線106、第二閘極線108以及閘極140可由同一層圖案化金屬層所構成(例如第一金屬層),但不以此為限。資料線112、源極144以及汲極142可由同一層圖案化金屬層所構成(例如第二金屬層),但不以此為限。畫素電極138可為透明電極,例如氧化銦錫電極,但不以此為限。
本發明之畫素陣列並不以上述實施例為限。下文將依序介紹本發明之其它較佳實施例之畫素陣列,且為了便於比較各實施例之相異處並簡化說明,在下文之各實施例中使用相同的符號標注相同的元件,且主要針對各實施例之相異處進行說明,而不再對重覆部分進行贅述。
請參考第3圖,其繪示了本發明之第一實施例之一變化實施例之畫素陣列之示意圖。如第3圖所示,不同於第一實施例,在本變化實施例之畫素陣列102A中,各畫素列104上之第6n-5個子畫素110的主動開關元件136之閘極140、第6n-3個子畫素110的主動開關元件136之閘極140與第6n個子畫素110的主動開關元件136之閘極140係與第一閘極線106電性連接,各畫素列104上之第6n-4個子畫素110的主動開關元件136之閘極140、第6n-2個子畫素110的主動開關元件136之閘極140與第6n-1個子畫素110的主動開關元件136之閘極140係與第二閘極線108電性連接,其中n為大於0之整數,但不以此為限。本變化實施例之畫素陣列102A的其餘特徵可與前述實施例相同,並可參考第1圖與第2圖,在此不再贅述。
請參考第4圖與第5圖,第4圖繪示了本發明之第二實施例之畫素陣列之示意圖,第5圖繪示了本發明之第二實施例之畫素陣列之剖面示意圖,且第5圖是對應第4圖之畫素陣列之示意圖中B-B’線之剖面示意圖。本實施例與第一實施例不同的地方在於,各畫素列104另包括共通電極線160,其中共通電極線160係設置於第一閘極線106與第二閘極線108之間,共通電極線160係與資料線112之連接部118在垂直投影方向Z上至少部分重疊,且共通電極線160係與共通電極156電性連接。如第5圖所示,本實施例中之共通電極線160可設置於共通電極156與絕緣層158之間,但不以此為限。換言之,本實施例中之共通電極線160係以不同於資料線112、第一閘極線106以及第二閘極線108之圖案化金屬層所形成(例如第三金屬層),但不以此為限。在其他變化實施例中,共通電極線160也可與第一閘極線106以及第二閘極線108於同一圖案化金屬層所形成(例如第一金屬層)。此外,本實施例之共通電極線160在垂直投影方向Z上與資料線112之主幹部114、分支部116及連接部118至少部分重疊。由於共通電極線160與資料線112之連接部118於垂直投影方向Z上重疊的設計,除了不影響原本第一閘極線106與第二閘極線108之間的佈線空間,亦可有效地提升顯示面板的開口率。本實施例之畫素陣列202的其餘特徵可與第一實施例或第一變化實施例相同,並可參考第1圖至第3圖,在此不再贅述。
請參考第6圖與第7圖,第6圖繪示了本發明之第三實施例之畫素陣列之示意圖,第7圖繪示了本發明之第三實施例之畫素陣列之剖面示意圖,且第7圖是對應第6圖之顯示面板之畫素陣列之示意圖中C-C’線之剖面示意圖。本實施例與第一實施例不同的地方在於,畫素陣列302另包括複數條共通電極線160,其中各共通電極線160係設置於各畫素列104之第二閘極線108與相鄰之畫素列104之第一閘極線106之間,並以平行第一閘極線106或第二閘極線108的方向延伸。此外,共通電極線160係與共通電極156電性連接。如第7圖所示,本實施例中之共通電極線160可設置於共通電極156與絕緣層158之間,但不以此為限。換言之,本實施例中之共通電極線160係以不同於資料線112、第一閘極線106以及第二閘極線108之圖案化金屬層所形成(例如第三金屬層),但不以此為限。在其他變化實施例中,共通電極線160也可與資料線112於同一圖案化金屬層所形成(例如第二金屬層)。本實施例之畫素陣列302的其餘特徵可與第一實施例或第一變化實施例相同,並可參考第1圖至第3圖,在此不再贅述。
請參考第8圖,其繪示了本發明之一實施例之顯示面板之剖面示意圖。如第8圖所示,本實施例之顯示面板10包括陣列基板100、畫素陣列102、顯示介質層162以及對向基板164。對向基板164與陣列基板100相對設置,畫素陣列102設置於陣列基板100上,且顯示介質層162設置於陣列基板100與對向基板164之間。本實施例之畫素陣列102可為前述任一實施例所揭示的畫素陣列。陣列基板100與對向基板164可包括玻璃基板、塑膠基板或其他適合之硬式或可撓式基版,其中陣列基板100可另包括被動元件(例如電容、電阻等)、配向層或驅動控制電路設置於顯示介質層162與陣列基板100之間,對向基板164可包括彩色濾光片或黑色矩陣設置於顯示介質層162與對向基板164之間,但不以此為限。此外,顯示介質層162可例如為液晶層、電泳層(electrophoresis)或有機發光二極體(OLED)元件,但不以此為限。在本實施例中,顯示面板10為邊緣電場切換型(Fringe Field Switching)液晶顯示面板,但本發明不限於此。在其他變化實施例中,顯示面板亦可為平面內切換型(In-Plane Switching)液晶顯示面板、扭轉向列型(Twisted Nematic)液晶顯示面板、垂直向列型(Vertical Alignment)液晶顯示面板或光電補償型(electrical optical compensation)液晶顯示面板。
綜上所述,在本發明之顯示面板及其畫素陣列中,資料線具有主幹部、連接部與分支部,其中連接部貫穿對應之子畫素並與主幹部以及分支部電性連接,且資料線透過分支部與對應之畫素電性連接,可以避免習知具有半源極驅動架構的畫素陣列中,資料線之分支電極為了與對應之子畫素之主動開關元件電性連接而佔用兩相鄰畫素列的相鄰兩條閘極線之間的佈線空間。因此,本發明之顯示面板及其畫素陣列可有效地縮減兩相鄰畫素列的相鄰兩條閘極線之間的佈線空間,進而有效地提升顯示面板的開口率。再者,在本發明之顯示面板及其畫素陣列中,資料線之連接部亦可有效地擋住液晶效率較差的區域,以提升顯示面板的液晶效率。   以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100‧‧‧陣列基板
102、102A、202、302‧‧‧畫素陣列
104‧‧‧畫素列
106‧‧‧第一閘極線
108‧‧‧第二閘極線
110‧‧‧子畫素
112‧‧‧資料線
D1‧‧‧第一方向
D2‧‧‧第二方向
114‧‧‧主幹部
116‧‧‧分支部
118‧‧‧連接部
132‧‧‧第一畫素列
134‧‧‧第二畫素列
136‧‧‧主動開關元件
138‧‧‧畫素電極
140‧‧‧閘極
142‧‧‧汲極
144‧‧‧源極
146‧‧‧閘極絕緣層
148‧‧‧通道層
150‧‧‧保護層
152‧‧‧第一保護層
154‧‧‧第二保護層
156‧‧‧共通電極
158‧‧‧絕緣層
160‧‧‧共通電極線
10‧‧‧顯示面板
162‧‧‧顯示介質層
164‧‧‧對向基板
Z‧‧‧垂直投影方向
第1圖繪示了本發明之第一實施例之畫素陣列之示意圖。 第2圖繪示了本發明之第一實施例之畫素陣列之示意圖中沿A-A’線之剖面示意圖。 第3圖繪示了本發明之第一實施例之一變化實施例之畫素陣列之示意圖。 第4圖繪示了本發明之第二實施例之畫素陣列之示意圖。 第5圖繪示了本發明之第二實施例之畫素陣列之示意圖中沿B-B’線之剖面示意圖。 第6圖繪示了本發明之第三實施例之畫素陣列之示意圖。 第7圖繪示了本發明之第三實施例之畫素陣列之示意圖中沿C-C’線之剖面示意圖。 第8圖繪示了本發明之一實施例之顯示面板之剖面示意圖。
102‧‧‧畫素陣列
104‧‧‧畫素列
106‧‧‧第一閘極線
108‧‧‧第二閘極線
110‧‧‧子畫素
112‧‧‧資料線
D1‧‧‧第一方向
D2‧‧‧第二方向
114‧‧‧主幹部
116‧‧‧分支部
118‧‧‧連接部
132‧‧‧第一畫素列
134‧‧‧第二畫素列
136‧‧‧主動開關元件
138‧‧‧畫素電極
Z‧‧‧垂直投影方向

Claims (11)

  1. 一種畫素陣列,設置於一陣列基板上,該畫素陣列包括: 複數個畫素列,各該畫素列包括: 一第一閘極線; 一第二閘極線,該第一閘極線與該第二閘極線係沿一第一方向依序排列; 複數個子畫素,沿一第二方向設置於該第一閘極線與該第二閘極線之間,其中一部分之該等子畫素係與該第一閘極線電性連接,且另一部分之該等子畫素係與該第二閘極線電性連接;以及 複數條資料線,各該資料線包括一主幹部、一分支部以及一連接部,其中: 該等資料線之該等主幹部係沿該第二方向依序排列並與該第一閘極線與該第二閘極線相交; 該等資料線之該等分支部係與該等主幹部沿該第二方向交替排列,且各該子畫素設置於任兩相鄰的該主幹部與該分支部之間;以及 各該資料線之該連接部係設置於該第一閘極線與該第二閘極線之間並與該主幹部與該分支部電性連接,且各該連接部沿該第二方向貫穿對應之該子畫素。
  2. 如請求項1所述之畫素陣列,其中該等畫素列包括一第一畫素列與一第二畫素列,該等資料線之該等連接部係貫穿該第一畫素列之第偶數個子畫素,以及該等資料線之該等連接部係貫穿該第二畫素列之第奇數個子畫素。
  3. 如請求項1所述之畫素陣列,其中各該子畫素包括一主動開關元件與一畫素電極,該主動開關元件包括一閘極、一汲極與一源極,且該畫素電極係與對應之該主動開關元件之該汲極電性連接。
  4. 如請求項3所述之畫素陣列,其中各該畫素列上之第6n-5個子畫素的該主動開關元件之該閘極、第6n-2個子畫素的該主動開關元件之該閘極與第6n個子畫素的該主動開關元件之該閘極係與該第一閘極線電性連接,各該畫素列上之第6n-4個子畫素的該主動開關元件之該閘極、第6n-3個子畫素的該主動開關元件之該閘極與第6n-1個子畫素的該主動開關元件之該閘極係與該第二閘極線電性連接,其中n為大於0之整數。
  5. 如請求項4所述之畫素陣列,其中該分支部係與在該第二方向上與其相鄰的兩該等子畫素的該等主動開關元件之該等源極電性連接。
  6. 如請求項1所述之畫素陣列,另包括一保護層、一絕緣層與一共通電極,設置於該陣列基板上,其中該共通電極係設置於該保護層上,該等畫素電極係設置於該共通電極上,且該絕緣層係設置於該共通電極與該等畫素電極之間。
  7. 如請求項6所述之畫素陣列,其中各該畫素列另包括一共通電極線,設置於該第一閘極線與該第二閘極線之間,該共通電極線係與該等資料線之該等連接部在一垂直投影方向上至少部分重疊,且該共通電極線係與該共通電極電性連接。
  8. 如請求項7所述之畫素陣列,其中該共通電極線係設置於該絕緣層與該共通電極之間。
  9. 如請求項6所述之畫素陣列,另包括複數條共通電極線,其中各該共通電極線係設置於各該畫素列之該第二閘極線與相鄰之該畫素列之該第一閘極線之間,且該等共通電極線係與該共通電極電性連接。
  10. 如請求項9所述之畫素陣列,其中該等共通電極線係設置於該絕緣層與該共通電極之間。
  11. 一種顯示面板,包括: 如請求項1所述之該畫素陣列; 一對向基板,與該陣列基板相對設置;以及 一顯示介質層,設置於該陣列基板與該對向基板之間。
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