JP6974685B2 - 応力による影響を受け易いmemsをパッケージングするための構造及び方法 - Google Patents
応力による影響を受け易いmemsをパッケージングするための構造及び方法 Download PDFInfo
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Description
Claims (20)
- 集積マイクロエレクトロメカニカルシステム(MEMS)デバイスをパッケージングするための方法であって、
基板のアッセンブリパッド上に半導体チップを取り付けることであって、前記基板がリードを含み、前記半導体チップが、第1及び第2の端子と、ポリイミドのリング構造を有する表面とを含む、前記半導体チップを取り付けることと、
第1のシリコーン材料の層を用いて前記リング構造の内部の前記表面の領域上に前記MEMSデバイスを取り付けることと、
前記MEMSデバイスの端子から前記第1の端子にボンディングワイヤを架けることと、
前記MEMSデバイスと前記ボンディングワイヤとの上に第2のシリコーン材料の層をディスペンスすることによってグロブ(glob)を形成して、前記グロブの表面を前記リング構造の内部の前記表面の一部に制限することと、
前記グロブを硬化させることと、
前記グロブの表面上に第3のシリコーン材料の層をディスペンスすることと、
前記グロブにより埋め込まれる前記MEMSデバイスと前記半導体チップと前記基板の一部とを重合体モールディング化合物によって封止することと、
を含み、
前記第1及び第2のシリコーン材料の層が同じ低弾性シリコーンであり、前記MEMSデバイスが前記低弾性シリコーンによって囲まれる、方法。 - 請求項1の方法であって、
前記第1、第2及び第3のシリコーン材料の層が10MPaより小さい弾性を有する低弾性シリコーンである、方法。 - 請求項1の方法であって、
前記第2のシリコーン材料の層が、疎水性であり、エポキシベースのモールディング化合物に対して非接着性である、方法。 - 請求項1の方法であって、
前記グロブを形成する前に、前記第2の端子を前記基板のリードにワイヤボンディングすることと、
前記第3のシリコーン材料の層をディスペンスすることの後に、前記第3のシリコーン材料の層を硬化することと、
前記グロブを硬化することの後で前記第3のシリコーン材料の層をディスペンスすることの前に、前記半導体チップと前記基板と前記グロブとの一部をプラズマエッチングすることと、
を更に含む、方法。 - 請求項1の方法であって、
前記基板が前記アッセンブリパッドとリードとを有するリードフレームである、方法。 - 請求項5の方法であって、
前記リードフレームがクワッドフラットノーリード(QFN)リードフレームである、方法。 - 請求項4の方法であって、
前記重合体モールディング化合物が、無機充填材粒子を含むエポキシベースの熱硬化性モールディング配合物である、方法。 - 請求項1の方法であって、
前記半導体チップを取り付けることが、エポキシベースの重合体化合物を用いる、方法。 - 請求項1の方法であって、
前記半導体チップを取り付けることの前に、
複数の半導体チップを含むシリコンウェハの表面の上にポリイミド材料の層を被覆することと、
前記複数の半導体チップの各々の上の前記リング構造を形成するために、フォトレジスト層をスピンオンし、前記フォトレジスト層をマスキングし、露光し、現像することを含むフォトリソグラフィ法を用いて、前記ポリイミド材料の層をパターニングすることと、
前記ポリイミド材料に、第1の時間硬化することと、アッシングすることと、第2の時間硬化することとを連続的に受けさせることと、
前記シリコンウェハから前記複数の半導体チップを個片化することと、
を更に含む、方法。 - 請求項9に記載の方法であって、
前記アッシングすることが、酸素プラズマを含む、方法。 - 集積マイクロエレクトロメカニカルシステム(MEMS)デバイスをパッケージングするための方法であって、
第1及び第2の端子と、ポリイミドのリング構造を有する表面とを含む半導体チップをリードを含む基板のアッセンブリパッド上に取り付けることと、
第1のシリコーン材料の層を用いて前記リング構造の内部の領域上に前記MEMSデバイスを取り付けることと、
前記MEMSデバイスの端子から前記第1の端子にボンディングワイヤを架けることと、
前記MEMSデバイスと前記ボンディングワイヤとの上に第2のシリコーン材料の層をディスペンスすることによりグロブを形成して、前記グロブを前記リング構造の内部の前記領域に制限することと、
前記グロブを硬化させることと、
前記グロブの表面上にエポキシ化合物の層をディスペンスすることと、
前記エポキシ化合物の層を硬化させることと、
前記グロブにより埋め込まれる前記MEMSデバイスと、前記半導体チップと、前記基板の一部とを重合体モールディング化合物内に覆うことと、
を含み、
前記第1及び第2のシリコーンの材料の層が同じ低弾性シリコーン材料であり、前記MEMSデバイスが前記低弾性シリコーン材料により囲まれる、方法。 - 請求項11の方法であって、
前記第1及び第2のシリコーン材料の層が10MPa未満の弾性を有する低弾性シリコーン材料である、方法。 - 請求項11の方法であって、
前記グロブを形成することの前に、前記半導体チップの第2の端子を前記基板のコンタクトパッドにワイヤボンディングすることと、
前記グロブを硬化させることの後で前記エポキシ化合物の層をディスペンスすることの前に、前記半導体チップと前記基板と前記グロブとの一部をプラズマエッチングすることと、
を更に含む、方法。 - 請求項11の方法であって、
前記半導体チップを取り付けることの前に、
複数の半導体チップを含むシリコンウェハの表面の上にポリイミド材料の層を被覆することと、
前記複数の半導体チップの各々の上に前記リング構造を形成するために、フォトレジスト層をスピンオンし、前記フォトレジスト層をマスキングし、露光し、現像することを含むフォトリソグラフィ法を用いて、前記ポリイミド材料の層をパターニングすることと、
前記ポリイミド材料の層に、第1の時間硬化することと、アッシングすることと、第2の時間硬化することとを連続的に受けさせることと、
前記シリコンウェハから前記複数の半導体チップを個片化することと、
を更に含む、方法。 - パッケージングされたマイクロエレクトロメカニカルシステム(MEMS)デバイスであって、
パッドとリードとを含む基板と、
第1及び第2の端子を備える回路要素を含む半導体チップであって、前記第2の端子が前記リードにワイヤボンディングされる、前記半導体チップと、
シリコーン化合物の層により前記半導体チップの表面に取り付けられるMEMSデバイスであって、前記MEMSデバイスの端子が、前記第1の端子へのワイヤ懸架によりボンディングされる、前記MEMSデバイスと、
前記MEMSデバイスと前記第1の端子とを囲む前記半導体チップの表面上のポリイミド化合物のリング構造と、
前記MEMSデバイスと前記ワイヤ懸架とを覆うシリコーン材料のグロブであって、前記半導体チップの前記リング構造の内部の表面領域に制限される、前記グロブと、
前記グロブと前記半導体チップと前記基板との一部を覆うモールディング化合物であって、前記グロブに対して非接着性である、前記モールディング化合物と、
を含み、
前記シリコーン化合物の層と前記シリコーン材料のグロブとが同じ低弾性シリコーンであり、前記MEMSデバイスが前記低弾性シリコーンにより囲まれる、MEMSデバイス。 - 請求項15のMEMSデバイスであって、
前記MEMSデバイスが、機械的及び熱的応力に影響を受け易い、MEMSデバイス。 - 請求項15のMEMSデバイスであって、
前記シリコーン化合物の層と前記シリコーン材料とが10MPa未満の弾性を有する低弾性シリコーン化合物である、MEMSデバイス。 - 請求項15のMEMSデバイスであって、
前記モールディング化合物がエポキシベースの熱硬化性モールディング化合物である、MEMSデバイス。 - 請求項15のMEMSデバイスであって、
前記リング構造の前記表面領域が、前記ポリイミド化合物の第1の硬化とアッシングと第2の硬化とのプロセスシーケンスから生じる、MEMSデバイス。 - 請求項15のMEMSデバイスであって、
前記リング構造が、円と矩形との一方の形状を有する、MEMSデバイス。
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