CN109075129B - 浮动裸片封装 - Google Patents

浮动裸片封装 Download PDF

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Publication number
CN109075129B
CN109075129B CN201780028211.8A CN201780028211A CN109075129B CN 109075129 B CN109075129 B CN 109075129B CN 201780028211 A CN201780028211 A CN 201780028211A CN 109075129 B CN109075129 B CN 109075129B
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die
semiconductor
substrate
semiconductor die
sublimable
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CN109075129A (zh
Inventor
本杰明·史塔生·库克
史蒂文·库默尔
库尔特·彼得·瓦赫特勒
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

所描述实例包含一种浮动裸片封装(200B‑1)，其包含通过在模制(216)组合件之后牺牲裸片密封剂的升华和裸片附接材料的升华或分离形成的空腔(252)。将模制结构中的针孔通风口(218)提供为升华路径以允许气体逸出，其中所述裸片(206)或裸片堆叠从衬底(202)释放且仅通过接合线(210)悬浮于所述空腔(252)中。

Description

浮动裸片封装
技术领域
本发明大体上涉及半导体装置和其制造方法，且更具体地说，涉及一种裸片封装和相关联的制造工艺。
背景技术
半导体封装为含有一或多个半导体裸片或组件的金属、塑料、玻璃或陶瓷壳体。封装在操作和执行例如半导体集成电路(IC)或裸片的组件时发挥基本作用。除提供将信号和电源线引入硅裸片中和硅裸片之外的方式以外，封装还去除由电路产生的热且提供机械支撑。最后，封装还保护裸片免受例如湿度的环境条件影响。此外，封装技术继续对例如微处理器、信号处理器等等高性能组件的执行和功率耗散具有重大影响。随着时间的推移，通过内部信号延迟和芯片上电容由于技术缩放的减小，此影响变得更为明显。
高精度IC现今被装配后封装应力影响，从而引起参数位移和电位漂移过温。例如，电特性(例如，晶体管的阈值电压、IC的高精度参考电压等等)可归因于由封装材料引起的热-机械应力而发生漂移。然而，到目前为止的常规解决方案通常依赖于采用具有低模量的弹性的材料，其仍然具有高热膨胀系数(coefficient of thermal expansion，CTE)。因此，尽管可改进应力抗扰性，但以此类技术封装的IC装置仍然展示参数应力和温度漂移。
包含有源和无源组件的半导体装置、接合技术和封装工艺可得益于相对于实现高性能、高可靠性和减小的制造成本的改进。
发明内容
在制造半导体裸片封装的实例方法中，所述方法可尤其包括裸片制备，其可涉及使来自半导体晶片的一或多个半导体裸片单体化，每个半导体裸片具有多个接合垫。将单体化的半导体裸片附接到具有多个电导体或导电指形件的衬底，其中所述附接包括所选裸片附接材料的合适的涂覆。在一个实施方案中，所选裸片附接材料可包括可升华物质。可以一或多个阶段固化裸片附接材料，继而使用对应数目的接合线将至少一个单体化的半导体裸片的接合垫线接合到衬底的所述多个电导体。涂覆所选可升华牺牲密封材料以使得团块或凸块结构覆盖单体化裸片的至少一部分和衬底中包含接合线的至少一部分。可升华牺牲裸片密封材料的凸块结构也可以一或多个阶段固化。涂覆所选模制材料以覆盖、包覆或以其它方式密封凸块结构和衬底，其中在模制材料中形成具有所选形状和大小的至少一针孔通风口以便在后一阶段为可升华牺牲密封材料提供升华路径。在一个实例实施方案中，可以一或多个阶段固化模制材料，优选地在此步骤处不会引起可升华材料的升华。接着实现升华过程以使可升华牺牲密封材料气化，由此允许气化的密封材料通过模制的针孔通风口逸出，由此形成空腔。在其它变化形式中，取决于实施方案，裸片附接材料还可升华、分层或保持完好。接着使用膜层覆盖或密封包含针孔通风口的模制结构以完成含有安置在空腔中的至少一个单体化裸片的半导体裸片封装的制造。
在实例半导体裸片封装中，所述封装尤其包括具有多个电导体的衬底和具有多个接合垫的至少一个半导体裸片，其使用对应数目的接合线线接合到衬底的所述多个电导体。提供覆盖或以其它方式密封半导体裸片的至少一部分、衬底和其间的接合线的模制结构，其中所述模制结构含有通过以下操作形成的空腔或腔室：(i)在模制之前将牺牲密封材料沉积在至少一个半导体裸片上方；且(ii)通过模制结构的针孔通风口使牺牲密封材料升华，且另外其中所述空腔提供安置有至少一个半导体裸片的空间，由于沉积在至少一个半导体裸片与衬底之间的裸片附接材料的升华或收缩/分层而浮于衬底上方。膜层安置在所述模制结构上方或上，气密密封形成于所述模制结构中的所述针孔通风口以用于提供升华路径。
附图说明
图1A和1B说明根据实例实施例的实例裸片封装工艺以作为后端半导体制造流程的部分。
图2A-1和2A-2说明根据一或多个实例实施例的由图1A的工艺流程的实施产生的实例过渡封装结构。
图2B-1到2B-3说明根据一或多个实例实施例的由图1B的工艺流程的实施产生的实例成品封装结构。
图2C说明出于实例实施例的目的操作为衬底的与引线框架结构联合的实例半导体裸片。
图3说明根据另一实例实施例的具有堆叠裸片配置的实例封装结构。
具体实施方式
在此描述中，对“一”实施例或“一个”实施例的参考未必是参考同一实施例，且此类参考可意指至少一个。另外，在结合实施例描述特定特征、结构或特性时，可结合其它实施例实现此特征、结构或特性，无论是否明确描述。
在图式中，相同的附图标记通篇一般用于指相同的元件。图式未按比例绘制。可在不具有特定细节中的一或多个或在具有其它方法的情况下实践实例实施例。实例实施例不受动作或事件的说明次序限制。一些动作可以不同次序发生和/或与其它动作或事件同时发生。此外，实施根据实例实施例的方法不需要所有所说明的动作或事件。
在此描述中，可参考图式的定向或其说明性元件使用某些方向性术语(例如“上部”、“下部”、“顶部”、“底部”、“左侧”、“右侧”、“前侧”、“背侧”、“竖直”、“水平”等等)。但实施例的组件可定位在多个不同定向上，因此方向性术语出于说明目的使用且不具限制性。在不脱离实例实施例的范围的情况下，可使用另外的实施例，且可进行结构或逻辑变化。除非特定地描述。否则本文中所描述的各种实例实施例的特征可彼此组合。
如在此描述中所使用，术语“耦合”、“电耦合”、“连接”或“电连接”并不需要元件必须直接耦合或连接在一起。中介元件可提供于“耦合”、“电耦合”、“连接”或“电连接”的元件之间。
大体上，实例实施例涉及浮动裸片封装和其制造。所述封装包含通过牺牲裸片密封剂的升华形成的空腔。并且，在一变化形式中，可在模制组合件之后实现裸片附接材料的升华和/或分层。可将模制结构中的一或多个针孔通风口或孔隙提供为升华路径以允许气体逸出，其中裸片或裸片堆叠从衬底释放且仅通过接合线悬浮于空腔中。
下文中所描述的实例半导体装置可包含或由例如Si、SiC、SiGe、GaAs或有机半导体材料的半导体材料形成。半导体材料可实现为含有任何类型的IC的半导体晶片或半导体芯片，例如数字、模拟、混合信号或功率型半导体芯片。实例半导体芯片或裸片可包含集成电路、控制集成电路的控制电路、一或多个存储器/处理器核心和相关联外围电路，和/或微机电组件或系统(MEMS)。半导体芯片可以进一步包含并非半导体的无机和/或有机材料(例如绝缘体，例如电介质层、塑料或金属等)。
可根据实例实施例封装的半导体装置的实例可包含多个接合垫(也被称作接触垫或接合垫)，其可由金属制成或包含金属，例如铜(Cu)、铝(Al)等等，且可进一步包括扩散阻挡层的一或多个层。例如，可涂覆多层级/层Cu扩散阻挡金属，例如包括镍钯(Ni-Pd)、氮化钽(TaN)-Ni-Pd等等。接触垫可被配置成在半导体装置的集成电路与连接到衬底的相应连接元件之间提供电连接。与接合垫建立接触的可能性可包含焊接、线接合、夹片接合、倒装芯片安装和探针等等。在一些实例实施例中，连接元件可因此实现为接线或接合夹片。
在下文中所描述的实例封装工艺中，可接合到接触垫的实例接线(或接合线)可包含线芯，其可包含金属或金属合金，例如铜或铜合金；且可以进一步包含布置在线芯上方的涂布材料。例如，实施例可包含包括涂布钯的材料(例如，涂布Pd的铜或PCC)等等中的一个的涂布材料。取决于应用，线径可以具有范围介于小于一微米到数百微米的厚度。在实例实施例中，取决于特定应用，线径可在15到250微米(μm)之间。线芯可具有大体上圆形的横截面，使得术语线芯的“厚度”可指代线芯的直径。
可根据实例实施例封装的实例半导体装置、裸片或裸片堆叠可包括接触垫，其已经使用多种表面处理工艺形成，例如包含湿式清洁、化学清洁、干式或等离子体清洁等等。
接线或材料(其可接合到实例实施例的接触垫)可包含钝化层，例如氧化物层。与此相关，术语“钝化”可指代避免或抑制被钝化层包覆或布置在钝化层下方的材料的氧化和腐蚀。例如，可经由硬质非反应性表面膜的自发形成(自发钝化)产生钝化层。在一些实例实施例中，所述钝化层可以具有1与10nm之间，例如4与8nm之间的厚度。
图1A和1B描绘根据实例实施例的实例裸片封装工艺100A、100B以作为后端半导体制造流程的部分。图1A中的附图标记100A大体上指代所述流程的第一部分，可取决于所涉及半导体装置的类型、制造技术和后端铸造流程而涉及裸片制备的各个阶段。作为单体化来自晶片的个别半导体裸片或芯片(即，“切割”)以供封装的部分，可执行涉及晶片分类、视觉/自动检测、衬带安装、晶片锯切以及去离子(DI)水清洁和润滑等等的多种工艺。另外，对于某些类型的半导体装置，还可在切割之前(另外或任选地)执行晶片背部研磨操作，以便从背侧去除足够的晶片衬底材料且由此获得在不同范围(例如，从约50微米到数百微米)内的所选薄度或厚度。并且，取决于制造工艺，一或多个合适的背侧金属层(例如，包括钛(Ti)、钛-镍-银(Ti-Ni-Ag)、镍-钒(Ni-V)等等)还可沉积在晶片的背侧衬底上方。这些制备步骤一起在框102处说明。
在裸片制备之后，可执行多个裸片附接相关步骤，其取决于所涉及半导体装置的类型、封装技术和后端铸造流程同样可涉及一或多个工艺阶段、一或多个单体化半导体裸片等等。根据实例实施例，第一半导体裸片(其还可被称作底部裸片或至少一个单体化的半导体裸片，取决于多裸片或多芯片配置是否经封装)可根据实例实施例使用所选裸片附接材料安装或以其它方式附接到具有多个电导体的衬底，例如引线框架座或裸片垫和相关联的导电指形件，如在框104处所阐述。在一个实施例中，裸片附接材料可包括相对于后端/封装处理的工艺参数的范围为非可升华或保持非可升华的材料、物质或化合物。在另一实施例中，裸片附接材料可包括在一或多个下游工艺步骤中或期间，可部分或完全地从半导体裸片或从衬底收缩(shrink)、分层、皱缩、收缩(contract)、回缩或以其它方式脱离的材料、物质或化合物。在另一实施例中，裸片附接材料可包括可在一或多个下游工艺步骤中升华的材料、物质或化合物。在此变化形式中，此类裸片附接材料可优选地在与实例封装流程参数相关的合适的温度范围下发生升华。并且，整个裸片附接材料可升华(例如，全部升华)或所述材料的至少一部分可升华(例如，部分升华)。下文中结合涉及升华的后续处理步骤中的一些描述实例可升华材料(其可出于实例实施例的目的使用)。
取决于技术和后端铸造流程，实例工艺流程100A可涉及优选地以一或多个阶段对裸片附接材料(和实施堆叠裸片配置的裸片间附接材料)进行固化/衬底(框106)，这可被称为安装固化工艺。在实例封装流程每个封装涉及多个裸片的情况下，额外裸片可在一个说明性实施方案中使用常规非可升华裸片间附接材料附接到一起(例如，呈竖直堆叠配置，在底部裸片顶部上)，其中可提供可升华底部填充物以将底部裸片附接到衬底。在此类堆叠裸片布置中，底部裸片可首先经附接和固化，继而使用非可升华裸片间附接材料将下一裸片附接在底部裸片顶部上且此后使其固化等等。因此，在一个实施例中，呈堆叠方式的每个裸片可分开且依序附接和固化直到所述堆叠中的顶部裸片经附接和固化为止。实例堆叠裸片配置可包含不同类型的半导体装置，其中每个裸片的固化工艺可涉及多个阶段，例如包括不同温度和时间范围，所述阶段可不同于所述堆叠中的其它裸片的那些阶段。
在一个实例实施方案中，底部裸片附接材料可提供为导电底部填充物，而裸片间附接材料可为非导电的。并且，可使用各种技术，例如使用注射器分配机构涂覆裸片附接材料。
在另一实例实施方案中，第一安装固化工艺可包括最小170℃到最大180℃的第一阶段温度范围，优选温度为175℃，所述第一阶段可进行25到35分钟的第一持续时间，优选时间为30分钟。同样，第一安装固化工艺的第二阶段可具有170℃到180℃的温度范围，持续55到65分钟的时间范围。第一安装固化工艺的第三和最终阶段可具有70℃到80℃的温度范围，持续40到50分钟的时间范围。在又另一实例实施方案中，第二安装固化工艺还可包括具有以下工艺参数的三个阶段：持续25到35分钟的时间范围的具有145℃到155℃的温度范围的第一阶段、持续60到65分钟的时间范围的具有145℃到155℃的温度范围的第二阶段和持续45到55分钟的时间范围的具有75℃到85℃的温度范围的第三阶段。
样本裸片间附接材料和/或非可升华裸片附接材料可包括但不限于各种已知或此前未知的环氧树脂材料、氰酸酯共混材料、软焊剂材料和共晶接合材料，可基于单个裸片或堆叠裸片配置和相关联的封装技术所需的特定热-机械性质而选择所述材料。
继续参考图1A，至少一个单体化的半导体裸片的裸片接合垫可使用对应数目的接合线结合不同接合技术线接合到衬底的所述多个电导体(例如，引线框架的导电指形件)(框108)。在涉及多个裸片的情况下，每个裸片可分开线接合到对应的一组导电指形件、凸块、球状物或支柱等等。另外，包括例如球状物接合、楔状物接合、带状物接合、夹片接合和胶带自动接合(tape-automated bonding，TAB)的各种线接合互连工艺可用于将各种冶金，例如金(Au)、铝(Al)或铜(Cu)等等的接合线连接到衬底的导电指形件。一般来说，在每种类型的接合中，可使用热、压力和超声波能量的某一组合将所述线附接在两端(即，接合垫和对应导电指形件)处以进行焊接。
图2C展示实例衬底200C，提供为具有裸片或芯片座274和多个导电指形件276A的引线框架结构272。将包含被多个接合垫280环绕的一或多个有源电路区域282的半导体裸片278安装在引线框架的芯片座274上。各自具有约15微米到25微米的实例线径的接合线276B说明性地展示为对应地在接合垫280与导电指形件276A之间提供线连接。
再次参考图1A，根据实例实施例涂覆所选可升华牺牲密封材料作为具有合适的形状和/或大小的凸块结构以覆盖单体化裸片(或呈堆叠裸片配置的多个裸片)的至少一部分和衬底中包含接合线的至少一部分(框110)。在一个实施例中，密封材料可完全密封裸片，连同接合线的各部分和/或衬底。在另一变化形式中，密封材料可仅覆盖裸片的部分区域、接合线的子组/部分和/或衬底(例如，在裸片/衬底的所选区域处)。这些密封变化形式说明性地展示在框110处。
材料(例如各种类型的多元醇)可有利地用作牺牲密封材料和/或可升华裸片附接材料，其可在线接合工艺窗和模制工艺窗(下文中所描述)外部的温度下发生升华或收缩/分层，以便在封装内形成空腔(部分或完整空腔，取决于实施方案)，其中半导体裸片(或裸片堆叠)可仅通过接合线而悬浮，由此实现可被称为“浮动裸片”的裸片，可缓解和/或克服通常在常规封装技术中引起不希望的参数位移的封装后热-机械应力。取决于多元醇的物理/化学性质和适用的工艺温度窗，所选可升华材料可涂覆为固体，其可在某些温度下挤压为熔融珠粒以沉积在裸片/衬底/接合线的所选部分上方。在另一变化形式中，可升华材料可溶解于合适的溶剂中且使用将珠粒分配在裸片部分和周围衬底与接合线部分(下文称为“密封组件”)上方的注射器分配机构涂覆为具有适合粘度的溶液。溶剂可从珠粒蒸发，由此使得材料的“团块”在裸片和密封组件上方作为凸块结构。在又一变化形式中，所选可升华材料在室温下可涂覆为液体，接着其可通过形成化学键的交联的辐射(例如，UV、IR等等)固化以固化为凸块。
多元醇为具有多个羟基官能团的化合物，其可提供为单体或聚合性物质。具有两个羟基的分子为二醇，具有三个羟基的分子为三醇，依此类推。实例可升华牺牲密封材料和可升华裸片附接材料可选自但不限于由以下中的至少一个组成的多元醇的群组：新戊二醇、三羟甲基乙烷和2,5-二甲基-2,5己二醇，其性质在下文中阐述。
表A
类似于如在框106处所阐述的固化裸片附接材料，也可取决于实施方案以一或多个阶段固化/烘烤牺牲裸片密封材料(其可被称为“团块顶部”固化工艺)，如在框112处所阐述。在一个实例实施例中，团块顶部固化工艺的第一阶段可包括最小145℃到最大155℃的第一阶段温度范围，优选温度为150℃，所述第一阶段可进行25到35分钟的第一持续时间，优选时间为30分钟。同样，团块顶部固化工艺的第二阶段可具有145℃到155℃的温度范围，持续55到65分钟的时间范围，且团块顶部安装固化工艺的第三和最终阶段可具有75℃到80℃的温度范围，持续40到50分钟的时间范围。
在框114处，可涂覆所选模制材料以覆盖凸块结构(其密封单体化半导体裸片或呈堆叠方式的多个裸片的至少一部分)和衬底的至少一部分，其中在模制材料中形成具有所选形状和大小的至少一针孔通风口、孔隙、开口或孔口等等以便在后一阶段为可升华牺牲密封材料(和裸片附接材料，如果可升华的话)提供升华路径。在实例实施方案中，模制材料可选自塑料、环氧树脂等等，其可经调配以含有各种类型的无机填充剂，例如熔融硅石、催化剂、阻燃剂、应力修正剂、粘合促进剂和其它添加剂，优选地基于特定产品/部分要求，但还可使用其它类型的模制/封装材料。在一个实例实施方案中，所选模制材料可通过具有针状物的封装工具涂覆，使所述封装工具与密封凸块结构接触，围绕所述针状物将所选模制材料沉积在所述密封凸块结构上，由此在所选模制材料中形成针孔通风口或开口，装配后操作为气体升华的逸出路径或排气路径。通常，可将强烈的热施加到模制材料，其可液化和塑形为所要形式。并且，可在模塑固化工艺中以一或多个阶段固化具有针孔通风口的所选模制材料(框116)。在一个实施方案中，实例模塑固化工艺可涉及170℃到180℃的温度范围，持续4到5小时的时间范围。
图2A-1展示根据实例实施例的由上文描述的图1A的工艺流程的实施产生的实例过渡封装结构200A-1。使用裸片附接材料层208将实例半导体裸片206安装到包括座202的衬底结构，所述裸片附接材料层在一个实施例中可包括如上文所描述的可升华物质。接合线210连接于裸片接合垫212与相应的多个导体204A/204B之间。凸块结构214由如先前章节中所描述的合适的牺牲密封材料形成，从而覆盖整个半导体裸片206和衬底202中至少上面附接有裸片206的部分。模制结构216覆盖凸块结构214和包含导体204A/204B的衬底结构，其中至少一个针孔通风口218形成于凸块结构214上方，由此为在装配后工艺中可在升华期间形成的气体提供逸出路径。在另一变化形式中，可替代地或另外在衬底202中提供一或多个孔或孔隙以操作为升华路径，从而允许可升华材料的除气。例如，衬底202可具有至少一孔，其足够小以使得所述粘度的团块顶部材料将未完全湿透。在此类布置中，可完全排除顶部针孔通风口218，由此依赖于底部衬底孔隙以促进气体去除。
在又另一变化形式中，图2A-2的实例过渡封装结构200A-2说明半导体裸片206的部分密封，其中展示部分凸块结构215以仅部分地覆盖半导体裸片206和衬底202。类似于图2A-1的实例实施例，模制结构216覆盖部分凸块结构215和包含接合线210和导电指形件204A的至少一部分的衬底结构，其中至少一个针孔通风口218(即，升华通风口)形成于部分凸块结构215上方作为升华路径。可在实例实施例的范围内实现图2A-1和2A-2的各种修改。
参考图1B，实例封装流程的第二部分100B大体上涉及升华和一或多个升华通风口的密封以完成封装(即，装配后流程)。在框152处，可例如相对于如上文所描述的后端封装流程条件在合适的温度下施加热、辐射或其它实现相变的能量或工艺以使凸块结构214的牺牲密封材料(和裸片附接材料层208，在可升华裸片附接实施方案中)气化(即，升华/蒸发)。优选地，选择密封和裸片附接材料使得所述材料可升华或收缩/分层的温度可在特定封装流程的线接合窗和模制工艺窗外部。由此允许气化的密封材料和/或裸片附接材料通过模制针孔通风口/孔口(例如，图2A-1和2A-2中的针孔218)逸出，由此取决于在图1A的工艺流程100A中沉积的团块/凸块的大小/形状围绕封装中的裸片/堆叠形成空间、空腔或腔室。任选地/替代地，裸片附接材料层可能并不升华。实际上，其可例如从引线框架裸片座或从裸片分层，同时使牺牲裸片密封材料升华。在又另一变化形式中，裸片附接材料可部分分层，即，部分完好且结合到衬底或半导体裸片。在框154中说明性地展示这些工艺，但可在实例实施例的范围内实现若干额外/替代实施方案。此后，针孔通风口或开口218可使用膜层覆盖或以其它方式密封，膜层例如包括B级膜或丝网印刷密封层。在实例实施方案中，密封所述部分/封装的特定膜层的选择可取决于针孔/孔口开口的大小/形状以完成裸片/堆叠的封装(框156)。
图2B-1说明根据实例实施例的由图1B的工艺流程100B的实施产生的实例成品封装结构200B-1，其中模制结构216含有空腔或圆顶252通过使覆盖图2A-1中所说明的整个半导体裸片206的牺牲密封凸块结构214升华而形成。并且，当可升华裸片附接层材料208气化且通过模制结构216中的针孔通风口218去除时，分离间隔256可形成于半导体裸片206与衬底/座202之间。附图标记254指代部分固化或B级环氧粘合剂，在一个实施例中提供为涂覆在模制结构216上方或上的密封膜或层。在另一实施例中，膜层254可包括丝网印刷密封膜，如上文所描述。
在另一变化形式中，图2B-2的实例成品封装结构200B-2说明裸片密封材料升华，同时裸片附接层208仍然完好而不分层或分离的情境。在此配置中，尽管半导体裸片206可仍然保持附接在底部，但其与其顶部表面上的任何结构组件之间无应力。在又一变化形式中，图2B-3的实例成品封装结构200B-3说明裸片密封材料如前所述升华，而裸片附接层208从衬底座202分层/与所述衬底座分离，由此在裸片206与衬底座202之间形成分离空间209的情境。在又其它变化形式中，裸片附接材料在一些区域中可升华，同时其在其它区域中仍然经附接(例如，以供结构支撑)(例如使裸片保持在一个边缘处和使其浮于另一边缘上)。取决于是否使用可升华裸片附接材料、裸片密封的覆盖范围等等，多个额外/替代封装实施方案在实例实施例的范围内是可能的以实现各种水平的应力减小。
取决于物理-化学性质和相位转变特性，可选择多种多元醇材料以用于根据实例实施例的具有不同工艺条件的不同类型的封装流程中。升华为物质在不经过中间液相的情况下直接从固相到气相的转变。因此，升华为在低于物质在其相图中的三相点的温度和压力下发生的吸热相位转变。因此，通过控制这些变量，可在实例实施方案中设计适合于特定封装类型的特定多元醇应用。
图3说明根据另一实例实施例的具有堆叠裸片配置的实例封装结构300。类似于图2B-1中的单个裸片封装结构200B-1，衬底352和相关联的导电指形件或支柱354A/354B和355A/355B由模制结构360覆盖，所述模制结构包含由涂覆在裸片堆叠305上方的合适的牺牲密封材料的升华产生的空腔或腔室312。底部裸片302使用合适的非导电裸片间附接材料306附接到顶部上的裸片304(即，顶部裸片)。底部裸片302与衬底352分离，如由其间的空间362所说明，例如归因于裸片附接材料的升华或其收缩/分层。独立的各组接合线308和310被布置成将底部裸片302和顶部裸片304的接合垫耦合到相应的导电指形件354A/354B和355A/355B。提供密封膜363以气密密封模制结构360，其包含经形成以操作为如上文所描述的升华路径的通风口314。
有利的是，实例实施例提供含有“无应力”空腔的改进裸片封装，其中裸片/堆叠仅通过线接合悬浮。可按需要添加额外线接合或甚至可提供带状物接合，其中与机械振动隔开是特别重视的问题。根据实例实施例，浮动裸片封装将有可能经受甚至小于基于陶瓷的精密装置的应力，从而引起显著成本优点以及提高的性能(例如，通过归因于应力和温度的变化而排除/减小参数漂移)。
实例实施例可结合各种封装类型和技术进行实践，例如小外形封装(smalloutline package，SOP)、薄形的收缩型SOP或TSSOP、小外形集成电路(small outlineintegrated circuit，SOIC)、迷你小外形封装(mini small outline package，MSOP)、塑料双列直插式封装(plastic dual in-line package，PDIP)、收缩型小外形封装(shrinksmall outline package，SSOP)、方形扁平封装(quad flat package，QFP)、塑料有引线芯片载体(plastic leaded chip carrier，PLCC)等。另外或替代地，还可使用各种类型的接合技术以用于将裸片的接合垫、球状物、凸块等等耦合到衬底或裸片载体以供封装。
在实例实施例中，任何特定组件、元件、步骤、动作或功能不一定是必需的。除非明确地如此描述，否则以单数形式提及元件并非意指“一个且仅仅一个”而是意指“一或多个”。
阐述实例实施例的广泛范围的数值范围和参数为近似值，但尽可能准确地报告特定实例中所阐述的数值。然而，任何数值本身必定含有由在其相应测量结果或范围中发现的标准偏差引起的某些误差。此外，本文中所描述的所有范围涵盖其中包含的任何和所有子范围。例如，“小于10”的范围可包含最小值零与最大值10之间(且包含所述最小值和最大值)的任何和所有子范围，即，具有等于或大于零的最小值和等于或小于10的最大值的任何和所有子范围，例如1到5。
即使本文中相对于若干实施方案中的仅一个描述实例实施例的特定特征，但此特征可与其它实施方案的一或多个其它特征组合，由于对于任何给定或特定功能可能需要且有利。此外，就本文中使用术语“包含(including/includes)”、“具有(having/has)”、“使用(with)”或其变化形式这一点来说，此类术语以类似于术语“包括”的方式为包含性的。术语“中的至少一个”意指可选择所列项目中的一或多个。另外，在此描述中，关于两种材料使用的术语“在…上”(例如，一种材料“在”另一种材料“上”)可意味着所述材料之间的至少某一接触，且术语“在…上方”可意味着所述材料接近，但有可能具有一或多种额外中介材料，使得接触是可能的但不是必需的。“在…上”与“在…上方”都不暗指如本文中所使用的任何方向性。术语“约”指示所列的值可略微更改，只要所述更改不会引起工艺或结构与实例实施例的不符合。
在权利要求书的范围内，在所描述的实施例中可能进行修改，且其它实施例是可能的。

Claims (16)

1.一种制造半导体裸片封装的方法，所述方法包括：
将半导体裸片附接到具有多个电导体的衬底，所述半导体裸片具有顶表面和底表面和多个接合垫，且所述附接包括裸片附接材料的涂覆；
使用接合线将所述半导体裸片的所述接合垫线接合到所述衬底的所述多个电导体；
将可升华牺牲密封材料涂覆为凸块结构以覆盖所述半导体裸片的至少一部分、所述衬底的至少一部分以及所述接合线的至少一部分；
固化所述可升华牺牲密封材料的所述凸块结构；
涂覆模制材料以覆盖所述凸块结构、所述衬底和相关联导体；
在所述模制材料中形成面向所述半导体裸片的所述顶表面的通风口以便为所述可升华牺牲密封材料提供升华路径；
固化所述模制材料；
实现升华过程以使所述可升华牺牲密封材料气化且允许气化的密封材料通过所述通风口逸出以形成空腔，所述空腔包括所述半导体裸片的所述底表面和所述衬底之间的空间；
实现所述裸片附接材料的部分升华或部分分层，且允许气化的裸片附接材料通过所述通风口逸出；且
使用膜层覆盖所述通风口，
其中实现所述裸片附接材料的部分升华或部分分层在实现所述升华过程以使所述可升华牺牲封装材料气化的同时发生。
2.根据权利要求1所述的方法，其中所述裸片附接材料包括选自以下中的至少一个组成的多元醇的群组的可升华材料：新戊二醇、三羟甲基乙烷和2,5-二甲基-2,5己二醇。
3.根据权利要求1所述的方法，其中所述可升华牺牲密封材料选自以下中的至少一个组成的多元醇的群组：新戊二醇、三羟甲基乙烷和2,5-二甲基-2,5己二醇。
4.根据权利要求1所述的方法，其中通过具有针状物的封装工具涂覆所述模制材料，使所述针状物与所述凸块结构接触，围绕所述针状物将所述模制材料沉积在所述凸块结构上，以在所述模制材料中形成所述通风口操作为所述升华路径。
5.根据权利要求4所述的方法，其中所述模制材料包括含有熔融硅石的环氧树脂材料。
6.根据权利要求1所述的方法，其中所述将所述半导体裸片附接到所述衬底包括附接呈堆叠形式的多个半导体裸片，其中使用所述裸片附接材料将底部裸片安装到所述衬底且使用裸片间附接材料将呈堆叠方式的安装在彼此顶部上的剩余半导体裸片耦合到所述底部裸片。
7.根据权利要求6所述的方法，其中所述裸片间附接材料选自由以下组成的群组：环氧树脂材料、氰酸酯共混材料、软焊剂材料和共晶接合材料。
8.根据权利要求1所述的方法，其中覆盖所述通风口的所述膜层包括B级环氧树脂。
9.根据权利要求1所述的方法，其中覆盖所述通风口的所述膜层包括丝网印刷密封层。
10.根据权利要求1所述的方法，其中与所述半导体裸片附接的所述衬底包括具有裸片座的引线框架，所述裸片座上安装有所述半导体裸片。
11.一种半导体封装，包括：
引线框架，其包含裸片座和多个导体；
半导体裸片，其通过接合线电连接到所述多个导体，所述半导体裸片具有顶表面和底表面；
模制结构，其覆盖所述引线框架的部分、所述半导体裸片以及所述接合线，所述模制结构包含面向所述半导体裸片的所述顶表面的通风口；
空腔，其位于所述模制结构内并围绕所述半导体裸片，其中所述空腔的一部分位于所述半导体裸片的所述底表面和所述裸片座的顶表面之间，且其中所述多个导体中的每一者的两个表面从所述半导体封装暴露；以及
部分完整的裸片附接材料，其结合到所述半导体裸片或所述裸片座，并且经配置以将所述半导体裸片的一部分附接到所述裸片座的表面。
12.根据权利要求11所述的半导体封装，其进一步包括与所述模制结构的部分接触并覆盖所述通风口的膜层。
13.根据权利要求11所述的半导体封装，其中所述模制结构覆盖所述多个导体中的每一者的至少一部分。
14.根据权利要求11所述的半导体封装，其中所述模制结构覆盖所述接合线中的每一者的至少一部分。
15.根据权利要求11所述的半导体封装，其中所述模制结构由含有硅石的环氧树脂材料形成。
16.根据权利要求11所述的半导体封装，其中所述裸片座的底表面从所述半导体封装暴露。
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