JP6895126B2 - 半導体パッケージ - Google Patents

半導体パッケージ Download PDF

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Publication number
JP6895126B2
JP6895126B2 JP2018060114A JP2018060114A JP6895126B2 JP 6895126 B2 JP6895126 B2 JP 6895126B2 JP 2018060114 A JP2018060114 A JP 2018060114A JP 2018060114 A JP2018060114 A JP 2018060114A JP 6895126 B2 JP6895126 B2 JP 6895126B2
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JP
Japan
Prior art keywords
sealing resin
semiconductor package
package according
lid
internal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018060114A
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English (en)
Japanese (ja)
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JP2019175923A5 (enExample
JP2019175923A (ja
Inventor
義貴 大坪
義貴 大坪
正之 安藤
正之 安藤
孝太 大原
孝太 大原
敬雅 小田
敬雅 小田
琢郎 森
琢郎 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2018060114A priority Critical patent/JP6895126B2/ja
Priority to US16/188,772 priority patent/US10593605B2/en
Priority to DE102019201158.6A priority patent/DE102019201158B4/de
Priority to CN201910221792.8A priority patent/CN110310930B/zh
Publication of JP2019175923A publication Critical patent/JP2019175923A/ja
Publication of JP2019175923A5 publication Critical patent/JP2019175923A5/ja
Application granted granted Critical
Publication of JP6895126B2 publication Critical patent/JP6895126B2/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
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    • H01L2924/1025Semiconducting materials
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    • H01L2924/10254Diamond [C]
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    • H01L2924/1025Semiconducting materials
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    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Fuses (AREA)
JP2018060114A 2018-03-27 2018-03-27 半導体パッケージ Active JP6895126B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2018060114A JP6895126B2 (ja) 2018-03-27 2018-03-27 半導体パッケージ
US16/188,772 US10593605B2 (en) 2018-03-27 2018-11-13 Semiconductor package
DE102019201158.6A DE102019201158B4 (de) 2018-03-27 2019-01-30 Halbleiterbaugruppe
CN201910221792.8A CN110310930B (zh) 2018-03-27 2019-03-22 半导体封装件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018060114A JP6895126B2 (ja) 2018-03-27 2018-03-27 半導体パッケージ

Publications (3)

Publication Number Publication Date
JP2019175923A JP2019175923A (ja) 2019-10-10
JP2019175923A5 JP2019175923A5 (enExample) 2020-08-20
JP6895126B2 true JP6895126B2 (ja) 2021-06-30

Family

ID=67910315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018060114A Active JP6895126B2 (ja) 2018-03-27 2018-03-27 半導体パッケージ

Country Status (4)

Country Link
US (1) US10593605B2 (enExample)
JP (1) JP6895126B2 (enExample)
CN (1) CN110310930B (enExample)
DE (1) DE102019201158B4 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11527456B2 (en) * 2019-10-31 2022-12-13 Ut-Battelle, Llc Power module with organic layers
JP7209615B2 (ja) * 2019-11-13 2023-01-20 三菱電機株式会社 半導体装置
WO2021195871A1 (zh) * 2020-03-30 2021-10-07 华为技术有限公司 埋入式基板、电路板组件及电子设备
JP7735655B2 (ja) * 2020-10-15 2025-09-09 富士電機株式会社 半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0233953A (ja) * 1988-07-22 1990-02-05 Mitsubishi Electric Corp 半導体装置
JP3506733B2 (ja) * 1993-07-09 2004-03-15 ローム株式会社 安全ヒューズ付き面実装型電子部品の構造
JP3019679B2 (ja) * 1993-09-08 2000-03-13 富士電機株式会社 半導体装置の内部配線構造
US5744860A (en) 1996-02-06 1998-04-28 Asea Brown Boveri Ag Power semiconductor module
JPH1012806A (ja) * 1996-06-24 1998-01-16 Toshiba Corp 半導体装置
DE19639279C2 (de) * 1996-09-25 2002-01-17 Daimlerchrysler Rail Systems Stromrichterschaltung
JP2000138107A (ja) 1998-11-04 2000-05-16 Mitsubishi Materials Corp 半導体サージ吸収素子
JP3778268B2 (ja) * 2001-03-21 2006-05-24 オムロン株式会社 過電流遮断構造の製造方法
JP4615289B2 (ja) * 2004-11-12 2011-01-19 三菱電機株式会社 半導体装置
US20070075822A1 (en) * 2005-10-03 2007-04-05 Littlefuse, Inc. Fuse with cavity forming enclosure
JP2008235502A (ja) * 2007-03-20 2008-10-02 Mitsubishi Electric Corp 樹脂封止型半導体装置
CN104112730A (zh) * 2013-06-09 2014-10-22 广东美的制冷设备有限公司 智能功率模块及其制造方法
JP6916997B2 (ja) * 2016-03-17 2021-08-11 富士電機株式会社 半導体装置
JP6627698B2 (ja) * 2016-09-13 2020-01-08 三菱電機株式会社 半導体装置
JP2018060114A (ja) 2016-10-07 2018-04-12 キヤノン株式会社 投影型表示装置
US9865537B1 (en) * 2016-12-30 2018-01-09 Texas Instruments Incorporated Methods and apparatus for integrated circuit failsafe fuse package with arc arrest

Also Published As

Publication number Publication date
US20190304859A1 (en) 2019-10-03
DE102019201158B4 (de) 2022-01-27
DE102019201158A1 (de) 2019-10-02
CN110310930B (zh) 2023-06-30
US10593605B2 (en) 2020-03-17
CN110310930A (zh) 2019-10-08
JP2019175923A (ja) 2019-10-10

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