JP6871438B2 - Game machine - Google Patents

Description

The present invention relates to gaming machines such as pachinko gaming machines and slot machines.

As a game machine, a game machine that defines an interrupt address when an interrupt of a game machine control program occurs in an interrupt vector definition area is known (Patent Document 1).

Japanese Unexamined Patent Publication No. 2002-52215 (paragraph 0033, etc.)

However, the gaming machine described in Patent Document 1 has room for improvement.

The present invention has been made by paying attention to such a problem, and an object of the present invention is to provide a gaming machine capable of preventing an unintended interrupt process from being executed in advance.

(1) In a game machine capable of playing a game
A memory means for storing programs and
A microcomputer that executes processing according to a program stored in the storage means, and
With
The program includes an interrupt program that is executed in response to the occurrence of an interrupt.
The microcomputer
When interrupts are permitted, interrupt processing execution means that executes processing according to the interrupt program based on the interrupt, and interrupt processing execution means.
An address storage means having a storage area capable of storing the address of the interrupt program in the storage means, and an address storage means.
A determination means for determining whether or not the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is started, and a determination means.
A start-prohibiting means that does not start the microcomputer when the determination means determines that the address of the interrupt program is not within the predetermined range.
A timer value storage means that can store a timer value in a plurality of timer value storage areas that can store a timer value, and a timer value storage means that can store the timer value.
It is provided with a timer value updating means capable of updating the timer values stored in a plurality of timer value storage areas in the processing according to the interrupt program.
The timer value storage means, when any kind of timing conditions among a plurality of types of timing condition is satisfied, stores the timer value corresponding to the regimen during conditions timer value storage area according to the regimen at conditions,
Consecutive addresses are assigned to multiple timer value storage areas according to a predetermined rule.
The timer value updating means can update the timer values stored in a plurality of timer value storage areas by repeatedly executing the timer value updating process.
The timer value update process changes the designated address for the timer value storage area by performing a predetermined operation, determines the timer value stored in the timer value storage area corresponding to the changed designated address, and determines the timer value. There without updating the timer value if 0, a process of updating the timer value if it is other than 0, the gaming machine.
The gaming machine may be configured as follows.
The gaming machine of means 1 is
In a game machine (slot machine 1) that plays a game
A first control means (main control unit 41) capable of performing the first control and maintaining the control state even when the power supply to the game machine (slot machine 1) is stopped.
A second control that can perform the second control based on the control information (command) transmitted from the first control means and can maintain the control state even if the power supply to the game machine (slot machine 1) is stopped. Control means (sub-control unit 91) and
With
The first control means is
When the power failure condition is satisfied (input of a voltage drop signal), the power supply process (power failure process (main)) is performed so that the control state before the power supply to the game machine (slot machine 1) is stopped can be restored. )) And the means of executing the power failure processing
A control information storage means (command storage process) that creates control information (command) to be transmitted to the second control means (sub-control unit 91) according to the progress of control and stores it in a storage area (command queue).
The control information (command) stored in the storage area (command queue) is sent to the second control means (sub control unit 91) every predetermined trigger (once every four timer interrupt processes (main)). First control information transmission means (normal command transmission processing) and
When the power failure condition is satisfied (input of a voltage drop signal), the control information (command) stored in the storage area (command queue) before the power failure process (power failure process (main)) is executed. A second control information transmitting means (command transmission processing at the time of power failure) that transmits all to the second control means (sub-control unit 91), and
Including
The period from the establishment of the power interruption condition (input of the voltage drop signal) to the inoperability of the first control means (main control unit 41) (the period until the inoperability due to the reset signal) is described above. The maximum number of control information (32 commands) that can be stored in the storage area (command queue) is transmitted to the second control means (sub-control unit 91), and the power failure process (power failure process (main)) is performed. )) Is characterized by being longer than the time required to complete.
According to this feature, when the power interruption condition is satisfied, the first control means transmits all the control information stored in the storage area to the second control means, and then executes the power interruption process. Therefore, the control state on the game control means side at the time of power interruption and the time of recovery from the power failure can be matched as much as possible with the control state on the game control means side specified by the effect control means side. Further, during the period from the establishment of the power failure condition until the first control means becomes inoperable, the maximum number of control information that can be stored in the storage area is transmitted to the second control means, and the power is transmitted. Since it is longer than the period required to complete the disconnection process, it is possible to reliably execute the process from the transmission of the control information to the disconnection process after the power failure condition is satisfied.

The first control means may be a control means that controls the game, or may be a control means that controls a control other than the control of the game, for example, a control of the effect. Further, the second control means may be any control means that performs some control based on the control information transmitted from the first control means. For example, the first control means is a control means that controls the game. In a certain case, the control means that controls the effect based on the control information transmitted from the first control means may be used as the second control means, or the control means that the first control means controls the effect. In some cases, the control means that controls the effect device based on the control information transmitted from the first control means may be used as the second control means.
Further, the power cut processing for enabling the return to the control state before the power supply to the game machine is stopped is, for example, whether or not the data is normal by the checksum or the parity diagnosis when the power supply is returned. This corresponds to the process of setting data so that it can be determined.
Further, the period until the first control means becomes inoperable is the period until the first control means becomes inoperable below the operable voltage of the first control means, or the first control means becomes inoperable due to a decrease in power supply. It is the period until the reset signal is input before the operation becomes inoperable below the operable voltage.
Further, the maximum number of control information that can be stored in the storage area is transmitted to the second control means during the period from the establishment of the power failure condition until the first control means becomes inoperable. In addition, the period required for the power interruption process to be completed is longer than the period required, for example, the period from the establishment of the power interruption condition to the inoperability of the first control means is stored in the storage area. The voltage at which the power failure condition is satisfied and the first power so as to transmit the maximum possible number of control information to the second control means and to be longer than the period required for the power failure process to be completed. The time required for the control means to drop to the inoperable voltage may be set, or the period from the establishment of the power failure condition to the inoperability of the first control means can be stored in the storage area. The first control after the power failure condition is satisfied so that the maximum number of control information is transmitted to the second control means and the period required for the power failure process to be completed is longer than the period required. The decrease in the supply voltage to the means may be delayed by a capacitor or the like, or the storage area may be set in a period shorter than the period from the establishment of the power failure condition until the first control means becomes inoperable. The maximum number of control information that can be stored may be transmitted to the second control means, and the maximum number of control information that can be stored in the storage area may be set so that the power interruption process can be completed.

The gaming machine of the means 2 of the present invention is the gaming machine according to the means 1.
The power failure condition was satisfied (input of a voltage drop signal), and all the control information (commands) stored in the storage area (command queue) was transmitted to the second control means (sub-control unit 91). After that, the output port (parallel output port 513) that outputs control information (command) is initialized.
According to this feature, after the power interruption condition is satisfied and all the control information stored in the storage area is transmitted, the output port that outputs the control information is initialized, so that the power supply is unstable. It is possible to prevent the control information from being transmitted by mistake.

The gaming machine of means 3 of the present invention is the gaming machine according to means 1 or 2.
The first control information transmission means (normal command transmission process) is a control information (command) stored in the storage area (command queue) every predetermined trigger (once every four timer interrupt processes (main)). Among them, a predetermined number of control information (command of 1) is transmitted to the second control means (sub-control unit 91).
According to this feature, even when a predetermined number or more of control information is stored in the storage area, the number of control information transmitted at one time is limited to a predetermined number. It is possible to prevent the other control by the control means from being delayed.

The gaming machine of means 4 of the present invention is the gaming machine according to any one of means 1 to 3.
The first control information transmission means (normal command transmission processing) is a control information (internal winning) according to the progress of control in the storage area (command queue) at a predetermined trigger (timer interrupt processing (main) once every four times). It is characterized in that specific control information (door command) indicating the state of the first control means (main control unit 41) is transmitted when a command or the like is not stored.
According to this feature, the state of the first control means can be specified in the second control means by transmitting the specific control information, and the specific control information is controlled in the storage area at a predetermined trigger according to the progress of control. Since the information is transmitted when the information is not stored, the transmission of the control information according to the progress of the control is delayed by the transmission of the specific control information, or the transmission of the specific control information causes another control by the first control means. It is possible to prevent delays.

The gaming machine of the means 5 of the present invention is the gaming machine according to the means 4.
The first control means (main control unit 41) is
A predetermined control information transmitting means for transmitting predetermined control information (return command) when the power supply to the gaming machine (slot machine 1) is started and the control state is restored before the power supply to the gaming machine is stopped. ,
When the power supply to the game machine (slot machine 1) is started, the transmission limiting means for restricting the transmission of the specific control information (door command) until the predetermined control information (return command) is transmitted, and
It is characterized by including.
According to this feature, the state of the first control means can be specified on the second control means side after it is determined that the first control means side returns.

The gaming machine of means 6 of the present invention is the gaming machine according to any one of means 1 to 5.
An interrupt processing execution means that executes processing according to an interrupt program (timer interrupt processing (main)) based on an interrupt, and
Address storage means (vector table) that can store the address of the interrupt program (timer interrupt process (main)),
A determination means for determining at startup whether or not the address stored in the address storage means (vector table) is within a predetermined range (the area of the program area in which the program or the like is actually stored).
When it is determined that the address stored in the address storage means (vector table) is not within the predetermined range, the start limiting means (in the main control unit 41, the address of the vector table is in the program area of the program or the like. If it is not the area actually stored, it will not be started),
It is characterized by having.
According to this feature, it is possible to prevent an unintended interrupt process from being executed in advance.

The gaming machine of means 7 of the present invention is the gaming machine according to any one of means 1 to 6.
A storage area setting means for setting a storage area (program / data area) in which a specific program is stored at startup, and a storage area setting means.
Specific program execution means (execution of the program by the main control unit 41) that executes processing according to the specific program stored in the storage area (program / data area) set by the storage area setting means, and
Anomalous control execution means that executes anomaly control (illegal access reset) when a specific program execution means calls a program stored in an area other than the storage area (program / data area) set by the storage area setting means.
With
The predetermined range is characterized by including at least the address of the area where the specific program is stored.
According to this feature, it is possible to prevent the execution of an unauthorized program.

The gaming machine of the means 8 of the present invention is the gaming machine according to any one of the means 1 to 7.
A data storage means for storing data in which a plurality of timer value storage areas (for example, 1-byte timers A to C) are provided, and
When any of a plurality of types of time timing conditions (for example, 1-byte timers A to C) is satisfied, a timer value storage area (for example, 1-byte timer A) corresponding to the time timing conditions is satisfied. To C), a timer value storage means (main process) for storing the timer value according to the timekeeping condition, and
A timer value updating means (time counter updating process) capable of updating the timer values stored in a plurality of timer value storage areas (for example, 1-byte timers A to C) every predetermined cycle (about 2.24 ms).
With
Consecutive addresses (7E2Ch to 7E2Eh) are assigned to a plurality of timer value storage areas (for example, 1-byte timers A to C) according to a predetermined rule (+1).
The timer value update means performs a predetermined operation (designated address + 1) for an update process (process of subtracting 1 from the value indicated by the pointer) for updating the timer value stored in the timer value storage area corresponding to the specified address. The feature is that multiple types of timer values can be updated by repeatedly executing while changing the specified address for the timer value storage area.
According to this feature, consecutive addresses are assigned to a plurality of timer value storage areas according to a predetermined rule, and an update process for updating the timer values stored in the timer value storage area corresponding to the specified address is predetermined. Since multiple types of timer values are updated by repeatedly executing while changing the specified address for the timer value storage area by performing the operation of, when performing the process of updating multiple types of timer values for each type of timer value. The program capacity can be reduced as compared with the above.
It should be noted that the assignment of consecutive addresses according to a predetermined rule means that, for example, an address to which N (N is a natural number) is added from the start address and the start address is assigned.
Further, changing the designated address for the timer value storage area by performing a predetermined operation means, for example, changing the designated address by adding or subtracting a value according to the number of processes to the current designated address. It corresponds to changing the designated address by adding or subtracting a constant from the reference address. At this time, the value or constant according to the number of processes may differ depending on the storage capacity of the timer value. For example, in the configuration where the timer value is stored byte by byte, the value according to the number of processes is the number of processes. Depending on the number of processes, it becomes 1, 2, 3 ..., and the constant becomes 1, but if the configuration is such that the timer value is stored by 2 bytes, the value according to the number of processes becomes 2, 4, 6 ... Depending on the number of processes. , The constant is 2.

The present invention may have only the invention-specific matters described in the claims of the present invention, and has a configuration other than the invention-specific matters together with the invention-specific matters described in the claims of the present invention. It may be a thing.

It is a front view of the slot machine of the Example to which this invention was applied. It is a perspective view which shows the internal structure of a slot machine. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of the main control part. It is a figure which shows the memory map of the RAM mounted on the main control part. It is a flowchart which shows the control content of the initial setting process which a main control part executes. It is a flowchart which shows the control content of the setting change processing executed by the main control part. It is a flowchart which shows the control content of the main process executed by the main control unit. It is a flowchart which shows the control content of the timer interrupt process (main) executed by the main control unit. It is a flowchart which shows the control content of the timer interrupt process (main) executed by the main control unit. It is a flowchart which shows the control content of the command storage process executed by the main control part. It is a flowchart which shows the control content of the normal time command transmission processing which the main control part executes. It is a flowchart which shows the control content of the command transmission processing at the time of power failure executed by the main control unit. It is a flowchart which shows the control content of the power failure process which a main control part executes. It is a timing chart for demonstrating the flow of control at the time of activation and power-off of a main control part and a sub-control part. It is a flowchart which shows the control content when the main control part determines the value of a timer counter in a main process. It is a figure which shows the storage area of the timer counter in RAM. It is a flowchart which shows the control content of the time counter update process executed by the main control part.

A mode for carrying out the gaming machine according to the present invention will be described below based on examples.

An embodiment of a slot machine, which is a gaming machine to which the present invention is applied, will be described with reference to the drawings. As shown in FIG. 1, the slot machine 1 of the present embodiment includes a housing 1a having an open front surface and a housing 1a thereof. It is composed of a front door 1b rotatably and pivotally supported at a side end of the body 1a.

As shown in FIG. 2, inside the housing 1a of the slot machine 1 of this embodiment, reels 2L, 2C, and 2R (hereinafter, left reel, middle reel, and right reel) in which a plurality of types of symbols are arranged on the outer circumference are arranged. ) Are arranged side by side in the horizontal direction, and as shown in FIG. 1, three consecutive symbols among the symbols arranged on the reels 2L, 2C, and 2R can be seen from the see-through window 3 provided on the front door 1b. It is arranged like this.

On the outer peripheral portions of the reels 2L, 2C, and 2R, a predetermined number of symbols (identification information) that can be distinguished from each other are drawn in a predetermined order. The symbols drawn on the outer peripheral portions of the reels 2L, 2C, and 2R are displayed in the upper, middle, and lower three stages in the see-through window 3 provided at substantially the center of the front door 1b.

Each reel 2L, 2C, 2R is rotated by the corresponding reel motors 32L, 32C, 32R (see FIG. 3), so that the symbols of the reels 2L, 2C, and 2R are continuous with the see-through window 3. While the reels 2L, 2C, and 2R are stopped rotating, three consecutive symbols are derived and displayed on the perspective window 3 as a display result.

Inside the reels 2L, 2C and 2R, there are reel sensors 33L, 33C and 33R that detect the reference position for each of the reels 2L, 2C and 2R, and a reel LED 55 that irradiates the reels 2L, 2C and 2R from the back. , Are provided. Further, the reel LED 55 is composed of 12 LEDs corresponding to three consecutive symbols of reels 2L, 2C, and 2R, and each symbol can be independently irradiated.

A display area 51a of the liquid crystal display 51 (see FIG. 1) is arranged at a position on the front side (player side) of the reels 2L, 2C, and 2R of the front door 1b. The liquid crystal display 51 has a liquid crystal panel having transparency in a state where no voltage is applied to the liquid crystal element, and passes through the transmission region 51b and the perspective window 3 corresponding to the perspective window 3 of the display region 51a. The reels 2L, 2C, and 2R can be visually recognized from the player side.

As shown in FIG. 1, the front door 1b has a medal insertion unit 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player-owned game value). MAXBET switch 6, which is operated when setting the maximum number of bets among the specified number of bets determined according to the gaming state within that range, and the setting of medals and bets stored as credits. Settlement switch 10, which is operated when the medals used for the above are settled (the medals used for setting the credit and the number of bets are returned), the start switch 7, which is operated when the game is started, reels 2L, 2C. The stop switches 8L, 8C, and 8R, which are operated when the rotation of the 2Rs is stopped, are provided so as to be operable by the player.

Further, as shown in FIG. 1, the front door 1b shows a credit display 11 that displays the number of medals stored as credits, the number of medals paid out due to the occurrence of a prize, and the contents when an error occurs. Game auxiliary display 12 that displays an error code, etc., 1BETLED14 that notifies by lighting that the number of bets is set to 1, 2BETLED15 that notifies by lighting that the number of bets is set to 2, and 3 settings to the number of bets. 3BETLED16 that notifies by lighting that the game is being inserted, insertion request LED17 that notifies by lighting that a medal can be inserted, and start effective LED18 that notifies by lighting that the game start operation by operating the start switch 7 is effective. , Waiting LED19 to notify by lighting that a wait (a state of waiting for the start of rotation of the reel because a certain period of time has not passed since the previous game start) is in progress, and a replay game to be described later is lit. A game display unit 13 is provided with an LED 20 during replay to be notified by.

Inside the MAXBET switch 6, a BET switch effective LED21 (see FIG. 3) is provided to notify by lighting that the betting number setting operation by operating the MAXBET switch 6 is effective, and the stop switches 8L, 8C, Inside the 8R, left, middle, and right stop effective LEDs 22L, 22C, and 22R (see FIG. 3) are provided to notify by lighting that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is effective. Has been done.

Inside the front door 1b, as shown in FIG. 2, a reset switch 23 for detecting an error state described later and a reset operation for canceling a stop state described later by a predetermined key operation, and a change of a setting value described later. A set value display 24 that displays the set value at that time while checking the inside or the set value, and a hit that controls the stop state (a state in which the progress of the game is restricted until the reset operation is performed) at a predetermined trigger. Stop switch 36a for selecting enable / disable of the stop function, automatic control to automatic settlement processing (processing to settle (return) medals stored as credits regardless of the player's operation) at a predetermined trigger The automatic settlement switch 36b for selecting the enable / disable of the settlement function and the flow path of the medals inserted from the medal insertion unit 4 are provided on the side of the hopper tank 34a (see FIG. 2) described later provided inside the housing 1a. Alternatively, a flow path switching solenoid 30 for selectively switching to either one of the medal payout outlet 9 sides, a medal insertion unit 31 for detecting medals inserted from the medal insertion unit 4 and flowing down to the hopper tank 34a side, and an insertion medal sensor. A medal selector 29 having a slot sensor 26 for detecting the insertion of foreign matter on the upstream side of 31 and a door open detection switch 25 (see FIG. 3) for detecting the open state of the front door 1b are provided.

Inside the housing 1a, as shown in FIG. 2, the reels 2L, 2C, 2R, the reel motors 32L, 32C, 32R (see FIG. 3), and the reel reference positions of the reels 2L, 2C, and 2R, respectively, are located. Reel unit 2 composed of detectable reel sensors 33L, 33C, 33R (see FIG. 3), external output board 1000 for outputting an external output signal (see FIG. 3), and medals inserted from the medal insertion unit 4 are stored. The hopper tank 34a, the hopper motor 34b for paying out the medals stored in the hopper tank 34a from the medal payout outlet 9 (see FIG. 3), and the payout sensor 34c for detecting the medal paid out by driving the hopper motor 34b (see FIG. 3). A hopper unit 34 and a power supply box 100 (see FIG. 3) are provided.

An overflow tank 35 for storing medals overflowing from the hopper tank 34a is provided on the side of the hopper unit 34. Inside the overflow tank 35, a full tank sensor 35a (see FIG. 3) for detecting that the stored medals are full is provided.

As shown in FIG. 2, the front surface of the power supply box 100 functions as a setting key switch 37 for switching to a setting change state or a setting confirmation state, and as a reset switch for canceling an error state or a stop state in a normal state. However, in the setting change state, the reset / setting switch 38 that functions as a setting switch for changing the setting value of the winning probability (ball output rate) of the internal lottery described later, and the power supply that is operated when the power is turned on / off. A switch 39 is provided.

Since the power supply box 100 is provided inside the housing 1a and the front door 1b can be opened by a predetermined key operation possessed by a clerk or the like, the power supply box 100 is provided on the front surface of the power supply box 100. The setting key switch 37, the reset / setting switch 38, and the power switch 39 can be operated only by a person such as a clerk who has the key, and cannot be operated by the player. The same applies to the reset switch 23 detected by a predetermined key operation. In particular, since the setting key switch 37 requires further key operation after opening the front door 1b by key operation, only the clerk who has the key to operate the setting key switch 37 among the clerk of the amusement park. It is possible to operate.

When playing a game on the slot machine 1 of this embodiment, first, medals are inserted from the medal insertion unit 4, or the number of bets is set using credits. To use the credit, operate the MAXBET switch 6. When the specified number of bets determined according to the game state is set, the winning line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the game can be started. Become. If more than the maximum number of medals are inserted out of the specified number corresponding to the gaming state, that amount will be added to the credit.

The winning line is a line set to determine whether the combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a combination of winning symbols. In this embodiment, as shown in FIG. 1, only the winning line LN set across the symbols arranged horizontally in the middle stage of the reel 2L, the middle stage of the reel 2C, and the middle stage of the reel 2R, that is, the middle stage is used as the winning line. It has been decided. In this embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

Further, in this embodiment, in order to make it easy to recognize that the winning line LN has a combination of symbols constituting the winning, the invalid lines LM1 to 4 are set separately from the winning line LN. The invalid lines LM1 to LM1 to 4 are not determined to win by the combination of the symbols aligned with the invalid lines LM1 to 4, but are invalid lines when the winning line LN has a combination of symbols constituting a specific winning. By configuring the combination of symbols (for example, bell-bell-bell) that will be awarded when the winning line LN is aligned with any of LM1 to LM4, the symbols constituting the winning line LN are the symbols that constitute a specific winning. This makes it easier to recognize that the combinations are complete.

When the start switch 7 is operated while the game can be started, the reels 2L, 2C, and 2R are rotated, and the symbols of the reels 2L, 2C, and 2R are continuously changed. When any of the stop switches 8L, 8C, and 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, and 2R is stopped, and the display result is derived and displayed on the perspective window 3.

When all reels 2L, 2C, and 2R are stopped, one game ends, and a predetermined combination of symbols (hereinafter, also referred to as a combination) on the winning line LN is displayed on each reel 2L, 2C, and 2R. If the game is stopped as a result, a prize will be generated, and a number of medals determined according to the prize will be given to the player and added to the credit. Further, when the maximum number of credits (50 in this embodiment) is reached, the medals are directly paid out from the medal payout outlet 9 (see FIG. 1). Further, when the combination of symbols accompanied by the transition of the gaming state stops on the winning line LN as the display result of each reel 2L, 2C, 2R, the combination of symbols is shifted to the gaming state according to the combination of symbols. ..

In this embodiment, the game starts when the operation of the start switch 7 is detected while the operation of the start switch 7 is valid, and the game ends when all the reels are stopped. In addition, one unit of control for executing the game (game control) starts when all the controls associated with the end of the previous game are completed, and when all the controls associated with the end of the game are completed. finish.

Further, in this embodiment, a configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, and a configuration using four or more reels may be used. In the configuration using two or more reels, the winning may be determined based on the combination of the display results derived to all the two or more reels. Further, in this embodiment, the variable display device is configured by a physical reel, but the variable display device may be configured by an image display device such as a liquid crystal display.

Further, in the slot machine 1 in the present embodiment, after the game is started and the reels 2L, 2C, and 2R are rotated to start the fluctuation of the symbol, one of the stop switches 8L, 8C, and 8R is operated. When this is done, the rotation of the reels corresponding to the stop switches 8L, 8C, 8R is stopped and the symbol is stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

The reels 2L, 2C, and 2R rotate 80 times per minute and change the symbol of 80 x 21 (the number of symbol frames per reel) = 1680 frames, so that a maximum of 4 frames can be drawn in 190 ms. You will be able to do it. That is, the symbols that can be selected as the stop symbols are the symbols that are displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols that are up to 4 frames ahead of them, for a total of 5 frames.

Therefore, for example, when any of the stop switches 8L, 8C, and 8R is operated, when the symbol displayed at the bottom of the reel corresponding to the stop switch is used as a reference, the symbol is up to 4 frames ahead. Since the symbol can be displayed in the lower row, the symbol displayed in the middle row of the reel corresponding to the stop switch when any of the stop switches 8L and 8R is operated in each of the reels 2L, 2C and 2R. Designs arranged within 5 frames including the above can be displayed on the winning line.

In the following, reels 2L, 2C, and 2R may be simply referred to as reels when it is not necessary to distinguish them. Further, the reel 2L may be referred to as a left reel, the reel 2C may be referred to as a middle reel, and the reel 2R may be referred to as a right reel. Further, the operation of stopping the reels 2L, 2C and 2R by operating the stop switches 8L, 8C and 8R may be referred to as a stop operation.

FIG. 3 is a block diagram showing the configuration of the slot machine 1. As shown in FIG. 3, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game control board 40 controls the game state, and the effect control board 90 controls the game state. The effect is controlled according to the above, and the drive power supply for the electric components constituting the slot machine 1 is generated by the power supply board 101 and supplied to each part.

An AC100V power supply is supplied to the power supply board 101 from the outside, and a DC voltage required for driving the electric components constituting the slot machine 1 is generated from the AC100V power supply, so that the game control board 40 and the effect control board 90 are generated. It is supposed to be supplied to. Further, the above-mentioned hopper motor 34b, payout sensor 34c, full tank sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

The game control board 40 includes the MAXBET switch 6, the start switch 7, the stop switch 8L, 8C, 8R, the settlement switch 10, the reset switch 23, the stop switch 36a, the automatic settlement switch 36b, the input medal sensor 31, and the door opening. The detection switch 25, the reel sensors 33L, 33C, and 33R are connected, and the payout sensor 34c, the full tank sensor 35a, the setting key switch 37, and the reset / setting switch 38 described above are connected via the power supply board 101. The detection signals of these connected switches are input. Further, on the game control board 40, the above-mentioned credit display 11, game auxiliary display 12, 1-3 BETLED 14 to 16, input request LED 17, start effective LED 18, wait LED 19, replay LED 20, BET switch effective LED 21, left. , Middle, right stop effective LEDs 22L, 22C, 22R, set value display 24, flow path switching solenoid 30, reel motors 32L, 32C, 32R are connected, and the hopper motor 34b described above is connected via the power supply board 101. These electrical components are connected and are driven based on the control of the main control unit 41, which will be described later, mounted on the game control board 40.

The game control board 40 is composed of a main control unit 41 that performs processing related to the progress of the game, a control clock generation circuit 42 that generates a control clock CCLK, a random clock generation circuit 43 that generates a random clock RCLK, and switches. The switch detection circuit 44 that takes in the input detection signal and transmits it to the main control unit 41, the motor drive circuit 45 that transmits the motor drive signal (phase signal of the stepping motor) to the reel motors 32L, 32C, 32R, and the solenoid drive signal. A solenoid drive circuit 46 that transmits to the flow path switching solenoid 30, an LED drive circuit 47 that transmits LED drive signals to various indicators and LEDs, and a voltage drop signal indicating that when a voltage drop is detected is sent to the main control unit 41. A power failure detection circuit 48 that outputs to the main control unit 41 and a reset circuit 49 that gives a system reset signal to the main control unit 41 when the power supply is unstable such as when the power is turned on or when the power is cut off are mounted.

FIG. 4 shows a configuration example of the main control unit 41 mounted on the game control board 40. The main controller 41 shown in FIG. 4 is a one-chip microcomputer, which includes an external bus interface 501, a clock circuit 502, a collation block 503, a unique information storage circuit 504, an arithmetic circuit 505, and a reset / interrupt. Controller 506, CPU (Central Processing Unit) 41a, ROM (Read Only Memory) 41b, RAM (Random)
Access Memory) 41c, free run counter circuit 507, random number circuits 508a, 508b, timer circuit 509, interrupt controller 510, parallel input port 511, serial communication circuit 512, parallel output port 513, and address. It is configured to include a decoding circuit 514. The reset / interrupt controller 506 includes an out-of-designated area travel prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b.

The reset / interrupt controller 506 is for controlling various resets and interrupt requests that occur inside or outside the main control unit 41. The reset / interrupt controller 506 includes an out-of-designated area travel prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit that monitors whether or not the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when it detects that the user program is executed outside the designated area. Further, the watchdog timer 506b has a function of generating a timeout signal for each set period.

The external bus interface 501 is a bus interface having an interface function between the external bus and the internal bus of the chip constituting the main control unit 41, a direction control function for the address bus, the data bus, and each control signal, and the like. The clock circuit 502 is a circuit that generates the internal system clock SCLK by dividing the control clock CCLK by two or the like. The collation block 503 has a function of connecting to an external collator and collating chips. The unique information storage circuit 504 is a circuit that stores a plurality of types of unique information that is internal information of the main control unit 41. The arithmetic circuit 505 is a circuit that performs multiplication and division.

The CPU 41a is a control CPU that executes game control in the slot machine 1 by executing a user program (game control processing program for game control) based on the control code read from the ROM 41b. When such game control is executed, the CPU 41a reads the fixed data from the ROM 41b, the fixed data read operation, the CPU 41a writes various variable data to the RAM 41c and temporarily stores the variable data, and the CPU 41a is temporarily stored in the RAM 41c. Variable data read operation to read various variable data, CPU 41a receives input of various signals from the outside of the main control unit 41 via the external bus interface 501, parallel input port 511, serial communication circuit 512, etc., CPU 41a Is also used to output various signals to the outside of the main control unit 41 via the external bus interface 501, the serial communication circuit 512, the parallel output port 513, and the like.

The ROM 41b stores a control code indicating a user program (game control processing program for game control), fixed data, and the like. The RAM 41c provides a work area for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power supply. That is, even if the power supply to the slot machine 1 is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period.

An 8-bit free run counter is mounted as the free run counter circuit 507. The random number circuits 508a and 508b are circuits that generate numerical data such as 8-bit random numbers and 16-bit random numbers, which are random number values having a predetermined update range. In this embodiment, the hardware random number generated by the 16-bit random number circuit 508b out of the random number circuits 508a and 508b is used as a random number for internal lottery described later. The timer circuit 509 is a 16-bit programmable timer, which counts down the set timer value based on the input of the control clock CCLK, and outputs an interrupt request signal to the interrupt controller when it reaches 0000 h. In this embodiment, the timer circuit 509 can be used to perform periodic interrupt requests and time measurement.

The interrupt controller 510 is a circuit that controls an external interrupt request from an interrupt terminal and an interrupt request from a built-in peripheral circuit (for example, serial communication circuit 512, random number circuits 508a, 508b, timer circuit 509). .. The parallel input port 511 has a built-in 8-bit wide input-only port. Further, the parallel output port 513 included in the main control unit 41 shown in FIG. 4 has a built-in 11-bit wide output dedicated port. The serial communication circuit 512 is a circuit that performs asynchronous serial communication in input / output to the outside.

The address decoding circuit 514 is a circuit for decoding each functional block inside the main control unit 41 and decoding a chip select signal which is a decoding signal for an external device. The chip select signal enables the internal circuit of the main control unit 41 or an external device serving as a peripheral device to be selectively and effectively operated to be accessed from the CPU 41a.

FIG. 5 is an address map of the memory area used by the main control unit 41. As shown in FIG. 5, the memory area used by the main control unit 41 includes a memory area (0000h to 7FFFh) allocated to the RAM 41c and a memory area (8000h to FFFFh) allocated to the ROM 41b.

The memory area of the RAM 41c is an internal function register area (1000h to 1000h) in which a usable area (0000h to 01FFh) that can be used as a work and a register group for controlling each function mounted on the main control unit 41 are stored. 1080h) and unused areas (0200h to 0FFFh, A800h to FFFFh) whose access is prohibited.

The memory area of the ROM 41b includes a program / data area (8000h to A6FFh) in which a program and fixed data are stored, a ROM comment area (A700h to A7FFh) in which arbitrary data such as a program title and version can be set, and a CALLV. The vector table area (A780h to A7A7h) where the start address of the instruction subroutine and the start address of the interrupt processing are set, and the HW parameter where the parameters for setting the internal functions of the main control unit 41 in terms of hardware are set. The area (addresses A7A8h to A7FFh) and an unused area (A800h to FFFFh) whose access is prohibited are included.

The parameters set in the HW parameter area include the final address (HPRGEND) of the ROM area used in the program / data area, the start address (HRAMSTAT) and the final address (HRAMEND) of the RAM area for which access is prohibited.

Then, when the main control unit 41 accesses the area between the address set in HPRGEND and A6FFh, that is, the area of the program / data area in which the program or the like is not stored, the address set in HRAMSTAT When there is access to the area between the addresses set in HRAMEND, that is, the area where access prohibition is set among the available areas, when there is access to the ROM comment area, access to the HW parameter area When there is, it is judged as unauthorized access and an illegal access reset is generated. When an illegal access reset occurs, it is controlled to a special error state described later, the progress of the game is disabled, the state shifts to the setting change state, and the setting value is not released until a new setting value is set.

In this way, the main control unit 41 accesses the program / data area in which the program or the like is not stored, or the available area in which access prohibition is set. That is, since the progress of the game is disabled by generating an illegal access reset when there is an access to a memory area that is not accessed in normal operation, it is not related to the unused area or operation of ROM 41b. Even when an illegal program is stored in an area, an unused area of the RAM 41c, or the like, it is possible to prevent the illegal program from being executed.

Further, the main control unit 41 is activated when a system reset by inputting a system reset signal, a WDT reset by WDT506b, and the above-mentioned illegal access reset occur. At this time, the value set in the vector table area is set. Is 0000h (value set in the unused vector table area), or is an area of the address set in 8000h to HPRGEND, that is, a value indicating the area in which the program or the like is actually stored in the program area. If it is determined whether or not the system exists, and the value set in the vector table area is neither 0000h nor the value indicating the area of the address set in 8000h to HPRGEND, the system is not activated.

In this way, the main control unit 41 is activated when the value set in the vector table area, that is, the start address of the subroutine of the CALLV instruction and the start address of the interrupt process are values indicating outside the area in which the program is set. By not doing so, it is possible to prevent in advance that an unintended process is executed due to an interruption or the like.

The main control unit 41 transmits various commands to the sub control unit 91 via the parallel output port 513. The command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and the command is not sent from the sub control unit 91 to the main control unit 41. Further, in this embodiment, the command is transmitted to the sub-control unit 91 via the parallel output port 513, that is, the command is transmitted as a parallel signal, but the command is transmitted via the serial communication circuit 512. A configuration in which a command is transmitted to the sub control unit 91, that is, a configuration in which the command is transmitted as a serial signal may be used.

Further, the main control unit 41 inputs the detection states of various switches connected to the game control board 40 from the parallel input port 511. Then, the main control unit 41 executes a basic process of gradually shifting according to the detection states of the various switches input from the parallel input ports 511. Further, the main control unit 41 can interrupt the basic process and execute the interrupt process when the interrupt occurs. In this embodiment, when a timeout occurs in the timer circuit 509, that is, the timer interrupt process (main) described later is executed at regular time intervals (about 0.56 ms in this embodiment). Further, the main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, priority is given according to a predetermined order. The interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process ends, a new interrupt will occur at that point. It will be.

As a basic process, the main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes, and responds to the change in the detection state of the various switches. Execute the process of gradual migration. Further, the main control unit 41 executes the timer interrupt process (main) at regular time intervals (about 0.56 ms in this embodiment). The execution interval of the timer interrupt process (main) is set to be longer than the total time of the time in which the process repeated according to the control state in the basic process completes and the execution time of the timer interrupt process (main). This means that the process of repeating the timer interrupt process (main) between this time and the next time according to the control state always completes at least one cycle.

A liquid crystal display 51, an effect LED 52, speakers 53, 54, a reel LED 55, and other effect devices are connected to the effect control board 90, and these effect devices are sub-controls described later mounted on the effect control board 90. It is driven based on the control by the unit 91. In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, the effect LED 52, the speakers 53, 54, and the reel LED 55. However, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board separately from the sub control unit 91, and the sub control unit 91 is based on a command from the main control unit 41. The output pattern of the effect device may be determined, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be used. The output of the effect device is controlled by both units. Further, in this embodiment, the liquid crystal display 51, the effect LED 52, the speakers 53, 54, and the reel LED 55 are illustrated as the effect device, but the effect device is not limited to these, and for example, a mechanically driven display is used. A device or a mechanically driven role object may be applied as a directing device.

The effect control board 90 is composed of a microcomputer provided with a sub CPU 91a, ROM 91b, RAM 91c, and I / O port 91d, and is a liquid crystal display connected to the effect control board 90 and the sub control unit 91 that controls the effect. From the display control circuit 92 that controls the display of 51, the effect LED 52, the LED drive circuit 93 that controls the drive of the reel LED 55, the audio output circuit 94 that controls the audio output from the speakers 53, 54, when the power is turned on, or from the sub CPU 91a. Reset circuit 95 that gives a reset signal to the sub CPU 91a when the initialization command of is not input for a certain period of time, switch detection circuit 96 that detects the detection signal input from the switches connected to the effect control board 90, date information and time. The power supply voltage supplied to the clock device 97 and the slot machine 1 that output time information including information is monitored, and when a voltage drop is detected, a voltage drop signal indicating that effect is output to the sub CPU 91a. The detection circuit 98, other circuits, etc. are mounted, and the sub CPU 91a receives a command transmitted from the game control board 40, performs various controls for performing the effect, and is mounted on the effect control board 90. It controls each part of the control circuit directly or indirectly.

In the game control board 40, the reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that gives the system reset signal to the main control unit 41, and the sub control unit 91 controls the main control when the power is turned on. It is designed to start at an earlier stage than the unit 41. On the other hand, the power failure detection circuit 98 is set to have a lower voltage for outputting the voltage drop signal than the power failure detection circuit 48 for outputting the voltage drop signal to the main control unit 41 on the game control board 40, and is set to have a lower voltage when the power is cut. The sub control unit 91 detects a power failure at a stage later than that of the main control unit 41, and performs a power failure process (sub) described later.

Like the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. , Executes command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 generates an interrupt every time the number of input of the system clock reaches a certain number, that is, every fixed time interval (about 2 ms), and executes a timer interrupt process (sub) described later. Further, unlike the main control unit 41, the sub control unit 91 interrupts the process when an interrupt occurs based on the reception of a command, even if the timer interrupt process (sub) is being executed. The command reception interrupt process is executed in, and even if the interrupt that triggers the timer interrupt process (sub) occurs at the same time, the command reception interrupt process is executed with the highest priority. Further, the backup power supply is also supplied to the sub control unit 91 at the time of a power failure, and the data stored in the RAM 91c is held while the backup power supply is supplied.

In the slot machine 1 of this embodiment, the medal payout rate changes according to the set value. More specifically, the medal payout rate is changed by using the winning probability according to the set value in the lottery that affects the advantage to the player such as the internal lottery, the navigation stock lottery, and the additional lottery described later. The set value is composed of 6 stages from 1 to 6, with 6 having the highest payout rate, and the smaller the value in the order of 5, 4, 3, 2, 1 the lower the payout rate. That is, when 6 is set as the set value, the advantage is highest for the player, and the smaller the value in the order of 5, 4, 3, 2, 1 is, the lower the advantage is.

In order to change the set value, it is necessary to turn on the power of the slot machine 1 after turning on the setting key switch 37. When the power is turned on with the setting key switch 37 in the ON state, the setting value read from the RAM 41c is displayed as a display value on the setting value display 24, and the setting value can be changed by operating the reset / setting switch 38. Move to the changed state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated by 1 (when the setting value 6 is further operated, the setting value is changed to 1). Return). Then, when the start switch 7 is operated, the display value is fixed as the set value. Then, when the setting key switch 37 is turned off, the confirmed display value (set value) is stored in the RAM 41c of the main control unit 41, and the game shifts to a state in which the game can proceed.

It should be noted that when the power is turned on while the setting key switch 37 is ON, the setting shift state is also provided on the condition that the door open detection switch 25 detects the opening of the front door 1b. Well, with such a configuration, it is possible to prevent the setting from being changed illegally when the front door 1b is not opened. Further, in the configuration of shifting to the setting change state on condition that the detection corresponding to the opening of the front door 1b is performed, the door opening detection switch 25 corresponds to the opening of the front door 1b after shifting to the setting change state. It is preferable to maintain the setting change state even if the setting change state is not detected. Therefore, even if the front door 1b is temporarily closed during the setting change, the operation for shifting to the setting change state again is performed. It is not necessary and the setting change operation is not complicated. Further, when the setting key switch 37 is turned off after the start switch 7 is operated to confirm the set value after shifting to the setting change state, the door open detection switch 25 detects the front door 1b to be opened. On the condition that the setting is changed, the setting change state may be terminated and the game may proceed to a state in which the game can proceed. Even in such a configuration, the front door 1b is illegally opened. It is possible to prevent the setting from being changed.

Further, in order to confirm the set value, the setting key switch 37 may be turned on after the game is finished and the bet number is not set. When the setting key switch 37 is turned on in such a situation, the setting value display 24 displays the setting value read from the RAM 41c, so that the setting value can be confirmed. In the setting confirmation state, the progress of the game is impossible, and by turning off the setting key switch 37, the setting confirmation state ends and the game returns to a state in which the progress is possible.

After the game is over, when the setting key switch 37 is turned on while the number of bets is not set, it is a condition that the door opening detection switch 25 detects the opening of the front door 1b. In addition, a configuration that shifts to the setting confirmation state may be used, and such a configuration can prevent the setting value from being illegally confirmed when the front door 1b is not opened. Further, in the configuration of shifting to the setting confirmation state on the condition that the detection corresponding to the opening of the front door 1b is performed, the door opening detection switch 25 corresponds to the opening of the front door 1b after shifting to the setting confirmation state. It is preferable to maintain the setting confirmation state even if the detection is not performed. Therefore, even if the front door 1b is temporarily closed during the setting confirmation, the operation for shifting to the setting confirmation state again is performed. It is not necessary and the setting confirmation operation is not complicated. Further, when the setting key switch 37 is turned off after the start switch 7 is operated to confirm the set value after shifting to the setting confirmation state, the door open detection switch 25 detects the front door 1b to be opened. On the condition that the setting is confirmed, the setting confirmation state may be terminated and the game may be returned to the state in which the game can proceed. Even in such a configuration, the front door 1b is illegally opened. It is possible to prevent the set value from being confirmed.

In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not a voltage drop signal from the power failure detection circuit 48 is detected each time the timer interrupt process (main) is executed. When the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process, the power failure process (main) for setting the data for determining whether the data in the RAM 41c is normal or not at the next return is performed. Execute.

Then, the main control unit 41 returns the processing state of the main control unit 41 to the state before the power failure based on the data stored in the RAM 41c, provided that the data in the RAM 41c is normal at the time of its activation. However, when the RAM 41c data is not normal, it is determined that the RAM is abnormal, the RAM abnormality error code is set in the register to control the RAM abnormality error state, and the progress of the game is disabled.

The error state shifts to the normal error state that is canceled by the reset operation (operation of the reset / setting switch 38 or the reset switch 23) and the setting change state described above, and is canceled until a new setting value is set. The RAM error state is a special error state, including the special error state without, and once controlled to the RAM error error state, it shifts to the setting change state and is released until a new setting value is set. Will not be done.

Further, the sub control unit 91 also determines whether or not the voltage drop signal from the power interruption detection circuit 98 is detected in the timer interrupt process (sub), and when it is determined that the voltage drop signal is detected, the sub control unit 91 also determines. At the next return, the power interruption process (sub) for setting the data for determining whether the data in the RAM 91c is normal is executed.

Then, the sub-control unit 91 returns the processing state of the sub-control unit 91 to the state before the power failure based on the data stored in the RAM 91c, provided that the data in the RAM 91c is normal at the time of its activation. However, when the data in the RAM 91c is not normal, it is determined that the RAM is abnormal, and the RAM 91c is initialized. In this case, unlike the main control unit 41, the RAM 91c is only initialized, and the execution of the effect is not disabled.

Further, even if it is determined that the data in the RAM 91c is normal at the time of its activation, the sub control unit 91 is activated when it receives a setting command described later indicating that the setting has been changed from the main control unit 41. The RAM 91c is initialized even when neither the return command nor the setting command, which will be described later, indicating that the control state of the main control unit 41 has been restored is received even after a certain period of time has elapsed. In this case as well, only the RAM 91c is initialized, and the execution of the effect is not disabled.

Next, the initialization of the RAM 41c of the main control unit 41 will be described. The usable area of the storage area of the RAM 41c of the main control unit 41 is divided into an important work, a special work, a general work, an unused area, and a stack area, and the important work, the special work, the general work, and the unused area. , The stack area is arranged in this order.

In this embodiment, the main control unit 41 displays the data of the RAM 41c when the setting key switch 37 is started when the setting key switch 37 is ON and the data of the RAM 41c is destroyed when the setting key switch 37 is started. From 6 when it is not destroyed, when the data of RAM 41c is destroyed at the time of starting with the setting key switch 37 ON, at the end of setting change, at the end of a specific game state, at the end of one game When the initialization condition is satisfied, four types of initialization with different regions to be initialized are performed according to each initialization condition.

Initialization 0 is when the data in the RAM 41c is destroyed when the setting key switch 37 is started up in the OFF state, or when the data in the RAM 41c is destroyed when the setting key switch 37 is started up in the ON state. In initialization 0, all the usable areas are initialized. The initialization 1 is the initialization performed when the data of the RAM 41c is not destroyed at the time of starting with the setting key switch 37 ON, and in the initialization 1, other than the important work and the special work in the usable area. Area is initialized. The initialization 2 is an initialization performed at the end of a specific gaming state, and in the initialization 2, the general work, the unused area, and the unused stack area among the usable areas are initialized. The initialization 3 is an initialization performed at the end of one game, and in the initialization 3, the unused area and the unused stack area among the usable areas are initialized. The storage area of the data indicating the set value and the game state is allocated to the special work, and when the data of the RAM 41c is not destroyed at the time of starting with the setting key switch 37 ON, that is, the data of the RAM 41c. If is normal and the setting is changed, the set value and the data indicating the game state will be retained. Further, the storage area of the timer counter, which will be described later, is allocated to the special work, and is retained without being initialized at the end of the game or the end of a specific game state.

In the slot machine 1 of the present embodiment, a specified number of bets that can be set according to the gaming state is determined, and the game is provided on the condition that the specified number of bets determined according to the gaming state is set. Can be started. In this embodiment, the winning line LN is activated when a predetermined number of bets are set according to the gaming state.

Then, in this embodiment, when all the reels 2L, 2C, and 2R are stopped, the activated winning line (in the case of this embodiment, all the winning lines are always activated, so that the following is valid. A winning line is obtained when a combination of symbols called a role is arranged on the winning line (the winning line is simply called the winning line). The combination may be a combination of the same symbols or a combination including different symbols.

The types of winning roles are determined according to the game status, but they can be broadly divided into small winning roles that involve payout of medals and re-starting the next game without the need to set the number of bets. There is a gaming role and a special role that involves a transition to a gaming state that is advantageous to the player. In the following, the small role and the replaying role will be collectively referred to as the general role. In order for each winning combination determined according to the game state to be won, it is necessary to win the internal lottery described later and set the winning flag of the winning combination in the RAM 41c. Of the winning flags for each of these winning combinations, the winning flags for the small winning combination and the replaying combination are valid only in the game in which the flags are set, and are invalid in the next game, but the winning flags for the special winning combination are , It is valid until the combinations of the allowed combinations are complete by the flag, and is invalid in the game in which the combinations of the allowed combinations are complete. That is, once the winning flag of the special role is won, even if the combination of the winning combination permitted by the flag cannot be aligned, the winning flag is not invalidated and is carried over to the next game. It becomes.

Hereinafter, the internal lottery of this embodiment will be described. In the internal lottery, before the display results of all reels 2L, 2C, and 2R are derived, whether or not the main control unit 41 allows the winning of each of the above-mentioned winning combinations (specifically, the start switch 7). Is determined at the time of detection). In the internal lottery, first, a random number value (an integer of 0 to 65535) for the internal lottery is acquired when the start switch 7 is detected. Specifically, the value generated by the random number circuit 508b and stored in the random number value register of the random number circuit 508b is set in the lottery work assigned to the RAM 41c. Then, for each winning combination determined according to the gaming state, according to the numerical data stored in the lottery work and the number of determination values of each winning combination determined according to the current gaming state, the number of bets, and the set value. It is determined whether or not to allow the prize.

In the internal lottery, the number of judgment values determined according to the winning combination, the current game state, and the set value to be the target of the internal lottery is sequentially added to the random number value for the internal lottery (numerical data stored in the lottery work). When the numbers are added and the result of the addition overflows, it is determined that the winning combination has been won. Therefore, the winning combination is won with a probability (number of determination values / 65536) according to the magnitude of the number of determination values.

Then, when the winning of any of the winning combinations is determined, the winning flag corresponding to the winning combination is set in the internal winning flag storage work assigned to the RAM 41c. The internal winning flag storage work is composed of a 2-byte storage area, in which the upper byte is assigned as the special role storage work in which the winning flag of the special combination is set, and the lower byte is the winning of the general combination. It is assigned as a general role storage work for which a flag is set. Specifically, when the special role is won, the winning flag of the special role indicating that the special role has been won is set in the special role storage work, and the winning flag set in the general role storage work is cleared. In addition, when the general role is won, the winning flag of the general role indicating that the general role has been won is set in the general role storage work. If neither combination nor combination of combinations is won, only the general combination storage work is cleared.

Next, the stop control of the reels 2L, 2C, and 2R will be described. The main control unit 41 refers to the table index and the table creation data stored in the ROM 41b when the reel starts to rotate and when the reel stops and the reel that is still rotating remains. , Create a stop control table for each spinning reel. The stop control table is data that can specify the number of slip frames for each timing when the stop operation is performed. Then, when any operation of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to, and the referenced stop control table is slipped. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, and 2R corresponding to the operated stop switches 8L, 8C, and 8R.

In this embodiment, a value of 0 to 4 is set as the number of sliding frames, and it is possible to pull in a maximum of 4 symbols to stop the reel after detecting the stop operation. That is, the stop position of the symbol can be specified from a range of up to 5 frames including the stop operation position where the stop operation is detected. Further, since it is necessary to move one frame to move the reel for one symbol, it is possible to pull in a maximum of four symbols after detecting the stop operation to stop the reel, and stop when the stop operation is detected. The stop position of a symbol can be specified from a range of up to 5 symbols including the operation position.

In this embodiment, when any of the winning combinations is won, when the stop operation is performed, the winning winning combinations can be stopped together on the winning line within a pull-in range of up to 4 frames. If possible, control is performed to align and stop the winning combination, and control is performed to stop the winning combination without aligning it within a pull-in range of a maximum of 4 frames. If the special role and the small role are won at the same time, such as when the special role is carried over from before the previous game and the small role is won, the maximum on the winning line is when the stop operation is performed. If it is possible to align and stop the winning small wins in the pull-in range of 4 frames, control is performed to align and stop the small wins that have been won in the pull-in range of up to 4 frames on the winning line. If it is not possible to draw in, if it is possible to align and stop the winning special roles in the drawing range of up to 4 frames on the winning line, control will be performed to align and stop, and the winning combination will be stopped. Control is performed so that the four frames are stopped without being aligned within the pull-in range of four frames. That is, in such a case, the control of aligning the small winning combination on the winning line is prioritized over the special winning combination, and the special winning combination can be won only when the small winning combination cannot be drawn in. If the special role and the small role can be drawn in at the same time, only the small role will be drawn in, and the small role will not be aligned on the winning line at the same time as the special role. Also, when a special role and a small role are won at the same time, the control to align the special role on the winning line is prioritized over the small role, and only when the special role cannot be drawn in, the small role is placed on the winning line. Alignment control may be performed.

Further, in this embodiment, when the special role and the re-game combination are won at the same time, such as when the special role is carried over from before the previous game and the re-game combination is won, the stop operation is performed. At that time, control is performed so that the symbols of the re-game combination are aligned and stopped within a pull-in range of up to 4 frames on the winning line. In this case, the symbols that make up the re-game combination or the symbols that make up the re-game combination that is won at the same time are arranged within 5 symbols, that is, within 4 frames for each of the reels 2L, 2C, and 2R. Since it can be stopped at any position within the pull-in range of 4 frames, if the special role and the re-game combination are won at the same time, regardless of the operation timing of the stop switches 8L, 8C, 8R by the player. Instead, all the re-game roles will be awarded. That is, in such a case, the control of aligning the re-game combination on the winning line is prioritized over the special combination, and the re-game combination is sure to win the prize. If the special role and the re-game role can be drawn in at the same time, only the re-game role is drawn in, and the special role will not be aligned on the winning line at the same time as the re-game role.

In this embodiment, the reel stop control is performed using a stop control table that can specify the number of slip frames for each timing when the stop operation is performed. However, the stop position that can specify the stop position can be specified. A configuration that specifies the stop position from the table and stops the reel at the specified stop position, and searches for a stop position that can be stopped at the timing when the stop operation is performed without using the stop control table or stop position table. A configuration that performs stop control to specify and stop the reel at the specified stop position, stop control using the stop control table, stop control using the stop position table, and stop without using the stop control table or stop position table. A configuration in which stop control by searching and specifying a stop position may be used together, or a configuration in which a stop control table or a stop position table is partially changed to perform stop control may be used.

In this embodiment, the main control unit 41 measures the game time, which is the time elapsed from the time when the rotation of the reel is started after the start of the game, that is, the time when the rotation of the reel is started. After the end of one game, a specified number of bets are set by inserting medals, etc., and when the game start operation is performed with the game start operation enabled, the reel rotation of the previous game starts. If the game time at which counting is started from a time point is equal to or longer than the specified time (4.1 seconds in this embodiment), that is, if the specified time has elapsed from the start time of reel rotation of the previous game, no wait is generated. At that point, the rotation of the reel for the game in the game is started. On the other hand, after the end of one game, a specified number of bets are set by inserting medals, etc., and when the game start operation is performed with the game start operation enabled, the reel rotation of the previous game starts. If the game time at which the time counting is started from the time point is less than the specified time, that is, if the specified time has not elapsed from the reel rotation start time of the previous game, a wait is generated and the reel rotation is started at that time. Instead, it waits until the game time at which counting starts from the start of reel rotation of the previous game reaches the specified time, and when the specified time is reached, the rotation of the reel is started.

In this embodiment, the main control unit 41 controls to output an external output signal indicating a gaming state, an error occurrence status, and the like. These external output signals are output to hall equipment such as a hall computer via an information providing terminal board of a game store (hall) in which the external output board 1000 and the slot machine 1 are installed.

The main control unit 41 has a medal IN signal indicating the number of medals used for setting the number of bets, a medal OUT signal indicating the number of medals given to the player due to the occurrence of a prize, and a game state of RB (regular bonus). An RB signal indicating that the game is in progress, a BB signal indicating that the game state is in BB (big bonus), an RT signal indicating that RT2 is in progress, and a door opening signal indicating that the front door 1b is open, which will be described later. A setting change signal indicating that the mode has been changed to the setting change mode, an insertion error signal indicating an abnormality of the medal selector, and a payout error signal indicating an abnormality of the hopper unit 34 are output.

The external output board 1000 is provided with a relay circuit, a parallel / serial conversion circuit, terminals for each output signal, and a connector to be connected for electrically connecting to the circuit of the information providing terminal board. Among the signals output from the game control board 40, the medal IN signal, the medal OUT signal, the RB signal, and the BB signal are directly output as pulse signals to the information providing terminal board via the relay circuit. On the other hand, the door open signal, the setting change signal, the input error signal, and the payout error signal are converted into a security signal which is a serial signal that can be individually identified by the parallel serial conversion circuit to provide information. It is output to the terminal board.

Next, a command transmitted by the main control unit 41 to the sub control unit 91 will be described.

In this embodiment, the main control unit 41 gives the sub control unit 91 a number of input commands, a credit command, a game state command, an internal winning command, a reel acceleration information command, a stop operation command, a slip frame number command, and a stop. Sends multiple types of commands including commands, game end commands, winning number commands, payout start commands, payout end commands, standby commands, stop commands, error commands, return commands, setting commands, setting confirmation commands, and door commands.

The number of inserted medals command is a command that can specify the number of inserted medals, that is, the number of medals used to set the number of bets, and is a state from the end of the game (after changing the setting) to the start of the game. , Or when a medal is inserted in a state where the specified number of bets is not set, or when the MAXBET switch 6 is operated to set the number of bets, the medal is transmitted. Further, since the insertion number command is transmitted when the bet number setting operation is performed, it is possible to identify that the bet number setting operation has been performed by receiving the insertion number command. The credit command is a command that can specify the number of medals stored as credits, is a state from the end of the game (after changing the setting) to the start of the game, and in a state where a specified number of bets is set. Sent when a medal is inserted and credits are added.

The game state command is a command that can specify the game state of the game, and is transmitted when the start switch 7 is operated to start the game. The internal winning command is a command that can specify the internal lottery result, and is transmitted when the start switch 7 is operated to start the game and after the game state command is transmitted. Since the game status command and the internal winning command are transmitted when the start switch 7 is operated and the game starts, it is possible to identify that the start switch 7 is operated and the game has started by receiving these commands. Is.

The reel acceleration information command is a command that can specify that the rotation of the reel starts as the game progresses, and is transmitted when the rotation of the reel starts as the game progresses. The stop operation command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, or the area number of the stop operation position of the corresponding reel, and is used for the stop operation of each reel. It is transmitted every time the accompanying stop control is performed. The number of sliding frames command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and the number of sliding frames that move from the stop operation of the corresponding reel to the stop. Therefore, each time the stop control associated with the stop operation of each reel is performed, the corresponding stop operation command is transmitted and then transmitted. The stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, or the area number of the stop position of the corresponding reel, and is a stop control associated with the stop operation of each reel. Is sent after the corresponding slip frame count command is sent each time. The stop operation command, the number of sliding frames command, and the stop command can all specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and are accompanied by the stop operation of each reel. Since it is transmitted every time the stop control is performed, it is possible to specify that the stop operation of any of the reels has been performed and the reel to be stopped by receiving these commands.

The game end command is a command that can specify that the game has ended, and is transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch. The winning number command is a command that can specify the combination of symbols aligned on the winning line LN, the presence or absence of winning, the type of winning, and the number of medals to be paid out at the time of winning, so that the player stops the third stop reel. It is when the stop switch is pressed and the stop switch is released, and is transmitted after the game end command is transmitted. Both the game end command and the winning number command are transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch. Therefore, by receiving these commands, It is possible to identify that all the operations necessary for advancing one game have been completed.

The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals by winning a prize or settlement of credits (including the medal used for setting the number of bets) is started. The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning a prize and settlement of credits is completed.

The standby command is a command indicating that the game shifts to the standby state, and when the game shifts to the standby state after the estimated end time (60 seconds in this embodiment) elapses without setting the number of bets after one game ends, credits It is sent after the payout of medals (including the medals used to set the bet number) is completed and the payout end command is sent.

The stop command is a command indicating the occurrence or release of the stop state, and after the end of the BB, when the ending effect waiting time elapses, the stop command indicating the occurrence of the stop state is transmitted, and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted. An error command is a command that indicates the occurrence or cancellation of an error state and the type of error state. When an error is determined and controlled to an error state, an error command indicating the occurrence of an error state and its type is sent and reset. When the operation is performed and the error state is cleared, an error command indicating the error state is cleared is sent.

The return command is a command indicating that the main control unit 41 has returned to the control state before the power failure, and is transmitted when the main control unit 41 returns to the control state before the power failure. The setting command is a command that indicates the start or end of the setting change state and the setting value after the setting change. When the setting change state is entered, the setting command indicating the start of the setting change state is sent, and when the setting change state ends, the setting command is sent. A setting command indicating the end of the setting change state and the setting value after the setting change is sent. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it is possible to specify that the control state of the main control unit 41 has been initialized by the setting command indicating the start of the setting. .. The setting confirmation command is a command that indicates the start or end of the setting confirmation state. A setting confirmation command that indicates the start of the setting confirmation is sent when shifting to the setting confirmation state, and a setting that indicates the end of the setting confirmation when the setting confirmation state ends. A confirmation command is sent.

The door command is a command indicating the detection state of the door open detection switch 25, that is, ON (open state) / OFF (closed state), and the command queue is empty when a predetermined condition is satisfied (normal time command transmission processing is executed). At some point) it will be sent.

Of these commands, commands other than the door command are generated in the main process, temporarily stored in the command queue provided in the RAM 41c, and then the timer interrupt process (main) normal command transmission process and power failure command transmission. Sent in the process. On the other hand, the door command is generated when no command is stored in the command queue in the normal command transmission process, is temporarily stored in the command queue provided in the RAM 41c, and is transmitted in the normal command transmission process. To.

Next, the control of the effect executed by the sub control unit 91 based on the command transmitted by the main control unit 41 to the sub control unit 91 will be described. When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

In the timer interrupt processing (sub), the sub control unit 91 determines whether or not an unprocessed command is stored in the reception buffer, and if an unprocessed command is stored, the earliest of them. The control pattern table stored in the ROM 91b is referred to based on the command received in the step, and the liquid crystal display 51, the effect LED 52, the speakers 53, 54, the reel LED 55, etc. are referred to based on the control contents registered in the control pattern table. Controls the output of various production devices. In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED 55, etc. are displayed for each of the plurality of types of effect patterns. The control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 of the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among them, the control pattern corresponding to the type of the received command is referred to, and the output control of the effect device is performed based on the control pattern. As a result, the effect according to the effect pattern and the progress of the game is executed.

If the sub-control unit 91 receives a new command during the execution of the effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and the newly received command is used. An effect based on the corresponding control pattern is executed. That is, even if the production is not completed to the end, when a new command is received, the production that was being executed is canceled and a new production is performed unless the new command received is not the command that triggers the new production. The effect based on the command will be executed.

When the internal winning command is received, the effect pattern is selected at a selection rate according to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub-control unit 91 receives the internal winning command, it is stored in the effect table according to the result of the internal lottery indicated by the internal winning command. The registered selection rate is referred to, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Therefore, even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received, and as a result, different effects may be performed depending on the effect pattern.

Further, whether the sub-control unit 91 has changed the detection state of the door open detection switch 25 from OFF (closed state) to ON (open state) based on the detection state of the door open detection switch 25 specified from the door command. When it is determined whether or not the door is open and the state changes from OFF (closed state) to ON (open state), a door opening notification is executed to notify that the front door 1b is being opened.

Next, various control contents executed by the main control unit 41 in this embodiment will be described below with reference to FIGS. 6 to 18.

When the main control unit 41 is activated due to the occurrence of a reset, the main control unit 41 sets the startup time. In the startup setting, the status flag provided in the main control unit 41 is initialized. The status flag is data that holds the state of the operation result and the execution result of the instruction, and particularly includes the interrupt master permission flag that sets the prohibition / permission of interrupt. Since the initial value of the interrupt master permission flag is a value indicating that interrupts are prohibited, the main control unit 41 is started in a state where interrupts are prohibited.

After that, the main control unit 41 sets various functions with reference to the HW parameters, and then performs the initial setting process shown in the flowchart of FIG. 6 according to the program stored in the program / data area. In the initial setting process, first, interrupting is prohibited by setting the value of the interrupt master permission flag to a value indicating interrupt prohibition (Sa1). As described above, the main control unit 41 is activated in the interrupt-prohibited state, but in Sa1, interrupts are prohibited again. Next, initialization data is set (Sa2), and each output port including the parallel output port 513 is initialized (Sa3). Next, the built-in register is set (Sa4).

Next, it is determined whether or not the power supply voltage is normal (Sa5). If the power supply voltage is not normal, the determination is repeated until it becomes normal. If the power supply voltage is normal, the upper address of the interrupt vector is set (Sa6). Then, access to the RAM 41c is permitted (Sa7), and the stack pointer is initialized (Sa8).

Next, the RAM parity is calculated (Sa9). Then, it is determined whether or not the calculated RAM parity becomes 0 (Sa10). If the RAM parity does not become 0, the process proceeds to the step of Sa13, and the destruction diagnosis data is cleared (Sa13). On the other hand, when the RAM parity becomes 0, the destruction diagnosis data is acquired from the RAM 41c (Sa11), it is determined whether or not the acquired destruction diagnosis data is correct (Sa12), and the destruction diagnosis data is cleared. (Sa13).

Next, it is determined whether or not the setting key switch 37 is in the ON state (Sa14). When the setting key switch 37 is in the ON state, the timer interrupt is set (Sa19). Specifically, the register of the timer circuit 509 built in the main control unit 41 is set so that the timer interrupt is executed periodically at predetermined time intervals. In this embodiment, the value corresponding to about 0.56 ms is set in a predetermined register (time constant register), so that the timer interrupt is periodically generated every about 0.56 ms. Further, in the timer circuit 509, the timer is initialized by setting the register, and the time counting is started from the initial value. When the timer interrupt setting in the step of Sa19 is completed, the process shifts to the setting change process.

On the other hand, when the setting key switch 37 is in the OFF state, it is determined whether or not the stored contents of the RAM 41c are destroyed (Sa15). In the step of Sa15, it is determined whether or not the RAM abnormality flag described later is set, and whether or not the stored contents of the RAM 41c are destroyed based on the determinations of Sa10 and Sa12. If the stored contents of the RAM 41c are not destroyed, a return command is transmitted to the sub-control unit 91 (Sa16). When the stored contents of the RAM 41c are not destroyed, it is determined that the RAM abnormality flag is not set and the RAM parity is 0 in the step of Sa10, and the destruction diagnosis data is further stored in the step of Sa12. This is the case when it is determined to be correct.

After the step of Sa16, all the registers are restored (Sa17), and the timer interrupt is set in the same manner as in the step of Sa19 (Sa18). Then, the process proceeds to the Sd24 process of the timer interrupt process (main) described later. As a result, the process that was executed before the power failure is restored.

If the stored contents of the RAM 41c are destroyed in the step of Sa15, the start address (0000h) of the RAM is set in the register (Sa20), and the specified address is reached to the final address of the usable area (0FFFh). Initialize the region, that is, all regions of the usable region (Sa21).

Next, a RAM abnormality flag indicating that the stored contents of the RAM 41c are not normal is set in the RAM 41c (Sa22), and the process proceeds to error processing. In error handling, the progress of the game is disabled. Further, in the error state in which the RAM abnormality flag is set and the transition is made, the setting key switch 37 is turned on and the power switch 39 is turned on, so that the error state can be canceled by shifting to the setting change processing. On the other hand, when the power switch 39 is turned on without turning on the setting key switch 37, the RAM error flag is still set and an error state occurs again.

Next, the setting change process executed by the main control unit 41 will be described.

As shown in FIG. 7, the main control unit 41 first sets the start address (0000h) of the RAM in the register (Sb1). Next, it is determined whether or not the stored contents of the RAM 41c are destroyed in the same manner as in the step of Sa15 shown in FIG. 6 (Sb2). If the contents of the RAM are not destroyed, that is, if the contents of the RAM are not abnormal, the start address of the RAM to be initialized at the start of setting change is set in the register (Sb3). That is, the address set in Sb1 is changed. If the contents of the RAM are destroyed, that is, if the contents of the RAM are abnormal, the process proceeds to step Sb4.

Next, the area from the address specified in the step of Sb1 or Sb3 to the final address of the usable area is initialized (Sb4). Since the start address of the RAM is set in the step of Sb1, in this case, all the usable areas are initialized in the step of Sb4. On the other hand, in the step of Sb3, the start address of the RAM to be initialized at the start of setting change is set. Therefore, in this case, in the step of Sb4, the areas other than the important work and the special work are initialized. Will be done.

Next, a setting command indicating the start of the setting change state is transmitted to the sub control unit 91 (Sb5) to allow interruption (Sb6).

Next, it is determined whether or not the reset / setting switch 38 has changed from OFF to ON (Sb7). When the reset / setting switch 38 changes from OFF to ON, the set value of the register is updated (1 is added for 1 to 5 and 1 is updated for 6) (Sb8). If the reset / setting switch 38 does not change, it is determined whether or not the start switch 7 has changed from OFF to ON (Sb9). If the start switch 7 does not change, the process returns to the step of Sb7. On the other hand, when the start switch 7 changes from OFF to ON, it is determined whether or not the setting key switch 37 is in the OFF state (Sb10). If the setting key switch 37 is not in the OFF state, the determination is repeated until the setting key switch 37 is in the OFF state. When the setting key switch 37 is OFF, the data of the set value set in the register is stored in the RAM 41c (Sb11).

Next, a setting command indicating the end of the setting change state is transmitted to the sub control unit 91 (Sb12). Then, the start address of the initialization target RAM at the end of the setting change is set in the register (Sb13), and the process proceeds to the main process.

Next, the main process executed by the main control unit 41 will be described. The main process is repeatedly executed for each unit of game. Then, one cycle of the main process corresponds to one unit of the game.

As shown in FIG. 8, the main control unit 41 first prohibits interruption (Sc1). Next, the final address of the RAM to be initialized is set (Sc2).

Next, the RAM area indicated by the specified address is cleared (Sc3). At this time, if the main process is started after the setting change process, the start address of the initialization target RAM at the end of the setting change is set, and in the Sc2 step, the final address of the initialization target RAM at the end of the setting change ( Since 0FFFh) is set, the areas other than the important work and the special work among the usable areas are initialized. Further, at the end of the game, which is not the end of the specific game state, the start address of the RAM to be initialized at the end of the game is set in the Sc10 step described later, and in the Sc2 step, the address indicated by the stack pointer as the final address. Is set, the general work, the unused area, and the unused stack area among the usable areas are initialized. Further, at the end of the specific game state and at the end of the game, the start address of the RAM to be initialized at the end of the specific game state is set in the Sc11 step described later, and the final address in the Sc2 step. Since the address indicated by the stack pointer is set as, the unused area and the unused stack area of the usable area are initialized.

After the RAM is initialized in the step of Sc3, the interrupt is permitted (Sc4), and the game start waiting process is executed (Sc5). In the game start waiting process, a process of waiting in a state in which the bet number can be set, setting a predetermined number of bets according to the game state, and starting the game when the start switch 7 is operated is executed.

Next, the internal lottery process is executed (Sc6). In the internal lottery process, whether to allow the above-mentioned winning of each winning combination based on the random number value for the internal lottery latched at the same time as the game starts by the detection of the start switch 7 in the step of Sc5 (that is, the derivation of the display result is derived. Performs the process of deciding whether or not to allow it.

Next, the reel control process is executed (Sc7). In the reel control process, the process of rotating each reel 2L, 2C, 2R in response to the operation of the start switch 7, the result of the internal lottery in the step of Sd2, and the operation of the stop switches 8L, 8C, 8R by the player are detected. A process of stopping the rotation of the corresponding reels 2L, 2C, and 2R is executed according to the fact.

Next, the game end setting process is executed (Sc8). In the game end setting process, when it is determined that the rotation of all reels 2L, 2C and 2R has stopped in the Sc7 process, a prize is generated according to the display result derived for each reel 2L, 2C and 2R. The process of determining whether or not it is executed is executed. Then, when it is determined that a prize has been generated, credits are added and medals are paid out based on the number of payouts according to the prize. When a prize is won, a process of setting the game state is executed in preparation for the next game after the payout of medals and the like is completed. Further, if no winning is generated, after the reels are stopped, a process of setting the game state is executed in preparation for the next game.

When the game end time setting process is completed, it is determined whether or not it is the end of a specific game state (Sc9), and if it is not the end of the specific game state, the start address of the initialization target RAM at the end of the game is set. Set (Sc10) and return to the Sc1 step. If it is the end of the specific gaming state, the start address of the initialization target RAM at the end of the specific gaming state is set (Sc11), and the process returns to the Sc1 step.

In the main process, a command storage process that generates a command according to the progress of the game and sets it in the command queue is executed, and the set command is executed in the subsequent timer interrupt process (main) during normal operation. It is transmitted to the sub-control unit 91 by the command transmission process.

9 and 10 are flowcharts showing the control contents of the timer interrupt process (main) executed by the main control unit 41 interrupting the basic process (mainly the main process) at regular intervals (intervals of about 0.56 ms). is there. The timer interrupt process (main) is a process executed by an interrupt generated according to the count of the timer circuit 509, and the address in which the timer interrupt process (main) program is stored is a vector table. It is set as a value corresponding to the timer interrupt of. Then, when the timer interrupt occurs, the process from the address is executed. In addition, other interrupts are automatically prohibited during the execution period of the timer interrupt process (main).

As shown in FIG. 9, in the timer interrupt process (main), first, the register in use is saved in the stack area (Sd1).

Next, a power failure determination process is performed (Sd2). In the power failure determination process, it is determined whether or not a voltage decrease signal has been input from the power failure detection circuit 48, and if the voltage decrease signal has been input, whether or not the voltage decrease signal has been input even in the previous power failure determination process. If a voltage drop signal is input even in the previous power failure determination process, it is determined that there is a power failure, and a power failure flag indicating that is set.

After the power failure determination process in the step of Sd2, it is determined whether or not the power failure flag is set (Sd3), and if the power failure flag is not set, the process proceeds to Sd4 and the detection data of various switches are detected from the input port. Performs port input processing. On the other hand, when the power cut flag is set, after executing the power cut command transmission process for transmitting various commands set in the command queue to the sub control unit 91, the process shifts to the power cut process (main). ..

Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sd5). In the step of Sd5, 1 is added when the branch counter value is 0 to 2, and the value is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0 ... Each time the timer interrupt process (main) is executed.

Next, it is determined whether it is 2 or 3, that is, timer interrupt 3 or timer interrupt 4 by referring to the branch counter value (Sd6), and if it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt. In the case of 1 or the timer interrupt 2, the motor phase signal output process for outputting the phase signal data of the reel motors 32C, 32C, 32R is executed (Sd7).

Next, it is determined whether or not it is 1 by referring to the branch counter value, that is, whether or not it is timer interrupt 2 (Sd8), and if it is not timer interrupt 2, that is, if it is timer interrupt 1, the reel motor Reel start processing (Sd9) that controls the step time interval at the start of 32L, 32C, 32R, motor step processing (Sd10) that changes the phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C , 32R is stopped, and after a certain period of time has elapsed, the motor phase signal standby process (Sd11) for changing the phase signal to one-phase excitation is sequentially executed, and then the process proceeds to the step of Sd24.

Further, when it is determined in the step of Sd8 that the timer interrupt is 2, the LED dynamic display process (Sd12) for dynamically lighting various indicators, and the control for outputting data such as lighting signals of various LEDs to the output port. Signal output processing (Sd13), time counter update processing for updating various time counters (Sd14), door monitoring processing for monitoring the detection status of the door open detection switch 25, door monitoring processing for requesting transmission of door commands (Sd15), command queue After sequentially executing the normal command transmission process (Sd16) for transmitting various commands set to to the sub-control unit 91 and the external output signal update process (Sd17) for updating the external output signal, the process proceeds to the step of Sd24.

Further, when it is determined in the step of Sd6 that the timer interrupt is 3 or the timer interrupt 4, it is further determined whether or not the branching counter value is 3, that is, whether or not the timer interrupt is 4 (Sd18). If it is not the timer interrupt 4, that is, if it is the timer interrupt 3, the origin passage process (Sd19) for checking the origin passage (passage of the reel reference position) of the rotating reels 2L, 2C, and 2R, and the switches After sequentially executing the switch input determination process (Sd20) for determining whether or not the detection state has changed, the process proceeds to the step of Sd24.

Further, when it is determined in the step of Sd18 that the timer interrupt is 4, the stop switch process (Sd21) for determining the stop position according to the detection of the stop switches 8L, 8C, 8R, and the two phases when it is time to stop. After sequentially executing the stop process (Sd22) for starting the brake by excitation and the final stop process (Sd23) for three-phase excitation after a certain time from the start of the brake in the stop process, the process proceeds to the step of Sd24.

In the step of Sd24, the register saved in the stack area in Sd1 is restored, and the process returns to the process before the interrupt.

As described above, in this embodiment, the main control unit 41 is started in the interrupt-prohibited state when a reset occurs, and is interrupted by the program at the start of the initial setting process to be executed for the first time thereafter. The prohibition is performed, and even if the main control unit 41 is activated in a state where the interrupt is not prohibited for some reason, it is possible to prevent an unintended interrupt from occurring.

Further, after the main control unit 41 is activated, after setting the timer interrupt in the timer circuit 509, the interrupt is permitted, and the interrupt occurs in a state where the timer interrupt does not operate normally. It can be prevented from being interrupted. Further, in the timer circuit 509, the timer is initialized by setting the timer interrupt, and the time counting is started from the initial value, and the time from the start until the first interrupt occurs. The timer interrupt can be generated at regular time intervals without any deviation from the time until the second and subsequent interrupts occur. Further, the main control unit 41 updates the setting of the timer circuit 509 to the initial value by the program in the initial setting process, and the setting of the timer circuit 509 is rewritten for some reason at the time of startup. Even if there is, it is possible to prevent an unintended interruption from occurring.

Further, if the setting key switch 37 is in the ON state at the time of activation, the main control unit 41 shifts to the setting change processing, and initializes the RAM 41c at the start of the setting change processing. At this time, if the data in the RAM 41c is normal, by holding the important work and the special work and initializing the other areas, the control state (set value, game state, etc.) before the change is maintained even after the setting is changed. While a part can be retained, if the data in RAM 41c is not normal, by initializing all the usable areas including important work and special work, the data in RAM 41c can be surely abnormal. It can be resolved.

Further, since the RAM abnormality flag is set in the main control unit 41 when the RAM abnormality is determined, the RAM parity is 0 when the power is turned off again after the RAM abnormality error occurs and the power is turned on again. Therefore, even when the destruction diagnosis data is determined to be normal, it is possible to determine whether or not the data in the RAM 41c is destroyed based on the RAM abnormality flag.

Further, after the setting change processing is completed, the main control unit 41 executes a main process for stepwise processing according to the progress of the game for each game unit. Further, in the main process, the RAM 41c is initialized for each game unit, and the RAM 41c is also initialized at the end of the setting change process. Then, after the setting change process is completed, the main process is started from the stage before the process of initializing the RAM 41c in the main process, and the initialization of the RAM 41c after the setting change process is completed and the game unit. Initialization of each RAM 41c can be performed by a common process.

Further, when the RAM 41c is initialized, the main control unit 41 prohibits interrupts until the initialization is completed, and the timer interrupt process (main) is performed during the execution of the initialization of the RAM 41c. When it occurs, it is possible to prevent the initialized contents from being changed or the processing performed in the timer interrupt processing (main) from being performed normally.

Further, the main control unit 41 updates the output state of the external output signal in the main process, and changes the output state of the external output signal in the subsequent timer interrupt process (main) based on the updated output state. At the same time, when updating the output status of the external output signal, interrupting is prohibited until the update is completed, and the timer interrupt processing (main) occurs before the output status of the external output signal is completed. By doing so, it is possible to prevent an external output signal indicating unintended data from being output.

The main control unit 41 of this embodiment generates a command according to the progress of the game in the above-mentioned setting change process and main process, stores the generated command in the command queue, and performs a normal time in the timer interrupt process (main). Every time the command transmission process is executed, the untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

FIG. 11 is a flowchart showing the control contents of the command storage process executed when various commands generated by the main control unit 41 are stored in the command queue. The command transmitted by the main control unit 41 is composed of two bytes, the first byte represents MODE (command classification), and the second byte represents EXT (command content). Further, the command form shown in this embodiment is an example, and other data forms may be used. Further, in this embodiment, the command is composed of a 2-byte signal, but these commands may be composed of a 1-byte signal or a 3-byte or more signal.

In the command storage process, first, MODE and EXT constituting the command to be transmitted are generated (Se1). Then, after storing the MODE and EXT of the generated command in the area of the area number indicated by the storage pointer, that is, in the free area of the command queue (Se2), 1 is added to the area number indicated by the storage pointer (Se3). Since the area number is a numerical value in the range of 0 to 31, when the serial number indicated by the storage pointer is 31, 1 is added and when it becomes 32, it is updated to 0.

Next, it is confirmed whether or not the untransmitted flag is set (Se4), and if the untransmitted flag is not set, the untransmitted flag is set (Se5). Then, it is confirmed whether or not the area number indicated by the storage pointer and the area number indicated by the transmission pointer match, that is, whether or not all the areas of the command queue are filled with untransmitted commands. If so, wait until the untransmitted command stored in the command queue is transmitted and the area number indicated by the storage pointer and the area number indicated by the transmission pointer do not match, and the area number indicated by the storage pointer. The command storage process is terminated when the area number indicated by the transmission pointer and the area number indicated by the transmission pointer do not match, that is, when the command queue becomes empty (Se6).

FIG. 12 shows the control of the normal command transmission process executed in the timer interrupt 2 of the timer interrupt process (main) described above in order for the main control unit 41 to transmit the command stored in the command queue by the command storage process. It is a flowchart which shows the content.

In the normal command transmission process, first, it is confirmed whether or not the untransmitted flag is set, that is, whether or not the untransmitted command is stored in the command queue (Sf1), and the untransmitted flag is not set. In this case, the detection state of the door open detection switch 25 is acquired, MODE and EXT constituting the door command are generated, and the generated MODE and EXT are stored in the area of the area number indicated by the storage pointer, that is, in the free area of the command queue. Store (Sf2, Sf3).

When it is determined that the untransmitted flag is set in the step of Sf1, and after the MODE and EXT constituting the door command are stored in the command queue in the steps of Sf2 and Sf3, the area indicated by the transmission pointer value of the command queue. The command stored in is transmitted to the sub-control unit 91 (Sf4 to Sf7). Specifically, first, the MODE constituting the command stored in the area indicated by the transmission pointer value of the command queue is output (Sf4), and a strobe signal for notifying the sub-control unit 91 that the command has been output is sent for a predetermined time. (In this embodiment, 10 μs) is output (Sf5). Then, the EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sf6), and the strobe signal is output again for a predetermined time (Sf7).

Next, 1 is added to the area number indicated by the transmission pointer (Sf8). Since the area number is a numerical value in the range of 0 to 31, when the area number indicated by the transmission pointer is 31, 1 is added and the area number is updated to 0 when it becomes 32. After that, it is confirmed whether the area number indicated by the transmission pointer and the serial number indicated by the storage pointer match, that is, whether the command to be transmitted is stored in the command queue (Sf9), and if they match. That is, when the command to be transmitted is not stored in the command queue, the non-transmission flag is cleared and the normal command transmission process is terminated (Sf10). On the other hand, if the area number indicated by the send pointer and the serial number indicated by the storage pointer do not match, that is, when the command to be sent is stored in the command queue, the unsent flag is maintained and the command is sent during normal operation. End the process. By maintaining the untransmitted flag, the untransmitted command left in the command queue will be transmitted in the timer interrupt process (main) from the next time onward.

The main control unit 41 of this embodiment executes a command transmission process at the time of power failure before executing the power failure process (main) when the power failure flag is set in the timer interrupt process described above. In addition to the normal command transmission process, the untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

FIG. 13 is a flowchart showing the control contents of the command transmission process at the time of power interruption, which is executed before the power interruption process (main) is performed by the main control unit 41 in the timer interrupt process (main).

In the command transmission process at the time of power failure, first, it is confirmed whether or not the untransmitted flag is set, that is, whether or not the untransmitted command is stored in the command queue (Sg1), and the untransmitted flag is set. If so, all the commands stored in the command queue are transmitted to the sub-control unit 91 (Sg1 to Sg7).

Specifically, first, the MODE constituting the command stored in the area indicated by the transmission pointer value of the command queue is output (Sg2), and a strobe signal for notifying the sub-control unit 91 that the command has been output is sent for a predetermined time. (In this embodiment, 10 μs) is output (Sg3). Then, the EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sg4), and the strobe signal is output again for a predetermined time (Sg5). After that, 1 is added to the area number indicated by the transmission pointer (Sg6). Since the area number is a numerical value in the range of 0 to 31 as in the case of adding the transmission pointer in the normal command transmission process, when the area number indicated by the transmission pointer is 31, 1 is added to obtain 32. Update to 0.

Next, it is determined whether or not the area number indicated by the transmission pointer and the serial number indicated by the storage pointer match, that is, whether or not the command to be transmitted is stored in the command queue (Sg7), and the area indicated by the transmission pointer. If the number and the serial number indicated by the storage pointer do not match, that is, when the command to be transmitted is stored in the command queue, the area number indicated by the transmission pointer and the serial number indicated by the storage pointer in the step of Sg7 The steps Sg2 to Sg7 are repeatedly executed until it is determined that they match, and all the commands stored in the command queue are transmitted to the sub-control unit 91.

Then, in the step of Sg7, when it is determined that the area number indicated by the transmission pointer and the serial number indicated by the storage pointer match, that is, all the commands stored in the command queue are transmitted to the sub-control unit 91. When no command remains in the command queue, the main control unit 41 clears the untransmitted flag (Sg8), ends the command transmission process at the time of power interruption, and shifts to the power interruption process (main).

In this way, in the normal command transmission process, one command (a set of commands consisting of 2 bytes) is sent to the sub-control unit 91 each time the normal command transmission process is executed in the timer interrupt process (main). On the other hand, in the command transmission process at the time of power interruption, all the commands stored in the command queue are sent to the sub-control unit 91 before the power interruption process (main) is performed in the timer interrupt process. Is supposed to be sent.

FIG. 14 shows a power cut process (main) executed after the power cut command transmission process when the main control unit 41 determines that the power cut flag is set in the timer interrupt process (main) described above. It is a flowchart which shows the control content.

In the power failure processing (main), first, all the registers that may be used are saved in the stack area (Sg1). Although the values of the I register and the IY register described above are used, they are not saved here because the same fixed values are always set at the time of initialization at startup.

Next, data for fracture diagnosis (5A (H) in this example) is set (Sg2). Then, all the output ports including the parallel output port 513 that outputs the command are initialized (Sg3). As a result, the output state of the output port corresponding to the last output command by the command transmission process at the time of power failure is initialized. Next, the RAM parity adjustment data is calculated and set so that the exclusive OR of all the storage areas (including the unused area and the unused stack area) of the RAM 41c becomes 0 (Sg4), and the access to the RAM 41c is performed. Prohibit (Sg5). After that, the voltage drops, the CPU 41a of the main control unit 41 stops, and the state shifts to the standby state. Then, when the voltage drops in this standby state, the main control unit 41 is internally stopped in operation, and the operation is surely stopped in the event of a power failure.

In this embodiment, as shown in FIG. 15, the reset circuit 49 of the game control board 40 has a monitoring voltage (DC + 24V) higher than the drive voltage (DC + 5V) of the main control unit 41 among the power supply voltages supplied from the power supply board 101. ) Is monitored, and when the monitoring voltage exceeds the operable voltage (main) (+ 3.5V) that enables the main control unit 41 to operate when the power is turned on, the reset signal is turned ON to the main control unit 41. After the output, when a sufficient time (sufficient time for the monitoring voltage to rise to + 24V) has elapsed for the drive voltage (DC + 5V) of the main control unit 41 to stabilize, the reset signal is turned off and the main control unit 41 is turned off. The control unit 41 is activated. On the other hand, the reset circuit 95 of the effect control board 90 has the sub control unit 91 when the reset signal is turned off by the reset circuit 49 when the power is turned on, that is, at a timing earlier than the timing when the main control unit 41 is activated. By turning off the reset signal output to the main control unit 41, the sub control unit 91 is activated at an earlier stage than the main control unit 41 when the power is turned on, and the return command or setting command (start) transmitted from the main control unit 41 is started. ) Is put on standby in a state where the sub-control unit 91 can receive.

Then, when the reset signal output by the reset circuit 49 is turned off and started, the main control unit 41 executes the above-mentioned initial setting process, and if it is possible to return to the state before the power failure, the initial setting After sending a reset command at the end of the process, the timer interrupt is permitted, and then the timer interrupt process is executed at regular intervals. Further, when the reset signal is turned off and the operation is started, the setting key switch 37 is in the ON state, the RAM 41c is initialized, and the setting change state is started without returning to the state before the power failure. , Before the timer interrupt is permitted at the end of the initial setting process, the setting command (start) is sent to the sub-control unit 91 instead of the reset command, and then the timer interrupt is permitted, and then the timer The interrupt process is executed at regular intervals. On the other hand, the sub control unit 91 starts before the main control unit 41 starts, executes and completes the initial setting process, and waits until a return command or a setting command (start) is received in a state in which the command can be received. To do.

Next, when the main control unit 41 executes the timer interrupt process (main) at regular intervals after transmitting the return command or the setting command, and executes the normal command transmission process in the timer interrupt process (main). If the command to be transmitted is not stored in the command queue, a door command is generated and transmitted based on the detection state of the door open detection switch 25. On the other hand, the sub control unit 91 starts the output control of the effect device by receiving the return command or the setting command (start).

Further, the main control unit 41 transmits a door command or the like by a normal command transmission process executed in the timer interrupt process (main), and after the main control unit 41 is started, the timer is interrupted until the end of the initial setting process. The interrupt is not permitted, and after the main control unit 41 is started, after the return command or setting command (start) is transmitted, the transmission of commands such as the door command transmitted by the normal command transmission process is permitted. It will be.

Further, as shown in FIG. 15, the main control unit 41 executes a power failure determination process in the timer interrupt process (main) based on whether or not a voltage drop signal is input from the power failure detection circuit 48. Identify the occurrence of a power outage. The power failure detection circuit 48 monitors the above-mentioned monitoring voltage (DC + 24V) higher than the drive voltage (DC + 5V) of the main control unit 41, and detects a voltage drop in which the monitoring voltage is higher than the drive voltage (DC + 5V) of the main control unit 41. Since the voltage drop signal is output when the voltage (main) (+ 20V) or less, the main control unit 41 identifies the occurrence of the power failure when the monitoring voltage becomes the voltage drop detection voltage (main) or less. .. Then, when the occurrence of the power failure is specified in the power failure determination process, the main control unit 41 executes the command transmission process at the time of the power failure, and sends all the commands stored in the command queue to the sub control unit 91. After sending, the power failure process (main) is executed.

Further, the reset circuit 49 has an operating limit voltage (main) (+ 8V) or less in which the monitoring voltage is lower than the voltage drop detection voltage (main) (+ 20V) and higher than the operable voltage (main) (+ 3.5V). As a result, the reset signal is turned on to make the main control unit 41 inoperable. The operating limit voltage (main) is the voltage drop in the time from when the power failure detection circuit 48 becomes equal to or lower than the voltage drop detection voltage (main) for detecting the occurrence of a power failure until it drops to the operation limit voltage (main). After the voltage falls below the detection voltage (main), the main control unit 41 identifies the occurrence of a power failure, executes the command transmission process at the time of the power failure, and secures the time required to execute the power failure process. Is set to.

The time required for the main control unit 41 to identify the occurrence of a power failure, execute the command transmission process at the time of power failure, and execute the power failure process after the voltage drop detection voltage (main) or less is reached. The maximum time until the main control unit 41 detects a power failure (0.56 ms because the occurrence of a power failure is specified for each timer interrupt process (main)) and the command queue in the command transmission process at the time of a power failure. The time required to transmit the maximum number of commands (32) that can be stored (40 μs for one command transmission (MODE transmission 10 μs, transmission interval 10 μs, EXT transmission 10 μs, transmission interval 10 μs), so the maximum number of transmissions is 40. × 32 = 1280 μs) and the time required for the power interruption process (main), which is the total time.

On the other hand, the power failure detection circuit 98 monitors the above-mentioned monitoring voltage (DC + 24V) higher than the drive voltage (DC + 5V) of the sub control unit 91, and the monitoring voltage is lower than the operation limit voltage (main) (+ 8V). Since a voltage drop signal is output when the voltage drop detection voltage (sub) (+ 6V) is higher than the drive voltage (DC + 5V) of the sub control section 91, the monitoring voltage of the sub control section 91 is the voltage drop detection voltage (sub). The occurrence of power failure will be identified by the following. Then, when the occurrence of the power failure is specified in the power failure determination process, the sub control unit 91 executes the power failure process (sub).

Further, the reset circuit 95 has an operating limit voltage (sub) (+ 4V) or less in which the monitoring voltage is lower than the voltage drop detection voltage (sub) (+ 6V) and higher than the operable voltage (sub) (+ 3.5V). As a result, the reset signal is turned on to make the sub control unit 91 inoperable. The operating limit voltage (sub) is the voltage drop for the time until the voltage drop detection circuit 98 detects the occurrence of a power failure after it falls below the voltage drop detection voltage (sub) until it drops to the operating limit voltage (sub). The sub control unit 91 identifies the occurrence of a power failure after the voltage becomes equal to or lower than the detection voltage (sub), and is set so that the time required to execute the power failure process is secured.

Further, in the sub control unit 91, the main control unit 41 becomes inoperable after the monitoring voltage is the operation limit voltage (main), that is, the command transmission process and the power cut process (main) at the time of power interruption by the main control unit 41 are completed. When the voltage drop detection voltage (sub) is lower than the voltage, the voltage drop signal output is used to identify the occurrence of the power failure and execute the power failure process (sub). At least the main control unit 41 Since the state in which commands can be received is maintained until the command transmission process at the time of power failure is completed, the power failure process should be executed in a state where the main control unit 41 has received all the commands transmitted by the command transmission process at the time of power failure. Can be done. Even if the timing at which the sub control unit 91 identifies the occurrence of a power failure is the timing before the main control unit 41 becomes inoperable, the command transmitted by the main control unit 41 by the command transmission process at the time of power failure is transmitted. If the configuration is such that the command can be received until the timing sufficient to receive all the commands, the main control unit 41 executes the power interruption process in the state where all the commands transmitted by the command transmission process at the time of power failure are received. can do.

As described above, the main control unit 41 of the present embodiment generates a command according to the progress of the game in the main process or the like, stores the generated command in the command queue, and performs a normal command in the timer interrupt process (main). Each time a transmission process is executed, an untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

In such a configuration, while a plurality of commands are stored in the command queue, the power supply to the slot machine 1 may be stopped and a power failure may occur, and the main control is performed when the power failure is detected by the main control unit 41. A plurality of commands have not been transmitted on the unit 41 side, the untransmitted commands are retained as they are even after the power failure, and the commands held before the power failure are transmitted to the sub control unit 91 after the power failure is restored. If transmitted, the control state on the main control unit 41 side at the time of power interruption and the time of recovery from power interruption will be different from the control state on the main control unit 41 side specified by the sub control unit 91 side.

On the other hand, in this embodiment, the main control unit 41 is stored in the command queue before executing the power interruption process (main) for returning to the control state before the power failure when the power failure is detected. Since the command transmission process at the time of power failure is executed to transmit all the commands to the sub control unit 91, the control state on the main control unit 41 side at the time of power failure and the time of recovery from power failure and the sub control unit 91 The control state on the main control unit 41 side specified on the side can be matched as much as possible.

Further, the main control unit 41 has a maximum number of commands that can be stored in the command queue during the period from when the power supply is stopped until when the power supply becomes uncontrollable at the time of power failure detection (up to 32 commands in this embodiment). Is transmitted to the sub-control unit 91, and it is longer than the period required for the power failure process (main) to be completed. Therefore, after the power failure is detected, all the commands stored in the command queue are transmitted. It is possible to reliably execute the processing up to the power interruption processing (main).

In this embodiment, the main control unit 41, which is the first control means for controlling the game, transmits a command as control information to the sub control unit 91, which is the second control means for controlling the effect. However, the first control means may be a control means other than the control of the game, for example, the control of the effect. Further, the second control means may be any control means that performs some control based on the control information transmitted from the first control means. For example, the first control means is a control means that controls the effect. In some cases, the control means that controls the effect device based on the control information transmitted from the first control means may be used as the second control means.

Further, in this embodiment, as the power interruption process (main) executed by the main control unit 41 (first control means), the RAM parity is adjusted so that the RAM parity (exclusive logical sum) of the backup area becomes 0. By setting the data and performing the process of setting the destruction diagnosis data (data other than 0), the RAM parity is 0 at the time of recovery from the power failure, and the destruction diagnosis data match, so that the data in the backup area However, if the power supply to the slot machine 1 is stopped and a power failure occurs, the control state before the power failure can be restored. A good example is that the checksum of the backup area may be set and the checksum of the backup area may be determined to be normal by matching the checksum calculated at the time of recovery from the power failure.

Further, in the present embodiment, the reset signal 49 of the game control board 40 is set to a reset signal before the monitor voltage drops below the operable voltage (main) at which the main control unit 41 becomes inoperable when a power failure occurs. Is supplied to the main control unit 41, and when a reset signal is supplied, the main control unit 41 is configured to stop all operations, that is, to be in an uncontrollable state. , The period until the reset signal is supplied and becomes uncontrollable is required for the maximum number of commands that can be stored in the command queue to be transmitted to the sub-control unit 91 and for the power interruption process (main) to be completed. Although the configuration is longer than the period, in the configuration in which the reset signal is not supplied to the main control unit 41 at the time of power failure, the monitoring voltage falls below the operable voltage (main) of the main control unit 41 until it becomes uncontrollable. Even if the period is longer than the period required to send the maximum number of commands that can be stored in the command queue to the sub-control unit 91 and complete the power cut processing (main), the power is cut off. After detection, it is possible to reliably execute the processing from the transmission of all the commands stored in the command queue to the power cut processing (main).

Further, in this embodiment, the operation limit voltage (main) for stopping the operation of the main control unit 41 when a power failure occurs is equal to or less than the voltage drop detection voltage (main) at which the power failure detection circuit 48 detects the occurrence of a power failure. After the time until the operation limit voltage (main) drops to the operation limit voltage (main) or less, the main control unit 41 identifies the occurrence of a power failure and performs a command transmission process at the time of the power failure. By setting so that the time required for execution and execution of the power failure processing is secured, the period from the occurrence of the power failure until the main control unit 41 becomes inoperable is stored in the command queue. The configuration is such that the maximum number of possible commands is transmitted to the sub-control unit 91, and the period required for the power failure processing (main) to be completed is longer than the period required for the power failure process (main) to be completed. The sub-control unit 91 can store the maximum number of commands that can be stored in the command queue for the period from when a power failure occurs until the main control unit 41 becomes inoperable by delaying the decrease in drive voltage by a capacitor, battery, capacitor, or the like. The maximum number that can be stored in the command queue is the period until the main control unit 41 becomes inoperable or the configuration is such that it is transmitted to the command and is longer than the period required for the power interruption processing (main) to be completed. The command may be sent to the sub-control unit 91, and the maximum number that can be stored in the command queue may be set so as to be longer than the period required for the power interruption processing (main) to be completed. Even with this configuration, it is possible to reliably execute the processing from the transmission of all the commands stored in the command queue to the power failure processing (main) after the power failure occurs.

Further, the main control unit 41 of the present embodiment executes the command transmission process at the time of power failure when the power failure is detected, and after transmitting all the commands stored in the command queue to the sub control unit 91, Since the power supply process (main) is executed and each output port of the parallel output port 513 including the output port that outputs the command in the power failure process (main) is initialized, the power supply is erroneously unstable. It is possible to prevent the command from being sent.

Further, the main control unit 41 of the present embodiment executes a normal command transmission process in the timer interrupt process (main), so that a predetermined number of commands stored in the storage area stored in the command queue can be executed. Since (in this embodiment, one) command is transmitted to the sub-control unit 91 every predetermined trigger (once every four timer interrupt processes (main)), a predetermined number (1 in this embodiment) is transmitted. Even if the above commands are stored in the command queue, the number of commands transmitted in one timer interrupt process (main) is limited to a predetermined number, so the commands in the normal command transmission process It is possible to prevent the other control by the main control unit 41 from being delayed due to the transmission of.

In addition, the main control unit 41 of this embodiment sets a command (internal winning command) in the command queue according to the progress of the game at a predetermined trigger (when performing a normal command transmission process executed in the timer interrupt process (main)). , Stop operation command, etc.) is not stored, and by transmitting a door command indicating the detection status of the door open detection switch 25 to the sub control unit 91, the open / closed state of the front door 1b can be changed to the sub control unit. Since 91 can be specified and the door command is transmitted when the command corresponding to the progress of the game is not stored in the command queue at a predetermined trigger, the transmission of the command according to the progress of the game is the door command. It is possible to prevent the delay due to the transmission and the delay of other controls (for example, each control in the main process) by the main control unit 41 due to the transmission of the door command.

Further, the main control unit 41 is allowed to transmit a command such as a door command transmitted by a normal command transmission process after transmitting a return command or a setting command (start) after its activation. , After the power is turned on, the door command will not be sent until the state before the power failure is restored and the return command is sent, or the setting command (start) is sent without returning to the state before the power failure. Therefore, after it is determined whether or not to restore the main control unit 41, the state of the main control unit 41 can be specified on the sub control unit 91 side, and the main control unit 41 is in the control state before the power failure. When the sub-control unit 91 receives a command in a state where it is not determined whether or not to return, it is possible to prevent an unintended operation from being performed.

In this embodiment, when no command is stored in the command queue in the normal command transmission process, a door command indicating the detection state of the door open detection switch 25 is generated and transmitted. When no command is stored in the command queue in the normal command transmission process, the operation switches (MAXBET switch 6, start switch 7, stop switch 8L, 8C, 8R) are based on the output of the switch detection circuit 44. It is possible to specify the control state on the main control unit 41 side, such as a command indicating the detection state (on / off), a command indicating the presence / absence of error detection and the type of detected error, and a command capable of specifying the game state of the game. A command may be generated and transmitted to the sub control unit 91. Even with such a configuration, the sub control unit 91 can specify the control state on the main control unit 41 side, and the game can be played. The transmission of a command according to the progress is delayed by the transmission of a command that can specify the control state of the main control unit 41, or another control by the main control unit 41 by the transmission of a command that can specify the control state of the main control unit 41. Can be prevented from being delayed.

Next, a timer counter for measuring the time interval used by the main control unit 41 for controlling the progress of the game and the like will be described with reference to FIGS. 16 and 17.

When the time counting start condition is satisfied, the main control unit 41 sets an initial value according to the time counting time as the timer value of the timer counter assigned to the RAM 41c, and periodically timers in the timer interrupt processing (main). The value is subtracted and the timer value becomes 0 to specify that the time has passed.

Specifically, when the timekeeping start condition is satisfied in the main process, the main control unit 41 sets the initial value of the timer value according to the timekeeping time in the area to which the timer counter corresponding to the condition is assigned. The set timer value is subtracted by 1 in the time counter update process of the timer interrupt process (main) until it becomes 0 about every 2.24 ms.

Then, in the main process, as shown in FIG. 16, the address of the corresponding timer counter is acquired (Si1), the acquired value is read (Si2), and it is determined whether or not the read value is not 0 (Si3). , When it is determined that the read value is 0, it is specified that the time counting time has elapsed.

As shown in FIG. 17, the timer counter used in this embodiment has an initial value of 1 byte or less, 1 byte timer A, 1 byte timer B, 1 byte timer C, and an initial value of more than 1 byte and 2 bytes or less. Includes 2-byte timer A, 2-byte timer B, 2-byte timer C, and 2-byte timer D.

The 1-byte timer is a timer for measuring a relatively short period that can be measured with a timer value of 1 byte or less. For example, an external output signal timer that measures the output period of an external output signal and an LED output update period. LED update timer to measure, stop invalid timer to measure the period from the detection of the stop operation to the activation of the stop operation again, the payout waiting to measure the period from the reel stop to the start of the payout of medals The timer, the insertion detection timer that measures the period after the ON of the insertion medal sensor 31 is detected, the insertion port detection timer that measures the period after the ON of the insertion port sensor 26 is detected, and the ON of the payout sensor 34c are detected. There are a payout detection timer that measures the period after the start of rotation, a start timer that measures the period from the start of reel rotation until the stop operation becomes effective, and the like. Of these, the stop invalid timer, the payout wait timer, and the start timer do not span the timing at which the measurement period of one game ends, but the external output signal timer, the LED update timer, the input detection timer, and the input port. The detection timer and the payout detection timer may have a measurement time by these timers that spans the timing at which one game ends.

The 2-byte timer is a timer for measuring a relatively long period that cannot be measured with a timer value of 1 byte or less. For example, a 1-game time timer that measures a specified time (about 4.1 seconds) required for 1 game. , A security signal timer that measures the minimum output period of the security signal among the external output signals, a standby time timer that measures the period from the end of the game, and a hopper empty that measures the period during which the payout sensor 34c is not detected after the hopper motor 34b is driven. There is a timer and so on. Of these, the standby time timer and the hopper empty timer do not straddle the timing at which the measurement period by these timers ends one game, but the one game time timer and the security signal timer measure the measurement time by these timers for one game. May straddle the end timing of.

In this way, the timer counter is the timing at which one game ends, that is, the timing at which a part of the RAM 41c is initialized according to the progress of the game (at the end of one game or at the end of a specific game state, a part of the RAM 41c). A timer counter that measures the measurement period that straddles the timing of initialization) and a timer counter that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game. The counter is also assigned to a special work that is not initialized at the timing according to the progress of the game.

Of these timer counters, the 1-byte timers A to C are allocated 1 byte each to the continuous 3-byte area (7E2Ch to 7E2Eh) of the RAM 41c, and the 2-byte timers A to D are the continuous 8-byte areas of the RAM 41c. Two bytes are allocated to each region (7E2Fh to 7E35h). Further, the 1-byte timers A to C and the 2-byte timers A to D are also assigned to the continuous area of the RAM 41c. In the following, the area to which the 1-byte timers A to C are allocated is referred to as a 1-byte timer group, and the area to which the 2-byte timers A to D are allocated is referred to as a 2-byte timer group. That is, both the 1-byte timer group and the 2-byte timer group are set in the area to which consecutive addresses are assigned according to a predetermined rule. The area to which consecutive addresses are assigned according to a predetermined rule is, for example, an area to which an address to be added by N (N is a natural number) from the start address and the start address is assigned.

FIG. 18 is a flowchart showing the control contents of the time counter update process.

In the time counter update process, first, the number of 1-byte timer counters to be updated (3 in this embodiment) is set as the number of 1-byte processes (Sj1), and the start address (7E2Ch) of the 1-byte timer group is set. Set the pointer (Sj2).

Next, if the 1-byte value stored in the specified address (address indicated by the pointer) is not 0, the 1-byte value of the specified address is subtracted by 1 (Sj3), and the number of processes set in the step of Sj1 is subtracted by 1. (Sj4), it is determined whether or not the number of processes after subtraction is 0 (Sj5).

If the number of processes after subtraction is not 0 in the step of Sj5, that is, if the update of all 1-byte timers is not completed, the pointer is added by 1 (Sj6), and the process returns to the step of Sj3. As a result, the pointer moves to the address of the unprocessed 1-byte timer, and if the 1-byte value of the specified address is not 0, it is subtracted.

When the number of processes after subtraction is 0 in the step of Sj5, that is, when the update of all 1-byte timers is completed, the number of 2-byte timer counters to be updated is set as the number of 2-byte processes (this embodiment). Then, 4) is set (Sj7), and the pointer is added by 1 (Sj8). As a result, the pointer moves to the start address (7E2Fh) of the 2-byte counter group.

Next, if the 2-byte value stored in the area consisting of the specified address (address indicated by the pointer) and the next address is not 0, the 2-byte value of the specified address and the next address is subtracted by 1 (Sj9), and Sj7. The number of processes set in step 1 is subtracted by 1 (Sj10), and it is determined whether or not the number of processes after the subtraction is 0 (Sj11).

If the number of processes after subtraction is not 0 in the step of Sj11, that is, if the update of all 2-byte timers is not completed, the pointer is added by 2 (Sj12), and the process returns to the step of Sj9. As a result, the pointer moves to the address of the unprocessed 2-byte timer, and if the 2-byte value of the specified address and the next address is not 0, the pointer is subtracted.

When the number of processes after subtraction is 0 in the step of Sj11, that is, when all the 2-byte timers have been updated, the processes are terminated.

As described above, in this embodiment, the value of the timer counter assigned to the RAM 41c is periodically updated, and the passage of time is specified by becoming a specific value (0). Conventionally, when measuring multiple types of time intervals, timer values are set and updated within multiple types of processing that require timekeeping, and each process is a program for updating multiple types of timer values. Since it is necessary to provide it inside, it has been a factor of increasing the program capacity. In addition, since multiple types of timer counters are assigned as data groups for each process used, it is necessary to read the values of their unrelated addresses in order to update them collectively in one process. there were.

On the other hand, in this embodiment, the area in which a plurality of types of timer counter values are stored is set in the area to which continuous addresses are assigned according to a predetermined rule of the RAM 41c, and the timer values stored in the specified addresses are set. Since the update process is repeatedly executed while changing the specified address for the area where multiple types of timer counter values are stored by adding a constant to the current specified address, multiple types of timer values are updated. , The program capacity can be reduced as compared with the case where a process of designating a plurality of types of addresses and updating the value of the address is performed in each process.

It should be noted that the process of updating the timer value stored in the specified address is repeatedly executed while changing the specified address for the area in which the multiple types of timer counter values are stored by performing a predetermined operation, thereby performing multiple types of timers. Any configuration may be used as long as the value is updated. For example, by adding a constant to the currently specified address, multiple types of timer counter values can be repeatedly executed while changing the specified address for the area where the value is stored. The timer value may be updated, or a value corresponding to the number of processes with respect to the reference address (for example, in the case of a 1-byte counter, +1 for the number of processes 1 and +2 for the number of processes 2 and the number of processes). In the case of 3, +3 ...) may be added or subtracted to update the plurality of types of timer values by repeatedly executing while changing the designated address for the area in which the plurality of types of timer counter values are stored.

Further, in this embodiment, the configuration includes seven types of timer counter values of 1-byte timers A to C and 2-byte timers A to D, but at least two or more types of timer counter values are set according to a predetermined rule of the RAM 41c. The process of updating the timer value stored in the specified address by setting the area in which consecutive addresses are assigned in is changed by performing a predetermined operation to change the specified address for the area in which multiple types of timer values are stored. However, if the configuration is such that two or more types of timer values are updated by repeatedly executing the timer values, the program capacity can be reduced as described above.

Further, for only one of the 1-byte timer and the 2-byte timer, the timer counter value is set in the area to which continuous addresses are assigned according to a predetermined rule of the RAM 41c, and the process of updating the timer value stored in the specified address is performed. A configuration may be used in which a plurality of types of timer values are updated by repeatedly executing the operation while changing the designated address for the area in which the plurality of types of timer values are stored by performing a predetermined operation.

Further, only a part of the timer counters provided in the main control unit 41 is set to the area to which continuous addresses are assigned according to a predetermined rule of the RAM 41c, and the timer value stored in the designated address is updated. A configuration may be used in which a plurality of types of timer values are updated by repeatedly executing the operation while changing the designated address for the area in which the plurality of types of timer values are stored by performing a predetermined operation.

Further, in the present embodiment, a separate timer counter is provided for each type of measurement period, but for example, one timer counter may be shared for a plurality of types of periods in which the measurement periods do not overlap.

Further, in this embodiment, as the processes executed by the main control unit 41, a timer interrupt process (main) that periodically performs a predetermined process regardless of the progress status of the game, and a timer interrupt process (main) that periodically performs the process according to the progress status of the game. The main control unit 41 sets an initial value in the timer counter when a timing condition is satisfied in the main process, including a main process that performs different processes in stages, and a plurality of types in the timer interrupt process (main). Since the timer value is updated and it is not necessary to provide a process for updating multiple types of timer values in each process constituting the main process, the program capacity for updating multiple types of timer values is reduced. be able to.

In this embodiment, the timer interrupt process (main) is executed by interrupting the main process periodically, but it is determined in advance in the timer interrupt process that is periodically performed regardless of the progress of the game. A configuration may be configured in which both the periodic processing for performing the processing and the main processing for performing different processing stepwise according to the progress of the game are performed. Even in such a configuration, the main control unit 41 is the main. By setting the initial value in the timer counter when the timing condition is satisfied in the process and updating multiple types of timer values in the periodic process, multiple types of timer values can be set in each process that constitutes the main process. Since it is not necessary to provide a process for updating, it is possible to reduce the program capacity for updating a plurality of types of timer values.

Further, in this embodiment, in the time counter update process, the value of the specified address is updated on the condition that the value of the specified address is not 0, and the timer value is updated to an abnormal value. Can be prevented.

Further, in the present embodiment, in the time counter update process, the same number of processes as the number of timer counters to be updated is set, and the process of updating the timer value is repeatedly executed for the set number of processes. In addition to facilitating the management of the number of timer counters to be updated, for example, when a plurality of types of timer counters having different update intervals are provided, the type of timer value to be updated can be arbitrarily set according to the number of processes to be set. it can.

The number of processes, that is, the number of timer counters to be updated may be set in the program, or the value set in the table may be read and set.

In addition, the timer counter to be updated last is set in advance without setting the number of processes first, and the process of updating the timer value is repeatedly executed until the address of the timer counter is reached, or the timer counter is updated at the end. A specific end value (for example, FFh) is stored at the next address of the timer counter to be used, and the process of updating the timer value is repeatedly executed until the value read from the specified address reaches the specific end value. good.

Further, in this embodiment, a 1-byte timer counter and a 2-byte timer counter are provided, and a process of updating the 1-byte timer value and a process of updating the 2-byte timer value are separately provided. Therefore, the capacity of the program and the capacity occupied by the timer value in the RAM 41c can be reduced as compared with the case where the process of updating the 1-byte timer value and the process of updating the 2-byte timer value are shared.

In this embodiment, a 2-byte timer counter is provided to measure a relatively long time corresponding to an initial value exceeding 1 byte. For example, a timer counter having a different update interval, for example, a timer Interruption processing (main) By providing a first timer counter that updates once every four times and a second timer counter that updates once every 14 times, it is relative without providing a 2-byte counter. It may be configured to measure a long time interval, and by doing so, it is not necessary to provide a process of updating the 1-byte timer value and a process of updating the 2-byte timer value, so that the timer value does not need to be provided. It is possible to reduce the program capacity related to the update of.

Further, in this embodiment, a plurality of types of timer counters are assigned to special works that are not initialized according to the progress of the game in the RAM 41c, and are not initialized according to the progress of the game. Regardless of the progress of the game, it is possible to measure the time of the period straddling the timing at which a part of the RAM 41c is initialized according to the progress of the game.

In particular, in this embodiment, not only the timer counter whose measurement period may straddle the end timing of one game, that is, the timing when a part of the RAM 41c is initialized according to the progress of the game, but also the measurement period is the game. Since the timer counter that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress is also stored in the area allocated to the special work together with the other timer counters, the timer counter can be easily managed. At the same time, the timer counter does not straddle the timing when the measurement period is partially initialized according to the progress of the game, and the timing when the measurement period is partially initialized according to the progress of the game. The usage of the timer counter can be easily changed by a later design change such as changing to a timer counter that may straddle. Further, if one timer counter is shared for a plurality of types of periods in which the measurement periods do not overlap as described above, the timing at which a part of the RAM 41c is initialized may be straddled according to the progress of the game. It is possible to measure the measurement period and the measurement period that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game with one timer counter.

Although the embodiments of the present invention have been described above with reference to the drawings, the present invention is not limited to the present invention, and even if there are changes or additions within the scope of the gist of the present invention, the present invention is included in the present invention. Needless to say.

In the embodiment, an example in which the present invention is applied to a slot machine in which the bet number is set by using medals and credits as the game value has been described, but the slot machine in which the bet number is set by using the game ball as the game value has been described. Alternatively, it may be applied to a fully credited slot machine that sets the number of bets using only credits as a gaming value. When the game ball is used as the game value, for example, one medal can correspond to five game balls, and when the bet number is set to 3 in the first embodiment, 15 game balls are used. Corresponds to setting the number of bets using.

Further, the value is not limited to using only one of a plurality of types of game values such as medals and game balls, and for example, a plurality of types of game values such as medals and game balls can be used together. It may be. That is, it is possible to set the number of bets and play a game by using any of a plurality of types of game values such as medals and game balls, and a plurality of types of games such as medals and game balls are generated when a prize is generated. A slot machine that can pay out any value may be applied.

Further, in the embodiment, the slot machine has been described as an example of the gaming machine, but the initial setting processing, the timer interrupt processing, the command storage processing, and the normal time related to the main control unit 41 and the main control unit 41 disclosed in the above embodiment have been described. By launching a game ball into another gaming machine, for example, a gaming area, processing related to the sub-control unit 91 and the sub-control unit 91, such as command transmission processing, command transmission processing at the time of power interruption, and timer counter update processing, is performed. It may be applied to a pachinko gaming machine or the like in which a game is played and the launched game ball enters a winning opening provided in the game area to generate a prize, and the game ball is paid out as a prize ball.

1 Slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 Start switch 8L, 8C, 8R Stop switch 41 Main control unit 91 Sub control unit

Claims (1)

In a game machine that can play games
A memory means for storing programs and
A microcomputer that executes processing according to a program stored in the storage means is provided.
The program includes an interrupt program that is executed in response to the occurrence of an interrupt.
The microcomputer
When interrupts are permitted, interrupt processing execution means that executes processing according to the interrupt program based on the interrupt, and interrupt processing execution means.
An address storage means having a storage area capable of storing the address of the interrupt program in the storage means, and an address storage means.
A determination means for determining whether or not the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is started, and a determination means.
A start-prohibiting means that does not start the microcomputer when the determination means determines that the address of the interrupt program is not within the predetermined range.
A timer value storage means that can store timer values in a plurality of timer value storage areas that can store timer values, and
It is provided with a timer value updating means capable of updating the timer values stored in a plurality of timer value storage areas in the processing according to the interrupt program.
The timer value storage means, when any kind of timing conditions among a plurality of types of timing condition is satisfied, stores the timer value corresponding to the regimen during conditions timer value storage area according to the regimen at conditions,
Consecutive addresses are assigned to multiple timer value storage areas according to a predetermined rule.
The timer value updating means can update the timer values stored in a plurality of timer value storage areas by repeatedly executing the timer value updating process.
The timer value update process changes the designated address for the timer value storage area by performing a predetermined operation, determines the timer value stored in the timer value storage area corresponding to the changed designated address, and determines the timer value. There without updating the timer value if 0, a process of updating the timer value if it is other than 0, the gaming machine.

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