JP6532720B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine and a slot machine.

  As this type of gaming machine, for example, a program relating to the progress of a game for performing lottery or operation of each part according to the operation of a player and abnormality detection not directly related to the progress of the game (for example, abnormal winning) And the program related to the determination etc. are mixed and stored in one storage area (for example, see Patent Document 1).

JP 2007-222418 A

  In the gaming machine described in Patent Document 1, if there is a mixture of a program relating to the progress of a game and a program not directly related to the progress of the game in one storage area, which program is a program relating to the progress of the game It was difficult to determine if it was.

  The present invention has been made in view of such problems, and it is an object of the present invention to provide a gaming machine capable of easily discriminating between a program related to the progress of a game and a program not related to the progress of the game. Do.

In order to solve the above problems,
The gaming machine according to claim 1 of the present invention is
In a gaming machine that plays a game,
Storage means having a storage area capable of storing data;
Permission area setting means capable of setting an area for permitting execution of a program among the storage areas;
Equipped with
The storage area is
A first program storage area in which a first program related to the first control is stored;
A first data storage area in which first data used by the first program is stored;
A second program storage area in which a second program related to the second control is stored;
A second data storage area in which first data used by the second program is stored;
Including
The first program storage area is an area from the first address of the storage area to the first address,
The first data storage area is an area from the next address to the second address of the first address of the storage area,
The second program storage area is an area from a third address to a fourth address after the second address of the storage area,
The second data storage area is an area from an address following the fourth address of the storage area to a fifth address,
In the area from the address next to the second address to the address before the third address of the storage area and the area from the next address to the final address of the fifth address, 0 is stored in all areas. It is an unused area,
The permission area setting means sets an area from the top address of the storage area to the first address and an area from the third address to the fourth address as areas for permitting execution of the program.
It is characterized by
The gaming machine according to claim 2 of the present invention is
In a gaming machine that plays a game,
Storage means having a storage area capable of storing data;
Permission area setting means capable of setting an area for permitting access to data stored in the storage area;
Equipped with
The storage area is
A first program storage area in which a first program related to the first control is stored;
A first data storage area in which first data used by the first program is stored;
A second program storage area in which a second program related to the second control is stored;
A second data storage area in which first data used by the second program is stored;
Including
The first program storage area is an area from the first address of the storage area to the first address,
The first data storage area is an area from the next address to the second address of the first address of the storage area,
The second program storage area is an area from a third address to a fourth address after the second address of the storage area,
The second data storage area is an area from an address following the fourth address of the storage area to a fifth address,
In the area from the address next to the second address to the address before the third address of the storage area and the area from the next address to the final address of the fifth address, 0 is stored in all areas. It is an unused area,
The permission area setting means sets an area from the top address of the storage area to the fifth address as an area for permitting access to the stored data collectively.
It is characterized by
The gaming machine of means 1 of the present invention is
In a gaming machine (slot machine 1) that plays a game,
Storage means (ROM 41 b, RAM 41 c) having a storage area capable of storing data;
Permission area setting means (setting based on the HW parameter by the main control unit 41) capable of setting an area for permitting predetermined control (travel of program, data access) among the storage areas;
Equipped with
The storage area is
A first storage area (game program area) in which a first program (game program) related to the first control is stored;
A second storage area (non-gaming program area) in which a second program (non-gaming program) related to the second control is stored;
An unused area (the area before the rear storage area (non game program area) allocated behind of the first memory area (game program area) and the second memory area (non game program area)) Unused area 1),
Including
The permission area setting means sets the predetermined control (running of program, data access) for each of the first storage area (game program area) and the second storage area (non-game program area). It is characterized by
According to this feature, the first storage area storing the first program related to the first control and the second storage area storing the second program related to the second control are separately allocated. In addition, since the unused area is allocated to the area before the backward storage area allocated behind among the first storage area and the second storage area, the first program and the second program It can be easily identified according to the difference. Further, among the storage areas, only the area set by the permission area setting means is permitted to perform predetermined control, and each of the first storage area and the second storage area is set as an area for permitting predetermined control, so that the illegal program It is possible to prevent unintended control due to illegal data.

The gaming machine of means 2 of the present invention is
In a gaming machine (slot machine 1) that plays a game,
Storage means (ROM 41 b, RAM 41 c) having a storage area capable of storing data;
Permission area setting means (setting based on the HW parameter by the main control unit 41) capable of setting an area for permitting predetermined control (travel of program, data access) among the storage areas;
Equipped with
The storage area is
A first storage area (game program area) in which a first program (game program) related to the first control is stored;
A second storage area (non-gaming program area) in which a second program (non-gaming program) related to the second control is stored;
An unused area (the area before the rear storage area (non game program area) allocated behind of the first memory area (game program area) and the second memory area (non game program area)) Unused area 1),
Including
Of the first storage area (game program area) and the second storage area (non-game program area) from the forward storage area (game program area) allocated to the front to the rear storage area (non-game program area) An area is collectively set as an area for permitting the predetermined control (travel of a program, data access).
According to this feature, the first storage area storing the first program related to the first control and the second storage area storing the second program related to the second control are separately allocated. In addition, since the unused area is allocated to the area before the backward storage area allocated behind among the first storage area and the second storage area, the first program and the second program It can be easily identified according to the difference. Further, predetermined control is permitted only for the area set by the permission area setting means among the storage areas, and backward allocated from the front storage area allocated to the front among the first storage area and the second storage area. Since the area up to the storage area is collectively set as the area for permitting the predetermined control, it is possible to prevent the unintended control by the unauthorized program or the unauthorized data being performed.

Incidentally, the front and back of the storage area in the means 1 and 2 refer to the magnitude relationship of the address values assigned to the storage area, the smaller the address being the front and the larger the address the rear. For this reason, the rear storage area allocated behind among the first storage area and the second storage area in the means 1 and 2 is the address value allocated among the first storage area and the second storage area. The storage area of the larger one corresponds. Further, the front storage area allocated forward of the first storage area and the second storage area in the means 2 is the smaller of the address values allocated among the first storage area and the second storage area. Corresponds to the storage area of.
Further, any means may be employed as long as the unused area is allocated in front of the backward storage area in the means 1 and 2, and the forward storage area, the unused area and the backward storage area may be allocated adjacent to each other. Another storage area may be allocated between the area and the unused area.
Further, setting of the area for permitting predetermined control in the means 1 and 2 may be setting of the area itself for permitting predetermined control, or as a result of setting the area for prohibiting predetermined control, the predetermined An area for permitting control may be set.
Further, setting each of the first storage area and the second storage area as the area for permitting the predetermined control in the means 1 permits the predetermined control only for the area when setting these areas. It may be set as an area, or other areas adjacent to the area may be collectively set as an area for permitting the predetermined control.
Further, in the means 2, among the first storage area and the second storage area, the area from the front storage area allocated to the front to the rear storage area is collectively set as an area to permit the predetermined control, When setting the area, only the area from the front storage area to the rear storage area may be collectively set as an area for permitting the predetermined control, or adjacent to the area from the front storage area to the rear storage area Other areas may be collectively set as the area for permitting the predetermined control.

The gaming machine according to means 3 of the present invention is the gaming machine according to means 1 or 2, wherein
The predetermined control is characterized by being control (data access) for accessing a storage area (program / data area).
According to this feature, since control to access an area other than the area set by the permission area setting means in the storage area is not permitted, it is possible to prevent unintended control by the illegal program or the illegal data.

The gaming machine of means 4 of the present invention is the gaming machine according to any one of means 1 to 3, and
The predetermined control is characterized by being control (execution of a program) for executing a program stored in a storage area (program).
According to this feature, since control to execute a program stored in an area other than the area set by the permission area setting means in the storage area is not permitted, unintended control based on the illegal program or the illegal data is performed. Can be prevented.

The gaming machine according to means 5 of the present invention is the gaming machine according to any one of means 1 to 4, and
The unused area is characterized in that a specific value (0) is stored in all areas.
According to this feature, since the specific values are stored in all the unused areas, the first storage area and the second storage area can be easily distinguished from the unused area, and Even if illegal data is stored in the area, it can be easily found.

A gaming machine according to means 6 of the present invention is the gaming machine according to any one of means 1 to 5, wherein
The first storage area (game program area) and the second storage area (non-game program area) are areas starting from an address (0H) whose lower N (N is a natural number of 1 or more) digits have the same value. It is characterized by
According to this feature, the first storage area and the second storage area can be easily distinguished from other areas.

The gaming machine according to means 7 of the present invention is the gaming machine according to any one of means 1 to 6, and
Specifying an address corresponding to an area where a program to be called is stored based on the upper address and the lower address, and calling means (CALLV instruction) for calling a program from the area corresponding to the specified address;
Storage means (vector table) for storing a specific value (08H);
Equipped with
The specific program (subroutine frequently used) of the first program (game program) or the second program (non-game program) is stored in the area corresponding to the address of the specific value (08H) in the upper address. Yes,
The calling means specifies an upper address based on the specific value (08H) stored in the storage means (vector table) when calling the specific program (subroutine frequently used), and the designated lower order. It is characterized by specifying an address.
According to this feature, the upper address constituting a part of the address used when calling the specific program of the first program or the second program is stored in advance in the storage means as the specific value, and is stored in the storage means Since the address is specified based on the specified value, it is possible to reduce the waste of the program for specifying the address when calling the specified program.

A gaming machine according to means 8 of the present invention is the gaming machine according to any one of means 1 to 7, wherein
Interrupt processing execution means for executing processing (timer interrupt processing (main)) according to the interrupt program based on the interrupt;
Address storage means (vector table) capable of storing an address of an interrupt program (timer interrupt process (main));
Determining means for determining at start-up whether or not the address stored in the address storage means (vector table) is within a predetermined range (an area where programs etc. are actually stored in the program area);
Activation limiting means for restricting activation when it is determined that the address stored in the address storage means (vector table) is not within the predetermined range (the main control unit 41 Do not start if the area is not actually stored)
It is characterized by
According to this feature, it is possible to prevent in advance the execution of unintended interrupt processing.

A gaming machine according to means 9 of the present invention is the gaming machine according to any one of means 1 to 8, wherein
Setting means for setting the control means (setting of various functions performed with reference to the HW parameter);
Processing means for executing processing based on a control program (game program or non-game program) after setting by the setting means;
Interrupt generation means (timer circuit 509) for generating an interrupt in response to satisfaction of the interrupt condition;
Interrupt processing execution means for executing interrupt processing (timer interrupt processing (main)) based on the interrupt;
Interrupt limiting means for limiting the occurrence of interrupts by the interrupt generating means;
Including
The interrupt limiting means is a first interrupt limiting means (setting of interrupt prohibition by setting at start-up) which limits occurrence of an interrupt before processing based on the control program (initial setting process) is started. And second interrupt restriction means (setting of interrupt prohibition by initial setting processing) for restricting the occurrence of the interrupt when the processing based on the control program is started.
It is characterized by
According to this feature, it is possible to prevent an unintended interruption from occurring.

A gaming machine according to means 10 of the present invention is the gaming machine according to any one of means 1 to 9, and
A plurality of timer value storage areas (for example, 1-byte timers A to C);
A timer value storage area (for example, 1-byte timer A) corresponding to the clocking condition when any of the clocking conditions of a plurality of types of clocking conditions (for example, clocking conditions of 1-byte timers A to C) is satisfied. Timer value storing means (main process) for storing a timer value according to the clocking condition in ~ C),
Timer value update means (time counter update processing) capable of updating timer values stored in a plurality of timer value storage areas (for example, 1-byte timers A to C) at predetermined intervals (about 2.24 ms);
Equipped with
To a plurality of timer value storage areas (for example, 1-byte timers A to C), consecutive addresses (804CH to 804EH) are allocated according to a predetermined rule (+1),
The timer value updating means performs a predetermined operation (designated address +1) on update processing (processing for subtracting one from the value indicated by the pointer) for updating the timer value stored in the timer value storage area corresponding to the designated address. Thus, the present invention is characterized in that multiple types of timer values can be updated by repeatedly executing while changing the designated address to the timer value storage area.
According to this feature, while a continuous address is allocated to a plurality of timer value storage areas according to a predetermined rule, an update process for updating the timer value stored in the timer value storage area corresponding to the designated address is specified. Since multiple types of timer values are updated by repeatedly executing while changing the designated address to the timer value storage area by performing the following operation, processing for updating multiple types of timer values is performed for each type of timer value. The program capacity can be reduced more than that.
The assignment of consecutive addresses according to a predetermined rule means, for example, that a start address and an address to which N (N is a natural number) is added from the start address are assigned.
Further, changing the designated address for the timer value storage area by performing a predetermined operation means, for example, changing the designated address by adding or subtracting a value corresponding to the number of processings from the current designated address, The specified address is changed by adding or subtracting a constant to or from the reference address. At this time, the value or constant corresponding to the number of processes may differ depending on the storage capacity of the timer value. For example, if the timer value is stored by 1 byte, the value corresponding to the number of processes is the number of processes Accordingly, 1, 2, 3, ... and the constant becomes 1. However, if the timer value is stored in 2 bytes each, the value according to the number of processing becomes 2, 4, 6 ... according to the number of processing. , Constant is 2.

  The present invention may have only the invention specific matters described in the claims of the present invention, and has the configuration other than the invention specific matters together with the invention specific matters described in the claims of the present invention. It may be something.

It is a front view of the slot machine of the example to which the present invention was applied. It is a perspective view which shows the internal structure of a slot machine. It is a block diagram showing composition of a slot machine. It is a block diagram showing composition of a main control part. It is a figure which shows the memory map of ROM which a main control part mounts, and RAM. It is a figure which shows the detail of the memory map of ROM which a main control part mounts, and RAM. It is a figure which shows the structure of a game program and a non-game program. It is a figure which shows the relationship between a game area and a non-game area. It is a flowchart which shows the flow of the process at the time of calling a non-gaming program. It is a flowchart which shows the control content of the initialization processing which a main control part performs. It is a flowchart which shows the control content of the setting change process which a main control part performs. It is a flowchart which shows the control content of the main process which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs. It is a flowchart which shows the control content of the command storing process which a main control part performs. It is a flowchart which shows the control content of the normal time command transmission process which a main control part performs. It is a flowchart which shows the control content of command transmission processing at the time of a power failure which a main control part performs. It is a flowchart which shows the control content of the interruption processing which a main control part performs. It is a timing chart for explaining the flow of control at the time of starting of a main control part and a sub control part, and at the time of a power failure. It is a flowchart which shows the control content at the time of a main control part determining the value of a timer counter in main processing. It is a figure which shows the storage area of the timer counter in RAM. It is a flowchart which shows the control content of the time counter update process which a main control part performs.

  A mode for carrying out a gaming machine according to the present invention will be described below based on an embodiment.

  An embodiment of a slot machine which is a gaming machine to which the present invention is applied will be described with reference to the drawings. As shown in FIG. 1, the slot machine 1 of this embodiment is a case 1a having an open front, and this case It is comprised from the front door 1b pivotally pivotally supported by the side end of the body 1a.

  Inside the housing 1a of the slot machine 1 of this embodiment, as shown in FIG. 2, reels 2L, 2C, 2R (hereinafter referred to as left reel, middle reel, right reel) in which plural kinds of symbols are arranged on the outer periphery ) Are juxtaposed in the horizontal direction, and as shown in FIG. 1, three consecutive symbols among the symbols arranged on these reels 2L, 2C, 2R are visible from the perspective window 3 provided on the front door 1b. It is arranged as.

  On the outer peripheral part of the reels 2L, 2C, 2R, a predetermined number of symbols (identification information) which can be distinguished from each other are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels 2L, 2C, 2R are displayed in three stages, upper, middle, lower, respectively, in a see-through window 3 provided substantially at the center of the front door 1b.

  The respective reels 2L, 2C, 2R are rotated by the corresponding reel motors 32L, 32C, 32R (see FIG. 3) so that the symbols on the respective reels 2L, 2C, 2R are continuous with the see-through window 3 While being displayed changing while being displayed, by stopping the rotation of each of the reels 2L, 2C, 2R, three consecutive symbols are derived and displayed on the transparent window 3 as a display result.

  Inside the reels 2L, 2C, 2R, reel sensors 33L, 33C, 33R for detecting the reference position respectively for the reels 2L, 2C, 2R, and a reel LED 55 for irradiating the reels 2L, 2C, 2R from the back side , Is provided. Further, the reel LED 55 is composed of 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, 2R, and can be irradiated with each symbol independently.

  A display area 51a of a liquid crystal display 51 (see FIG. 1) is disposed at a position on the near side (player side) of each reel 2L, 2C, 2R of the front door 1b. The liquid crystal display 51 has a liquid crystal panel having transparency in a state in which a voltage is not applied to the liquid crystal element, and through the transmissive region 51b and the transmissive window 3 corresponding to the transmissive window 3 of the display region 51a. Thus, each reel 2L, 2C, 2R can be visually recognized from the player side.

  On the front door 1b, as shown in FIG. 1, a medal insertion portion 4 capable of inserting medals, a medal payout opening 9 for medals to be paid out, and a credit (the number of medals stored as gaming value owned by a player) MAX BET switch 6 operated when setting the maximum bet number among the bet numbers defined according to the game state within that range, setting the medals and bet numbers stored as credits Adjustment switch 10 operated at the time of settling the medals used for (setting the credits and the number of bets used), the start switch 7 operated at the start of the game, reels 2L, 2C The stop switches 8L, 8C, 8R are operated by the player so as to be operated when the rotation of 2R is stopped respectively.

  In addition, as shown in FIG. 1, on the front door 1b, the credit display 11 displays the number of medals stored as credits, and indicates the number of medals paid out due to the occurrence of winnings and the contents when an error occurs. Error code etc. is displayed, game auxiliary indicator 12, 1 bet LED 14 to notify that the bet number is set by lighting, 2 BET LED 15 to notify by light that 2 bet numbers are set, 3 bet number is set 3 BET LED 16 notifying that it is lit by lighting, insertion request LED 17 notifying by light that the medal can be inserted, start effective LED 18 notifying that the game start operation by the operation of the start switch 7 is effective , Weight (The reel starts rotating because a certain period of time has not passed since the game started Waiting to have state) in wait for notifying by lighting the effect that in LED 19, a game display section 13 in the replay LED20 is provided for informing it is provided by lighting the effect that during replay game, which will be described later.

  Inside the MAX BET switch 6, a BET switch valid LED 21 (see FIG. 3) is provided to notify by lighting that the setting operation of the bet number by the operation of the MAX BET switch 6 is enabled, and the stop switches 8L, 8C, The left, middle, and right stop enable LEDs 22L, 22C, and 22R (see FIG. 3) are provided in the interior of 8R to notify that the stop operation of the reel by the corresponding stop switches 8L, 8C, 8R is effective by lighting. It is done.

  Inside the front door 1b, as shown in FIG. 2, a reset switch 23 for detecting an error state to be described later and a reset operation for releasing a pause state to be described later by a predetermined key operation, change of setting values to be described later The setting value display 24 in which the setting value at that time is displayed during confirmation of the setting value or in the middle, the bat is controlled to a stop state (a state in which the progress of the game is restricted until a reset operation is made) Stop switch 36a for selecting the enable / disable of the stop function, Automatic control to automatically settle processing at predetermined timing (processing to settle (return) the medal stored as a credit without the operation of the player) An automatic settlement switch 36b for selecting the validity / invalidity of the settlement function, a hopper tank 34a (described later) provided inside the housing 1a for the flow path of medals inserted from the medal insertion unit 4 2) A flow path switching solenoid 30 for selectively switching to either the side or the medal payout port 9 side, and the inserted medal sensor 31 that detects medals thrown from the medal insertion section 4 and flowing down to the hopper tank 34a side. A medal selector 29 having an insertion port sensor 26 for detecting insertion of foreign matter on the upstream side of the insertion medal sensor 31 and a door opening detection switch 25 (see FIG. 3) for detecting the open state of the front door 1b are provided.

  Inside the housing 1a, as shown in FIG. 2, the reel reference positions of the reels 2L, 2C, 2R, the reel motors 32L, 32C, 32R (see FIG. 3) and the respective reels 2L, 2C, 2R are respectively described. Reel unit 2 composed of detectable reel sensors 33L, 33C, 33R (see FIG. 3), external output board 1000 (see FIG. 3) for outputting an external output signal, and medals inserted from the medal insertion unit 4 are stored. Hopper motor 34b (see FIG. 3) for paying out the medals stored in the hopper tank 34a and the hopper tank 34a from the medal payout opening 9 and a payout sensor 34c for detecting medals paid out by driving the hopper motor 34b (see FIG. The hopper unit 34 and the power supply box 100 which consist of FIG. 3 are provided.

  At the side of the hopper unit 34, an overflow tank 35 is provided in which the medals overflowing from the hopper tank 34a are stored. Inside the overflow tank 35, a full tank sensor 35a (see FIG. 3) is provided for detecting that the stored medals are full.

  On the front of the power supply box 100, as shown in FIG. 2, it functions as a setting key switch 37 for switching to a setting change state or a setting confirmation state, and as a reset switch for canceling an error state or a suspension state under normal conditions. In the setting change state, the reset / setting switch 38 functions as a setting switch for changing the setting value of the internal lottery winning probability (outgoing ball ratio) described later, and the power supply operated when turning the power on / off A switch 39 is provided.

  The power supply box 100 is provided inside the housing 1a, and the front door 1b is provided on the front of the power supply box 100 because it can be opened by a predetermined key operation possessed by a store clerk or the like. Only the store clerk or the like who holds the key can operate the set key switch 37, the reset / set switch 38, and the power switch 39 so that the player can not operate it. The same applies to the reset switch 23 detected by a predetermined key operation. In particular, since the setting key switch 37 requires the key operation after opening the front door 1b by the key operation, among the salesclerk of the game arcade, only the clerk who holds the key for operating the setting key switch 37 Operation is possible.

  When playing a game in the slot machine 1 of this embodiment, first, a medal is inserted from the medal insertion unit 4 or a bet number is set using a credit. In order to use the credits, the MAX BET switch 6 may be operated. When a prescribed number of bets determined according to the gaming state is set, the payline LN (see FIG. 1) becomes effective, and the operation of the start switch 7 is effective, that is, the state where the game can be started. Become. When the medal is inserted exceeding the maximum number among the prescribed numbers corresponding to the gaming state, that amount is added to the credit.

  The pay line is a line set to determine whether a combination of symbols displayed in the see-through window 3 of each of the reels 2L, 2C, 2R is a combination of pay symbols. In the present embodiment, as shown in FIG. 1, only the payline LN set across the middle of the reel 2L, the middle of the reel 2C, and the middle of the reel 2R, that is, the symbols horizontally arranged in the middle is as a payline. It is fixed. Although only one pay line is applied in this embodiment, a plurality of pay lines may be applied.

  Further, in the present embodiment, in order to make it easy to recognize that the combination of the symbols constituting the winning combination is complete in the winning line LN, the invalid lines LM1 to LM4 are set separately from the winning line LN. Ineffective lines LM1 to 4 are not determined to be winning by a combination of symbols aligned to these ineffective lines LM1 to IV, and when a combination of symbols constituting a specific winning is aligned on the payline LN, an invalid line The combination of symbols (for example, bell-bell-bell) which will be a prize when aligned to the payline LN in any one of the LM1 to 4 is made uniform, thereby forming a specific prize in the payline LN. This makes it easy to recognize that the combination is complete.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, 2R are rotated, and the symbols of the reels 2L, 2C, 2R are continuously varied. In this state, when any one of the stop switches 8L, 8C, 8R is operated, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the transparent window 3.

  And one game is ended by stopping all the reels 2L, 2C, 2R, and a combination of symbols (hereinafter also referred to as a combination) determined in advance on the payline LN is displayed on each reel 2L, 2C, 2R When the game is stopped as a result, a winning occurs, and the number of medals determined according to the winning is awarded to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in the present embodiment), the medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, on the pay line LN, when the combination of symbols accompanied by the transition of the gaming state is stopped as the display result of each reel 2L, 2C, 2R, it is shifted to the gaming state according to the combination of symbols .

  In the present embodiment, the game is started when the operation of the start switch 7 is detected in a state where the operation of the start switch 7 is valid, and the game is ended when all the reels are stopped. In addition, one unit control (game control) for executing a game starts when all the controls associated with the end of the previous game are completed, and when all the controls associated with the end of the game are completed. finish.

  Further, in the present embodiment, the configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, or a configuration using four or more reels may be used. In a configuration using two or more reels, winning may be determined based on a combination of display results derived on all the two or more reels. Further, in the present embodiment, the variable display device is configured by physical reels, but the variable display device may be configured by an image display device such as a liquid crystal display.

  Further, in the slot machine 1 in the present embodiment, after the game is started and the reels 2L, 2C, 2R are rotated to start symbol variation, any one of the stop switches 8L, 8C, 8R is operated. When it is done, the rotation of the reels corresponding to the stop switches 8L, 8C, 8R is stopped and the symbol is stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

  The reels 2L, 2C, and 2R rotate 80 times in 1 minute, and change 80 x 21 (the number of symbol frames per reel) = 1680 frames, so they draw in a maximum of 4 symbols during 190 ms. It will be possible. That is, what can be selected as the stop symbol is the symbol displayed when the stop switch 8L, 8C, 8R is operated, the symbol from four frames ahead, and the symbol for five frames in total.

  For this reason, for example, when any of the stop switches 8L, 8C, and 8R is operated, based on the symbol displayed on the lower side of the reel corresponding to the stop switch, the symbol from the symbol to the four frames ahead Since the symbol can be displayed in the lower part, the symbol displayed on the middle of the reel corresponding to the stop switch when any one of the stop switches 8L and 8R is operated on each of the reels 2L, 2C, 2R The symbols arranged within 5 frames including can be displayed on the pay line.

  Hereinafter, the reels 2L, 2C, and 2R may be simply referred to as reels unless there is a need to distinguish them. Further, the reel 2L may be referred to as a left reel, the reel 2C may be referred to as a middle reel, and the reel 2R may be referred to as a right reel. Further, the operation of stopping the reels 2L, 2C, 2R by the operation of the stop switches 8L, 8C, 8R may be referred to as a stop operation.

  FIG. 3 is a block diagram showing the configuration of the slot machine 1. As shown in FIG. 3, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The gaming control board 40 controls the gaming state, and the effect control board 90 controls the gaming state The effect according to is controlled, and the power supply substrate 101 generates drive power of electric components constituting the slot machine 1 and supplies it to each part.

  The power supply substrate 101 is externally supplied with AC 100 V power, and the AC 100 V power supply generates a DC voltage necessary to drive the electric components that make up the slot machine 1. The game control board 40 and the effect control board 90 To be supplied to Further, to the power supply substrate 101, the hopper motor 34b, the payout sensor 34c, the full tank sensor 35a, the setting key switch 37, the reset / setting switch 38, and the power switch 39 described above are connected.

  On the game control board 40, the aforementioned MAX BET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, stop switch 36a, automatic settlement switch 36b, inserted medal sensor 31, door open The detection switch 25 and the reel sensors 33L, 33C, and 33R are connected, and the above-described dispensing sensor 34c, the full tank sensor 35a, the setting key switch 37, and the reset / setting switch 38 are connected via the power supply substrate 101, Detection signals of these connected switches are input. In addition, the gaming control board 40, the aforementioned credit indicator 11, gaming assistance indicator 12, 1-3 BETLED 14-16, closing request LED17, start effective LED18, weight in progress LED19, replay in progress LED20, BET switch effective LED21, left While the right stop effective LED 22L, 22C, 22R, the setting value display 24, the flow path switching solenoid 30, the reel motor 32L, 32C, 32R are connected, the hopper motor 34b described above via the power supply board 101 The electric components are connected and driven under the control of a main control unit 41 described later mounted on the game control board 40.

  The game control board 40 includes a main control unit 41 that performs processing related to the game, a control clock generation circuit 42 that generates a control clock CCLK, a random number clock generation circuit 43 that generates a random number clock RCLK, and switches The switch detection circuit 44 takes in the input detection signal and transmits it to the main control unit 41, the motor drive circuit 45 transmits the motor drive signal (phase signal of the stepping motor) to the reel motors 32L, 32C, 32R, and the solenoid drive signal The solenoid drive circuit 46 that transmits the flow path switching solenoid 30, the LED drive circuit 47 that transmits the LED drive signal to various displays and LEDs, and a voltage drop signal indicating that when the voltage drop is detected Power failure detection circuit 48 that outputs to the Source reset circuit 49 to provide the system reset signal to the main control unit 41 is mounted in an unstable state.

  FIG. 4 shows an example of the configuration of the main control unit 41 mounted on the game control board 40. The main control unit 41 shown in FIG. 4 is a one-chip microcomputer, and has an external bus interface 501, a clock circuit 502, a check block 503, a unique information storage circuit 504, an arithmetic circuit 505, and a reset / interruption. A controller 506, a central processing unit (CPU) 41a, a read only memory (ROM) 41b, a random access memory (RAM) 41c, a free run counter circuit 507, random number circuits 508a and 508b, and a timer circuit 509; An interrupt controller 510, a parallel input port 511, a serial communication circuit 512, a parallel output port 513, and an address decode circuit 514 are provided.

  The reset / interrupt controller 506 is for controlling various reset and interrupt requests generated inside and outside the main control unit 41. The reset / interrupt controller 506 includes an out-of-designated area running inhibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit that monitors whether or not the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when detecting that the user program is executed outside the designated area. In addition, the watchdog timer 506 b has a function of generating a time-out signal every set period.

  The external bus interface 501 is a bus interface having an interface function between an external bus of a chip constituting the main control unit 41 and an internal bus, an address bus, a data bus, and a direction control function of each control signal. The clock circuit 502 is a circuit that generates an internal system clock SCLK by dividing the control clock CCLK by two. The collation block 503 is connected to an external collation machine and has a function of collating chips. The unique information storage circuit 504 is a circuit for storing a plurality of types of unique information serving as internal information of the main control unit 41. The arithmetic circuit 505 is a circuit that performs multiplication and division.

  The CPU 41a is a control CPU that executes game control in the slot machine 1 by executing a user program (game control processing program for game control) based on the control code read from the ROM 41b. When such game control is executed, the CPU 41a reads out fixed data from the ROM 41b, the fixed data read operation where the CPU 41a writes various fluctuation data to the RAM 41c and temporarily stores them, and the CPU 41a is temporarily stored in the RAM 41c Fluctuation data read operation to read out various fluctuation data, reception operation to receive input of various signals from the outside of the main control unit 41 through the external bus interface 501, parallel input port 511, serial communication circuit 512, etc., CPU 41a Also, a transmission operation of outputting various signals to the outside of the main control unit 41 via the external bus interface 501, the serial communication circuit 512, the parallel output port 513 and the like is also performed.

  The ROM 41 b stores a control code indicating a user program (game control processing program for game control), fixed data, and the like. The RAM 41 c provides a work area or the like for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power supply. That is, even if the power supply to the slot machine 1 is stopped, the content of at least a part of the RAM 41c is stored for a predetermined period.

  As a free run counter circuit 507, an 8-bit free run counter is mounted. The random number circuits 508a and 508b are circuits that generate numerical data such as an 8-bit random number or a 16-bit random number, which is a random number having a predetermined update range. In this embodiment, hardware random numbers generated by the 16-bit random number circuit 508b among the random number circuits 508a and 508b are used as random numbers for internal lottery described later. The timer circuit 509 is a 16-bit programmable timer, which counts down the set timer value based on the input of the control clock CCLK, and outputs an interrupt request signal to the interrupt controller when it reaches 0000h. In this embodiment, the timer circuit 509 can be used to periodically perform interrupt request and time measurement.

  The interrupt controller 510 is a circuit that controls external interrupt requests from the interrupt terminal and interrupt requests from the built-in peripheral circuits (for example, the serial communication circuit 512, the random number circuits 508a and 508b, and the timer circuit 509). . The parallel input port 511 incorporates an 8-bit wide input-only port. Further, the parallel output port 513 included in the main control unit 41 shown in FIG. 4 incorporates an 11-bit wide output dedicated port. The serial communication circuit 512 is a circuit that performs asynchronous serial communication at input / output to / from the outside.

  The address decode circuit 514 is a circuit for decoding each functional block in the main control unit 41 and decoding a chip select signal which is a decode signal for an external device. By the chip select signal, the internal circuit of the main control unit 41 or an external device serving as a peripheral device is selectively enabled to allow access from the CPU 41a.

  The main control unit 41 transmits various commands to the sub control unit 91 via the parallel output port 513. The command transmitted from the main control unit 41 to the sub control unit 91 is sent in one direction only, and the command is not sent from the sub control unit 91 to the main control unit 41. In the present embodiment, the command is transmitted to the sub control unit 91 via the parallel output port 513, that is, the command is transmitted as a parallel signal, but via the serial communication circuit 512. The command may be transmitted to the sub control unit 91, that is, the command may be transmitted as a serial signal.

  The main control unit 41 also receives, from the parallel input port 511, detection states of various switches connected to the game control board 40. Then, the main control unit 41 executes basic processing to shift in stages according to the detection state of various switches input from the parallel input port 511. In addition, the main control unit 41 can interrupt the basic process to execute the interrupt process when the interrupt occurs. In this embodiment, a timer interrupt process (main) to be described later is executed at every occurrence of a time-out in the timer circuit 509, that is, at predetermined time intervals (about 0.56 ms in this embodiment). Further, the main control unit 41 is set to prohibit other interrupts during execution of the interrupt processing, and when a plurality of interrupts occur simultaneously, priority is given according to a predetermined order. The interrupt to be executed is set. It should be noted that another interrupt factor is generated during execution of the interrupt process, and if the interrupt factor continues even if the interrupt process is completed, a new interrupt is generated at that time. It will be.

  The main control unit 41 repeatedly loops the process according to the control state until the detection states of the various switches connected to the game control board 40 change as the basic process, and the main control unit 41 responds to the change in the detection states of the various switches Execute the process of migrating in stages. Further, the main control unit 41 executes timer interrupt processing (main) at predetermined time intervals (about 0.56 ms in the present embodiment). The execution interval of the timer interrupt process (main) is set to a time longer than the combined time of the process to be repeated depending on the control state in the basic process and the execution time of the timer interrupt process (main). Therefore, at least the processing repeated according to the control state is always performed between the current and the next timer interrupt processing (main).

  The rendering control substrate 90 is connected to rendering devices such as a liquid crystal display 51, a rendering effect LED 52, speakers 53 and 54, a reel LED 55, etc. These rendering devices are mounted on the rendering control substrate 90 as described later. It is driven based on the control by the unit 91. In this embodiment, the sub control unit 91 mounted on the effect control substrate 90 controls the output of the effect devices such as the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, and the reel LED 55. However, separately from the sub control unit 91, an output control unit that directly performs output control of the rendering device is mounted on the effect control substrate 90 or another substrate, and the sub control unit 91 is based on a command from the main control unit 41. The output pattern of the rendering device may be determined, and the output control unit may control the output of the rendering device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control The output control of the rendering device is performed by both of the units. In addition, although the liquid crystal display 51, the effect effect LED 52, the speakers 53 and 54, and the reel LED 55 are illustrated as the effect device in the present embodiment, the effect device is not limited to these, for example, a display driven mechanically A device or a mechanically driven combination may be applied as the rendering device.

  The effect control board 90 is constituted by a microcomputer having a sub CPU 91a, a ROM 91b, a RAM 91c, and an I / O port 91d, and a sub control unit 91 for controlling effects and a liquid crystal display connected to the effect control board 90 A display control circuit 92 for controlling the display 51, an effect LED 52, an LED drive circuit 93 for controlling the drive of the reel LED 55, an audio output circuit 94 for controlling audio output from the speakers 53 and 54, power on or sub CPU 91a The reset circuit 95 which gives a reset signal to the sub CPU 91a when the initialization command is not inputted for a predetermined time, the switch detection circuit 96 which detects a detection signal inputted from switches connected to the effect control board 90, date information and time Clock device 97 that outputs time information including information, slot machine 1 It is equipped with a power failure detection circuit 98 that monitors the supplied power supply voltage and outputs a voltage drop signal to that effect to sub CPU 91a when a voltage drop is detected, and other circuits. The CPU 91a receives commands transmitted from the game control board 40, performs various controls for effecting, and directly or indirectly controls each part of the control circuit mounted on the effect control board 90.

  The reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 which gives the system control signal to the main control unit 41 in the game control board 40, and the sub control unit 91 performs main control when the power is turned on. It is started earlier than the unit 41. On the other hand, the voltage detection circuit 98 has a lower voltage for outputting the voltage reduction signal than the power failure detection circuit 48 which outputs the voltage reduction signal to the main control unit 41 in the game control board 40, and In this case, the sub-control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power-off process (sub) described later.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 generates an interrupt each time the number of inputs of the system clock reaches a predetermined number, that is, every predetermined time interval (about 2 ms), and executes timer interrupt processing (sub) described later. Also, unlike the main control unit 41, when an interrupt occurs based on the reception of a command, the sub control unit 91 interrupts the process even while timer interrupt processing (sub) is being executed. The command reception interrupt process is executed, and the command reception interrupt process is executed with the highest priority even if an interrupt that triggers the timer interrupt process (sub) simultaneously occurs. The sub control unit 91 is also supplied with backup power at the time of a power failure, and while the backup power is supplied, data stored in the RAM 91 c is held.

  In the slot machine 1 of this embodiment, the payout rate of medals changes in accordance with the set value. In more detail, the payout rate of medals is changed by using the probability of winning according to the set value in the lottery that affects the player's degree of advantage to the player such as an internal lottery, a navistock lottery, and an additional lottery. The set value is composed of six steps of 1 to 6, and the payout rate is the highest at 6 and the payout rate decreases as the value decreases in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the degree of advantage is the highest for the player, and the degree of advantage decreases stepwise as the values decrease in the order of 5, 4, 3, 2, 1.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after turning on the setting key switch 37. When the power is turned on with the setting key switch 37 in the ON state, the setting value read from the RAM 41c is displayed as a display value on the setting value display 24, and setting can be changed by operating the reset / setting switch 38. Transition to the change state. In the setting change state, when the reset / setting switch 38 is operated, the display value displayed on the setting value display 24 is updated one by one (when the setting value 6 is further operated, the setting value is set to 1 Return). Then, when the start switch 7 is operated, the display value is determined as the set value. Then, when the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 41c of the main control unit 41, and the state shifts to a state where the game can be progressed.

  When the setting key switch 37 is ON and the power is turned on, the setting change state is also transitioned on condition that the door opening detection switch 25 detects that the front door 1b is opened. By setting it like this, it can prevent that a setting change will be carried out illegally in the state which the front door 1b is not open | released. Further, in the configuration to shift to the setting change state on condition that the detection corresponding to the opening of the front door 1b is made, the door opening detection switch 25 responds to the opening of the front door 1b after transitioning to the setting change state. It is preferable to maintain the setting change state even if the detection is no longer performed, whereby even if the front door 1b is temporarily closed during the setting change, an operation for shifting to the setting change state again is performed. There is no need to make the setting change operation complicated. Further, after transitioning to the setting change state, when the setting key switch 37 is turned off after the start switch 7 is operated and the setting value is determined, detection corresponding to the opening of the front door 1b by the door opening detection switch 25 It is also possible to end the setting change state and shift to a state in which the game can be progressed on condition that the front door 1b is not opened even in such a configuration. It is possible to prevent the setting from being changed.

  Further, in order to confirm the setting value, after the game is over, the setting key switch 37 may be turned ON in the state where the bet number is not set. When the setting key switch 37 is turned on in such a situation, the setting value read from the RAM 41 c is displayed on the setting value display 24 to shift to a setting confirmation state where the setting value can be confirmed. In the setting confirmation state, the game can not be progressed, and by setting the setting key switch 37 to the OFF state, the setting confirmation state is ended and the game can be returned to the state in which the progress of the game is possible.

  It should be noted that after the game is over, when the setting key switch 37 is turned ON in a state where the bet number is not set, it is a condition that the door opening detection switch 25 detects that the front door 1b is opened. Alternatively, the configuration may be shifted to the setting confirmation state. With such a configuration, it is possible to prevent the setting value from being checked illegally in a state where the front door 1b is not opened. Further, in the configuration to shift to the setting confirmation state on condition that the detection corresponding to the opening of the front door 1b is made, the door opening detection switch 25 responds to the opening of the front door 1b after transitioning to the setting confirmation state. It is preferable to maintain the setting confirmation state even if the detection is not performed, so that, even if the front door 1b is temporarily closed during the setting confirmation, an operation for shifting to the setting confirmation state again is performed. There is no need to make the setting confirmation operation complicated. Further, after transitioning to the setting confirmation state, when the setting key switch 37 is turned off after the start switch 7 is operated and the setting value is determined, detection corresponding to the opening of the front door 1b by the door opening detection switch 25 It is also possible to end the setting confirmation state and return to the state where the game can be progressed on condition that the front door 1b is not opened in such a condition, in a state where the front door 1b is not opened. It is possible to prevent the setting value from being confirmed.

  In the slot machine 1 of the present embodiment, the main control unit 41 performs a power cut to determine whether or not the voltage drop signal from the power failure detection circuit 48 is detected each time the timer interrupt process (main) is executed. Perform the power-off process (main) to set the data to determine whether the data in the RAM 41c is normal or not at the time of the next return when the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process. Run.

  Then, the main control unit 41 restores the processing state of the main control unit 41 to the state before power interruption based on the data stored in the RAM 41 c on condition that the data of the RAM 41 c is normal at the time of startup. However, when the RAM 41c data is not normal, it is determined that the RAM is abnormal, and the RAM abnormal error code is set in the register to control to the RAM abnormal error state to disable the progress of the game.

  The error state changes to the normal error state released by the reset operation (the operation of the reset / setting switch 38 or the reset switch 23) and the setting change state described above, and is released until a new set value is set. There is no special error state, and the RAM abnormal error state is a special error state, and once controlled to the RAM abnormal error state, it shifts to the setting change state and is released until a new set value is set. It will not be done.

  Further, the sub control unit 91 also determines whether or not the voltage drop signal from the power failure detection circuit 98 is detected in the timer interrupt process (sub), and determines that the voltage drop signal is detected, A power interruption process (sub) is performed to set data for determining whether the data in the RAM 91c is normal or not at the next return.

  Then, the sub control unit 91 restores the processing state of the sub control unit 91 to the state before the power failure based on the data stored in the RAM 91 c on condition that the data in the RAM 91 c is normal at the time of activation. However, when the data in the RAM 91c is not normal, it is determined that the RAM is abnormal and the RAM 91c is initialized. In this case, unlike the main control unit 41, the execution of the effect is not disabled only by initializing the RAM 91c.

  Further, even when it is determined that the data in the RAM 91c is normal at the time of activation, the sub control unit 91 is activated when receiving a setting command described later indicating that the setting change state has been entered from the main control unit 41. The RAM 91 c is initialized also when neither a return command nor a setting command, which indicates that the control state of the main control unit 41 has returned, is received even after a predetermined time has passed. Also in this case, the execution of the effect is not disabled only by initializing the RAM 91 c.

  Next, initialization of the RAM 41 c of the main control unit 41 will be described. The usable area of the storage area of the RAM 41 c of the main control unit 41 is divided into important work, special work, general work, unused area, and stack area, and the important work, special work, general work, unused area , Are arranged in the order of the stack area.

  In the present embodiment, when the data of the RAM 41 c is destroyed when the setting key switch 37 is turned off and the data of the RAM 41 c is destroyed, the data of the RAM 41 c is started when the setting key switch 37 is turned on. When not destroyed, when the setting key switch 37 is activated and the data in the RAM 41c is destroyed at the time of start-up, the setting change end, the end of a specific gaming state, the end of one game from six When the following initialization conditions are satisfied, four different types of initialization are performed according to the respective initialization conditions.

  When initialization is started when the setting key switch 37 is off and data in the RAM 41c is destroyed, initialization 0 is started when the setting key switch 37 is on and data in the RAM 41c is destroyed In initialization 0, all available areas are initialized. The initialization 1 is an initialization performed when the data of the RAM 41 c is not destroyed when the setting key switch 37 is turned ON, and in the initialization 1, other than the important work and the special work in the usable area The area of is initialized. The initialization 2 is an initialization performed at the end of a specific gaming state, and in the initialization 2, a general work, an unused area and an unused stack area out of usable areas are initialized. The initialization 3 is an initialization performed at the end of one game. In the initialization 3, an unused area and an unused stack area of the usable area are initialized. The storage area of the setting value and the data indicating the gaming state is allocated to the special work, and when the data of the RAM 41c is not destroyed when the setting key switch 37 is turned on, that is, the data of the RAM 41c In the case where the setting is normally changed, the setting value and data indicating the gaming state are held. Further, a storage area of a timer counter described later is assigned to a special work, and is held without being initialized at the end of a game or at the end of a specific gaming state.

  In the slot machine 1 of the present embodiment, the specified number of bets that can be set according to the game state is determined, and the game is performed on the condition that the specified number of bets determined according to the game state is set. It is possible to start the In the present embodiment, the pay line LN is activated when the specified number of bets is set according to the game state.

  And, in the present embodiment, when all the reels 2L, 2C, 2R stop, activated pay lines (in the case of the present embodiment, all pay lines are always activated. It becomes a prize when the combination of the symbols called a combination is aligned on the converted pay line is simply called the pay line). The role may be a combination of the same symbols or a combination including different symbols.

  The type of winning combination is determined according to the game state, but can be roughly divided into a small combination with payout of medals and the need to set the number of bets, and the next game can be started again There are a play role and a special role accompanied by transition to a play state advantageous to the player. In the following, the small part and the re-play part are collectively referred to as a general part. In order to generate a winning of each combination determined in accordance with the gaming state, it is necessary to win an internal lottery to be described later, and the winning flag of the combination must be set in the RAM 41c. Of the winning flags for each of these winning combinations, the winning flags for the small winning combination and the re-playing combination are only valid in the game for which the flag is set and are invalid in the next game, but the special winning combination is The combination is valid until the combination of the combination accepted by the flag is complete, and the combination is invalidated in the game. That is, once the winning combination of the special part is won, even if the combination of the combinations permitted by the flag can not be aligned, the winning flag is not invalidated but is carried over to the next game. It becomes.

  Hereinafter, the internal lottery of the present embodiment will be described. In the internal lottery, before the display results of all the reels 2L, 2C, 2R are derived (specifically, the start switch 7), whether or not the main control unit 41 permits winning in each of the above-described combinations. (At the time of detection of In the internal lottery, first, a random number value (an integer of 0 to 65535) for the internal lottery is acquired when the start switch 7 is detected. Specifically, the value generated by the random number circuit 508 b and stored in the random number value register of the random number circuit 508 b is set as the lottery work assigned to the RAM 41 c. Then, for each combination determined according to the gaming state, according to the numerical data stored in the lottery work and the determination value number of each combination determined according to the current gaming state, the number of bets, and the set value. A determination is made as to whether or not to accept a prize.

  In the internal lottery, the role to be the object of the internal lottery, the number of judgment values determined corresponding to the current gaming state and the set value is sequentially set to the random value for the internal lottery (numeric data stored in the lottery work) The addition is performed, and when the result of the addition overflows, it is determined that the winning combination has been won. Therefore, the winning combination is won with the probability (number of judgment values / 65536) according to the magnitude of the number of judgment values.

  When it is determined that one of the winning combinations has been won, the winning flag corresponding to the winning combination is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work is configured by a 2-byte storage area, the upper byte of which is assigned as a special role storage work in which the special winning flag is set, and the lower byte is a general winning The flag is assigned as a general role storing work to be set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination has been selected is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning combination flag indicating that the general combination has been selected is set in the general combination storing work. If neither combination nor combination of winning combinations is won, only the general combination storing work is cleared.

  Next, stop control of the reels 2L, 2C, 2R will be described. The main control unit 41 refers to the table index and table creation data stored in the ROM 41b when the rotation of the reel starts, and when the reel is stopped and the reel which is still rotating remains. Create a stop control table for each spinning reel. The stop control table is data that can specify the number of sliding symbols at each timing when the stop operation is performed. Then, when one of the stop switches 8L, 8C, 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the reference stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the present embodiment, a value of 0 to 4 is determined as the number of sliding symbols, and it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stopping operation. That is, it is possible to designate the stop position of the symbol from the range of maximum 5 frames including the stop operation position at which the stop operation is detected. In addition, since it is necessary to move one frame to move the symbol by one symbol, it is possible to pull in a maximum of four symbols after detecting the stop operation and stop the reel, and the stop having detected the stop operation It will be possible to specify the stop position of the symbol from the range of maximum 5 symbols including the operation position.

  In this embodiment, when one of the winning combinations is won, it is possible to align and stop the winning combinations in the draw-in range of up to 4 frames on the pay line when the stop operation is performed. If possible, control to align and stop these is performed, and to a combination that has not been won, control is performed to stop without aligning in the lead-in range of up to four frames. When a special combination and a small combination are simultaneously won, such as when the small combination is won while the special combination has been carried over from before the previous game, the maximum on the pay line when the stop operation is performed If it is possible to align and stop the small winning combination in the drawing range of 4 pieces, control is made to align and stop this and the small combination winning in the drawing range of up to 4 pieces on the pay line is performed When it is not possible to draw in, if it is possible to align and stop the special part winning in the lead-in range of up to 4 pieces on the pay line, control to align and stop this is performed, and the part not winning Control is performed to stop without aligning in the lead-in range of four frames. That is, in such a case, the control of aligning the small winning combination on the pay line has priority over the special winning combination, and it becomes possible to win the special winning combination only when the small winning combination can not be drawn. When the special role and the small role can be drawn simultaneously, only the small role is drawn in, and the small role and the special role are not aligned on the pay line. In addition, when the special role and the small role are winning at the same time, priority is given to the control to align the special role on the pay line over the small role, and the small role is put on the pay line only when the special role can not be withdrawn. You may perform control to align.

  Further, in the present embodiment, the stop operation is performed when the special combination and the re-play combination are simultaneously won, such as when the re-play combination is won with the special combination carried over from before the previous game. At the time of winning, control is performed to align and stop the symbols of the replay role on the pay line in the lead-in range of up to 4 pieces. In this case, the symbols making up the re-playing combination or the symbols making up the simultaneously playing re-playing combination are arranged within 5 symbols for any of the reels 2L, 2C, 2R, that is, within 4 frames. Because it can always be stopped at any position within the four-frame pull-in range, when the special combination and the re-play combination are simultaneously won, regardless of the operation timing of the stop switches 8L, 8C, 8R by the player. Instead, you will be rewarded with a complete remake. That is, in such a case, the control of aligning the re-play combination on the pay line has priority over the special combination, and the re-play combination will always be won. When the special combination and the re-play combination can be drawn simultaneously, only the re-play combination is drawn in, and the special combination is not arranged on the pay line at the same time as the re-play combination.

  In this embodiment, the stop control of the reel is performed using the stop control table capable of specifying the number of sliding symbols at each timing when the stop operation is performed, but the stop position where the stoppable position can be specified The stop position is specified from the table, and the stop control is performed to stop the reel at the specified stop position. Without using the stop control table or the stop position table, the stop position which can be stopped at the stop operation is searched. A configuration for performing stop control to specify and stop the reel at the specified stop position, stop control using the stop control table, stop control using the stop position table, stop without using the stop control table or the stop position table A configuration that combines stop control by searching and specifying the stop position, and a configuration that performs stop control by partially changing the stop control table and the stop position table It may be.

  In the present embodiment, after starting the game, every time the rotation of the reel is started, the main control unit 41 counts the game time which is the time elapsed from the time when the rotation of the reel is started. After the end of one game, when the specified number of bets is set by inserting a medal, etc. and the game start operation is performed with the game start operation enabled, the reel rotation of the previous game is started. If the game time at which time counting is started from the time point is longer than the specified time (4.1 seconds in this embodiment), that is, if the specified time has elapsed from the reel rotation start time of the previous game, no weight is generated. At that time, the rotation of the reel for the game in the game is started. On the other hand, after the end of one game, when the specified number of bets is set by the insertion of medals, etc. and the game start operation is performed with the game start operation enabled, the reel rotation start of the previous game is started. If the game time at which time counting was started from the time is less than the specified time, that is, if the specified time has not elapsed from the reel rotation start time of the previous game, a weight is generated and the reel rotation is started at that time Instead, the game waits for the specified time to reach the specified time from the start of reel rotation of the previous game, and starts the reel rotation when the specified time is reached.

  In the present embodiment, the main control unit 41 performs control to output an external output signal indicating a gaming state, an occurrence of an error, and the like. These external output signals are output to a hall device such as a hall computer via an external output board 1000 and an information providing terminal board of a game arcade (hall) in which the slot machine 1 is installed.

  The main control unit 41 has a medal IN signal indicating the number of medals used for setting the number of bets, a medal OUT signal indicating the number of medals awarded to the player by the occurrence of a prize, and the gaming state being RB (regular bonus). In-RB signal indicating the effect, BB in-signal indicating the gaming state is in BB (big bonus), RT-in-signal indicating the effect in RT2, door open signal indicating that the front door 1b is open, which will be described later A setting change signal indicating transition to the setting change mode, an insertion error signal indicating abnormality of the medal selector, and a payout error signal indicating abnormality of the hopper unit 34 are respectively output.

  The external output substrate 1000 is provided with a relay circuit, a parallel-serial conversion circuit, and a terminal for each output signal, and a connector to be electrically connected to the circuit of the information provision terminal board is provided. Among the signals output from the game control board 40, the medal IN signal, the medal OUT signal, the RB in-progress signal, and the BB in-progress signal are output as they are as pulse signals to the information providing terminal board via the relay circuit. On the other hand, the door open signal, the setting change signal, the closing error signal, and the payout error signal are converted by the parallel-serial conversion circuit into security signals which are serial signals that can individually identify these signals, and information is provided. It is output to the terminal board.

  Next, commands that the main control unit 41 transmits to the sub control unit 91 will be described.

  In the present embodiment, the main control unit 41 instructs the sub control unit 91 the number-of-inputs command, the credit command, the game state command, the internal winning command, the reel acceleration information command, the stop operation command, the sliding number command, the stop A plurality of types of commands including a command, game end command, winning number command, payout start command, payout end command, standby command, halt command, error command, return command, setting command, setting confirmation command and door command are transmitted.

  The insertion number command is a command that can specify the number of medals inserted, that is, the number of medals used for setting the number of bets, and is the state from the end of the game (after the setting change) to the start of the game. Or, when the specified number of bets is not set, a medal is inserted, or the MAX bet switch 6 is operated to transmit when the number of bets is set. Further, since the inserted number command is transmitted when the bet number setting operation is performed, it is possible to specify that the bet number setting operation is performed by receiving the inserted number command. The credit command is a command capable of specifying the number of medals stored as a credit, and is in a state from the end of the game (after the change of setting) to the start of the game, and in a state where the specified number of bets is set, Sent when medals are inserted and credits are added.

  The game state command is a command that can specify the game state of the game, and is transmitted when the start switch 7 is operated to start the game. The internal winning command is a command that can specify the internal lottery result, and is transmitted when the game is started after the start switch 7 is operated and the game is started. Since the game state command and the internal winning command are transmitted when the start switch 7 is operated and the game starts, receiving these commands enables the start switch 7 to be operated and the game started to be identified. It is.

  The reel acceleration information command is a command that can specify that the rotation of the reel starts as the game progresses, and is transmitted when the rotation of the reel starts as the game progresses. The stop operation command is a command capable of specifying whether the reel to be stopped is a left reel, a middle reel, or a right reel, or the area number of the stop operation position of the corresponding reel. It is transmitted each time the accompanying stop control is performed. The command for the number of sliding symbols is a command that can specify the number of sliding symbols to move from when the reel to be stopped is any of the left reel, the middle reel, and the right reel, or after the corresponding reel is stopped. Each time the stop control associated with the stop operation of each reel is performed, the corresponding stop operation command is transmitted after being transmitted. The stop command is a command that can specify which of the left reel, the middle reel, and the right reel the reel to be stopped is and the area number of the stop position of the corresponding reel, and the stop control accompanying the stop operation of each reel Is sent after the corresponding slide number command is sent. The stop operation command, the sliding number command, and the stop command can specify whether the reel to be stopped is any of the left reel, the middle reel, and the right reel and can be specified along with the stop operation of each reel. Since it is transmitted each time the stop control is performed, it is possible to specify that one of the reels has been stopped and the reels to be stopped by receiving these commands.

  The game end command is a command capable of specifying that the game has been ended, and is transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch. The winning number command is a command capable of specifying the combination of symbols arranged in the winning line LN, the presence or absence of winning, the type of winning, and the number of medals paid out at the time of winning, and for the player to stop the third stop reel. When the stop switch is depressed and the stop switch is released, it is transmitted after the transmission of the game end command. The game end command and the winning number command are both transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch, so these commands are received. It is possible to specify that all operations necessary to advance one game have ended.

  The payout start command is a command for notifying start of medal payout, and is transmitted when payout of medals is started by winning or winning a credit (including medals used for setting the number of bets). The payout end command is a command for notifying the medal payout end, and is transmitted when the payout of the medal due to the winning and the settlement of credits is ended.

  The standby command is a command indicating transition to the standby state, and when one game is ended, the credit is entered when the estimated end time (60 seconds in this embodiment) elapses without setting the number of bets, and then the credit is entered. It is sent after the payout of the medals by the settlement of the payment (including the medal used for setting the number of bets) is completed and the payout end command is sent.

  The suspension command is a command indicating the occurrence or cancellation of the suspension state, and when the ending effect waiting time elapses after the BB is completed, the suspension command indicating the occurrence of the suspension state is transmitted, and the reset operation is performed. When the suspension state is released, a suspension command indicating release of the suspension state is transmitted. An error command is a command that indicates the occurrence or cancellation of an error condition or a type of error condition, and when an error is determined and controlled to an error condition, an error command indicating the occurrence of an error condition and its type is transmitted, and reset. When the operation is performed and the error state is released, an error command indicating the release of the error state is sent.

  The return command is a command indicating that the main control unit 41 has returned to the control state before power interruption, and is transmitted when the main control unit 41 starts up and returns to the control state before power interruption. The setting command is a command indicating the start or end of the setting change state, and the setting value after the setting change, and the setting command indicating the start of the setting change state is transmitted at the time of transition to the setting change state. A setting command indicating the end of the setting change state and the setting value after the setting change is transmitted. Further, since the control state of the main control unit 41 is initialized along with the transition to the setting change state, it can be specified that the control state of the main control unit 41 is initialized by the setting command indicating the start of setting. . The setting confirmation command is a command indicating the start or end of the setting confirmation state, and when transitioning to the setting confirmation state, a setting confirmation command indicating the start of the setting confirmation is transmitted, and the setting confirmation end is indicated when the setting confirmation state is ended. A confirmation command is sent.

  The door command is a command indicating the detection state of the door open detection switch 25, that is, ON (open state) / OFF (closed state), and when a predetermined condition is satisfied (normally, the command queue is empty at the time of command transmission processing). Sent at a certain time).

  Among these commands, commands other than the door command are generated in the main processing and temporarily stored in the command queue provided in the RAM 41 c, and the normal command transmission processing of the timer interrupt processing (main) thereafter, the command transmission at power off Sent in processing. On the other hand, the door command is generated when no command is stored in the command queue in the normal command transmission process, temporarily stored in the command queue provided in the RAM 41 c, and transmitted in the normal command transmission process. Ru.

  Next, control of an effect performed by the sub control unit 91 based on a command that the main control unit 41 transmits to the sub control unit 91 will be described. When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91 c.

  The sub control unit 91 determines whether or not an unprocessed command is stored in the reception buffer in the timer interrupt process (sub), and if the unprocessed command is stored, the earliest of them is stored. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, the reel LED 55, etc. based on the control content registered in the control pattern table. Perform output control of various rendering devices. The control pattern table includes display patterns of the liquid crystal display 51 corresponding to command types, lighting modes of the rendering effect LEDs 52, output modes of the speakers 53 and 54, lighting modes of the reel LEDs 55, and the like for each of a plurality of types of effect patterns. The control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the control patterns of the control pattern table are registered in correspondence with the effect patterns set in the RAM 91 c in the game. Among them, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. As a result, an effect corresponding to the effect pattern and the progress of the game is performed.

  When the sub-control unit 91 newly receives a command during execution of an effect triggered by the reception of a certain command, the sub-control unit 91 cancels the effect based on the control pattern being executed, and the newly received command is An effect based on the corresponding control pattern is performed. That is, even when the effect is not finished to the end, when a new command is received, the effect being executed except for the case where the received new command is not a command that triggers a new effect is canceled and a new An effect based on a command will be executed.

  When the internal winning command is received, the effect pattern is selected at a selection rate according to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91 c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 displays the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the selection rate registered, one of the effect patterns is selected from the plurality of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91 c as the effect pattern of the game. Even if the same command is received, different control patterns are selected according to the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

  Also, whether the detection state of the door opening detection switch 25 has changed from OFF (closed state) to ON (open state) based on the detection state of the door opening detection switch 25 specified from the door command It is determined whether or not it is changed, and when it is changed from OFF (closed state) to ON (opened state), door open notification to notify that the front door 1b is open is executed.

  FIG. 5 is an address map of a memory area used by the main control unit 41. As shown in FIG. 5, the memory area used by the main control unit 41 includes memory areas (0000H to 7FFFH) allocated to the ROM 41b and memory areas (8000H to FFFFH) allocated to the RAM 41c.

  The memory area of the ROM 41b includes a program / data area (0000H to 26FFH) in which programs and fixed data are stored, a ROM comment area (2700H to 277FH) in which arbitrary data such as program title and version can be set, and The vector table area (2780H to 27A7H) in which the upper address of the subroutine of the CALLV instruction to be executed and the start address of the timer interrupt processing (main) are set, and the parameters for setting the internal function of the main control unit 41 as hardware Is set, and an unused area (2800H to 7FFFH) in which access is prohibited.

  The memory area of the RAM 41c is an internal function register area (9000H to 9000H) in which a usable area (8000H to 81FFH) usable as a work and a register group for controlling each function mounted on the main control unit 41 are stored. 9080H) and unused areas (8200H to 8FFFH, 9081H to FFFFH) in which access is prohibited.

  The parameters set in the HW parameter area in the ROM 41b include the final address (HPRGEND) of the ROM area used in the program / data area, the start address (HRAMSTAT) of the RAM area to be accessed and the final address (HRAMEND).

  FIG. 6 is an address map of a program / data area in the ROM 41 b of the main control unit 41 and an available area in the RAM 41 c.

  As shown in FIG. 6A, the program / data area in the ROM 41b is a game program area in which a game program related to the progress of a game is stored, a game data area in which game data used by the game program is stored, and It includes a use area 1, a non-play program area where a non-play program not related to the progress of a game is stored, a non-play data area where non-play data used by the non-play program is stored, and an unused area 2. .

  In addition, the progress of the game is to advance a series of processes constituting the game, and in the case of a slot machine, set the number of bets and enable the start of the game, start the game and rotate the reels. The steps of stopping the reel and deriving the display result, and advancing the step of imparting a value such as a medal according to the display result.

The game program area is allocated to 0000H to 097EH, the game data area is allocated to 097FH to 1256H , the non-game program area is allocated to 1380H to 1D 02H, and the non-game data area is allocated to 1D03H to 267DH. Further, an area ( 1257H to 137FH) between the game data area and the non-game program area is an unused area 1, and an area ( 267EH to 26FFH) of the program / data area in the ROM 41b after the non-game data area is It is considered as an unused area 2, and 0 is stored in all areas in the unused areas 1 and 2.

  As described above, the game program area related to the progress of the game and the non-game program not related to the progress of the game are separately allocated, and behind the storage area of the ROM 41b among the game program area and the non-program area An area before the allocated non-program area is allocated an unused area 1 of at least 16 bytes or more, so a game program area related to the progress of the game and a non-game program not related to the progress of the game Can be easily identified according to the difference in storage area.

  Also, while the game program area and the game data area, the non-game program area and the non-game data area are respectively allocated to continuous areas, the game program area and the game data area related to the progress of the game and the non-regardless of the progress of the game Because the game program and the non-game data area are allocated to the non-continuous area across the unused area 1 of at least 16 bytes or more, the game program area and the game data area pertaining to the progress of the game, and the progress of the game Non-play programs and non-play data areas that are not involved can be easily identified according to the difference in storage area.

  In the above description, the front and back of the storage area is the magnitude relationship of the address values assigned to the storage area, the smaller the address being the front and the larger the address the rear. Therefore, a storage area allocated later than one storage area corresponds to a storage area whose address value is larger than that of one storage area, and a storage area allocated ahead of one storage area. A storage area whose address value is smaller than that of one storage area corresponds to this.

  In addition, the game program may be allocated behind the non-game program area, and the unused area may be allocated in front of the game program allocated behind the non-game program area. A game program area related to the progress of the game and a non-game program not related to the progress of the game can be easily specified according to the difference in the storage area.

  In addition, the game program area and the non-game program area may be allocated to the adjacent areas across the unused area 1, and even with such a structure, a game program area related to the progress of the game Non-game programs that are not involved in the progress of the game can be easily identified according to the difference in storage area.

  In addition, since 0 values are stored in all areas in the unused areas 1 and 2 of the program / data area of the ROM 41b, the game program area and the game data area, the non-game program area and the non-game data, The unused areas 1 and 2 can be easily distinguished from each other, and the unauthorized areas 1 and 2 can be easily detected even when illegal data is stored.

  Incidentally, 1 may be stored in all areas in the unused areas 1 and 2 of the program / data area of the ROM 41b, and even in such a structure, the game program area and the game data area, and the non-game area The program area and the non-play data can be easily distinguished from the unused areas 1 and 2 and can be easily found out even if the unused areas 1 and 2 store illegal data. .

  The game program area and the non-game program area both start from an address (0H) of 0 having the same lower four digits when the address is expressed in binary, and the program / data area of the ROM 41b Among them, the game program area related to the progress of the game and the non-game program area not related to the progress of the game can be easily distinguished from the other areas.

  In addition, in both the gaming program area and the non-game program area, when the address is expressed in binary notation, not only the lower 4 digits start from the same address of 0, but also in hexadecimal expression, the lower 1 digit value. Since it starts from the same address of 0 (0H), the game program area and the non-game program area can be easily distinguished from other areas not only when the address is expressed in binary but also when expressed in hexadecimal. can do.

  In addition, regardless of whether the game program area and the non-game program area both represent addresses in binary notation or hexadecimal notation, the lower N (N is a natural number of 1 or more) digits start from an address having the same value. It is possible to easily distinguish the game program area and the non-game program area from other areas, for example, the lower N (N is a natural number of 1 or more) digits have the same value 1 The same effect can be obtained with the configuration starting from the address of.

  As shown in FIG. 6B, the usable area of the RAM 41c is a game RAM area used as a work by a game program, an unused area 3, a non-game RAM area used as a work by a non-game program, and an unused area. 4 and the stack area.

  The game RAM area is allocated to 8000H to 805 BH, the non-game RAM area is allocated to 8070 H to 814 CH, and the stack area is allocated to 8170 H to 81 FFH. In addition, the area between the gaming RAM area and the non-gaming RAM area (805CH to 806FH) and the area between the non-gaming RAM area and the stack area (814DH to 816FH) are respectively used as unused areas 3 and 4 and unused. In the areas 3 and 4, 0 is stored in all the areas. Further, in the stack area, the stack pointer (SP) to 81 FFH is the in-use stack area, and the other 816 FH to SP is the unused stack area. As described above, the game RAM area used as a work by the game program and the non-game RAM area used as a work by the non-game program are allocated to areas not continuous across the unused area 3 of at least 16 bytes.

  As described above, since the game RAM area and the non-game RAM area are allocated to the non-consecutive areas across the unused area 3 of at least 16 bytes or more, the game RAM area used by the game program related to the progress of the game The non-game RAM area used by the non-game program not related to the progress of the game can be easily specified according to the difference of the storage area.

  In the following, the game program area, the game data area and the game RAM area may be collectively referred to as a game area, and the non game program area, the non game data area and the non game RAM area may be collectively referred to as a non game area. . In addition, the unused area 1 and the unused area 2, the unused area 3 and the unused area 4 may be collectively referred to as an unused area.

  The main control unit 41 sets an area (game program area, game area, etc.) from the top address (0000H) of the program / data area of the ROM 41b to the address (267DH) set to HPRGEND based on the parameters set in the HW parameter area. Access to data area, unused area 1, non-playing program area, non-playing data area) is collectively set to permission, and the area between address (267EH) and address 26FFH after the address (267DH) set in HPRGEND Set access to (unused area 2) to be prohibited. Also, based on the parameters set in the HW parameter area, an area (game RAM area, unused area 3) from the start address (8000H) of the usable area of the RAM 41c to the address before the address (814DH) set in HRAMSTAT. , Access to the area (stack area) from the address (8170H) to the address 81FFH after the address (816FH) set in HRAMEND, non-play RAM area), and the address set in HRAMSTAT (814DH) Access to the area (unused area 4) between the addresses (816FH) set in H. to HRAMEND are prohibited. The access to the area other than the program / data area in the ROM 41b and the access to the area other than the usable area in the RAM 41c are uniformly set to prohibited.

  When the main control unit 41 accesses the unused area 2 between the address (267FH) and the 26FFH after the address (267EH) set to the HPRGEND in the program / data area of the ROM 41b, the main control unit 41 When there is an access to an area other than the program / data area, to the unused area 4 between the address (814 DH) set in HRAMSTAT and the address (816 FH) set in HRAMEND among the usable areas of the RAM 41 c. When an access is made to an area other than the available area in the RAM 41c, it is determined that the access is illegal and an illegal access reset is generated. When an illegal access reset occurs, the game is controlled to a special error state, which will be described later, and the progress of the game is disabled, and the setting change state is entered, and the setting is not canceled until the setting value is newly set.

  As described above, when the main control unit 41 accesses the area where the access is inhibited in the program / data area of the ROM 41b based on the parameter set in the HW parameter area, the main control section 41 out of the usable area of the RAM 41c. When there is access to an area where access is not set to permission, when there is access to an area other than program / data area in ROM 41b, there is access to an area other than usable area in RAM 41c. When there is an access to a memory area that can not be accessed in normal operation, that is, an illegal access reset is generated to disable the progress of the game, so there are unused areas and operations of the ROM 41b. An illegal program is not included in the area not related, the unused area of the RAM 41c, etc. Even if it is possible to prevent the illegal program from being executed.

  Particularly, in the present embodiment, the gaming program area and the non-gaming program area are allocated to the program / data area of the ROM 41b to which access is permitted by the program, and before the non-gaming program area behind the gaming program area. Unused area 1 is allocated to the area, and a group of areas including the head address of the gaming program area to the final address of the non-gaming program in the program / data area based on the parameters set in the HW parameter area While the access to the area (the area from the game program area to the non-game data area) is collectively set to permission, the game program or game data in the other areas, that is, the program / data area, the non-game program, Non-play data not stored non- Because it is forbidden access to the area later than trick data, it is possible to prevent conducted unintended control by malware or illegal data.

  Further, in the program / data area of the ROM 41b where access is permitted by the program, the game area is allocated behind the non-game program area, and an unused area in the area before the game program area behind the non-game program area. Is allocated, and based on the parameters set in the HW parameter area, batch access to a group of areas including the area from the top address of the non-gaming program area to the final address of the gaming program in the program / data area Even if the access to the other area is prohibited, it is possible to prevent the unintended control by the illegal program or the illegal data.

  In the present embodiment, based on the parameters set in the HW parameter area, a group of areas including the area from the head address of the game program area to the final address of the non-game program in the program / data area Access to the area from the area to the non-game data area is collectively set to permission, but the game program area and the non-game program area are allocated to the program / data area, and from the game program area Unused area 1 is allocated to the area before the non-game program area behind, and one area (a game program area to the game data area) including the game program area in the program / data area, the non-game area A single area containing game programs (non-game program area Access to the area to the non-gaming data area may be set as permission, and access to other areas may be prohibited. Even in such a configuration, the game program in the program / data area may be set. Also, since the access to the area where the non-gaming program is not stored is prohibited, it is possible to prevent the unintended control by the illegal program or the illegal data being performed. Further, in the program / data area of the ROM 41b where access is permitted by the program, the game area is allocated behind the non-game program area, and an unused area in the area before the game program area behind the non-game program area. Of the program / data area including the gaming program area (the area from the gaming program area to the gaming data area) and the one area including the non-game program (non-gaming program area) Access to the area to the data area may be set to permit, and access to other areas may be prohibited. Even in such a configuration, a game program or non-game in the program / data area may be set. Access to the area where the program is not stored Because There is inhibited, it is possible to prevent conducted unintended control by malware or illegal data.

  Also, in the above description, although the area itself for permitting access in the program / data area is set, the area for indirectly permitting access is set by setting the area for prohibiting access in the program / data area. It is good also as composition which is done.

  The main control unit 41 sets an area from the address (0000H) set in IATSTAT1 to the address (097EH) set in IATEND1 in the program / data area of the ROM 41b based on the parameters set in the HW parameter area (game Program area) The area (non game program area) from the address (1380H) set in IATSTAT2 to the address (1D02H) set in IATEND2 is set as a designated area where the IAT circuit 506a permits program travel.

  Then, the IAT circuit 506a is set to an area (game program area) from an address (0000H) set to IATSTAT1 to an address (097EH) set to IATEND1, and is set to IATEND2 from an address (1380H) set to IATSTAT2. The area up to the address (1D02H) (non-gaming program area), that is, the area other than the designated area for permitting program travel (a game data area in the program / data area of the ROM 41b, non-gaming data area, unused area 1, 2 When a user program is executed in an area other than the program / data area of the ROM 41b, an IAT generation signal is output. Then, when the IAT generation signal is output, the CPU 41a is controlled to a special error state to be described later, and while the progress of the game is disabled, the CPU 41a shifts to the setting change state, and a new setting value is set. It is designed not to be released.

  Thus, when the user program is executed in an area other than the designated area for permitting program travel based on the parameters set in the HW parameter area, the main control section 41 executes the user program in a normal operation. Since the IAT circuit 506a disables the progress of the game by outputting an IAT generation signal when the user program is executed in an area where there is no event, the area not related to the unused area or the operation of the ROM 41b, Even when an unauthorized program is stored in an unused area or the like of the RAM 41c, the unauthorized program can be prevented from being executed.

  Particularly, in the present embodiment, the gaming program area and the non-gaming program area are allocated to the program / data area of the ROM 41b to which access is permitted by the program, and before the non-gaming program area behind the gaming program area. Unused area 1 is allocated to the area, and IAT circuit 506a permits program travel for each of the game program area and the non-game program area in the program / data area based on the parameters set in the HW parameter area. While it is set as a designated area, program running is prohibited in other areas, that is, areas of the program / data area where game programs and non-game programs are not stored, and thus unintended due to illegal programs or illegal data Control is line It can be prevented been.

  Further, in the program / data area of the ROM 41b where access is permitted by the program, the game area is allocated behind the non-game program area, and an unused area in the area before the game program area behind the non-game program area. Is set, and based on the parameters set in the HW parameter area, the IAT circuit 506a sets the designated area for permitting program travel for each of the game program area and the non-game program area in the program / data area. Thus, even if the program running in other areas is prohibited, it is possible to prevent the unintended control due to the illegal program or the illegal data being performed.

  In this embodiment, based on the parameters set in the HW parameter area, the IAT circuit 506a is set as a designated area for permitting program travel for each of the game program area and the non-game program area in the program / data area. The game program area and the non-game program area are allocated to the program / data area, and the unused area 1 is allocated to the area in front of the non-game program area behind the game program area. , HW parameter area based on the parameters, in the program / data area a single area including the area from the top address of the gaming program area to the final address of the non-gaming program (from the gaming program area to the non-gaming data area Area), I The T circuit 506a may be collectively set as a designated area for permitting program travel, and program travel in other areas may be prohibited. Even in such a configuration, the game in the program / data area may be played. Since program running in an area where a program or non-game program is not stored is prohibited, it is possible to prevent an unintended control by an unauthorized program or unauthorized data being performed. Further, in the program / data area of the ROM 41b where access is permitted by the program, the game area is allocated behind the non-game program area, and an unused area in the area before the game program area behind the non-game program area. Of the program / data area including the area from the top address of the non-gaming program area to the final address of the gaming program based on the parameters set in the HW parameter area (from the gaming program area Even if the IAT circuit 506a collectively sets a designated area for permitting program travel with respect to the area to the non-gaming data area) and program travel in other areas is prohibited, the illegal program or data may be generated. Unintended control line It can be prevented been.

  In the above description, although the program / data area is configured to set the area for permitting program travel itself, program travel is indirectly permitted by setting the area for prohibiting program travel in the program / data area. An area may be set.

  Among the gaming programs stored in the ROM 41b, the particularly frequently used subroutine is stored in the gaming program area of the ROM 41b in an area where the top address is a specific value (for example, 08H). On the other hand, in the vector table area of the ROM 41b, a specific value is set as an upper address of a subroutine called by the CALLV instruction. Then, when the main control unit 41 calls a subroutine in which the upper address of the start address has a specific value, only the lower address is specified using the CALLV instruction to set the specific value set in the vector table area as the upper address. The lower address specified as the lower address is specified, and the subroutine stored in the upper and lower addresses is called and executed. For this reason, the high-order address which forms a part of the address used when calling the particularly frequently used subroutine among the game programs is set in advance as a specific value in the vector table, and based on the specific value set in the vector table. Since the addresses are specified, it is possible to reduce the waste of the program for specifying the addresses when calling these subroutines.

  Among the non-gaming programs stored in the ROM 41b, a particularly frequently used subroutine is stored in an area where the top address becomes a specific value in the non-gaming program area of the ROM 41b, and a CALLV instruction is executed in the vector table area of the ROM 41b. These subroutines are specified by setting a specific value as the high-order address of the subroutine to be called in, and specifying only the low-order address using the CALLV instruction when the main control unit 41 calls the subroutine where the high-order address of the top address becomes the specific value. Even when the system is configured to call and execute, it is possible to reduce the waste of a program for specifying an address when calling these subroutines.

  Further, the upper address used when calling by the CALLV instruction may be set to a specific register of the main control unit 41 instead of the vector table area.

  Among the game data stored in the ROM 41b, particularly frequently used game data is stored in the game data area of the ROM 41b in the area where the top address is a specific value, and in the vector table area of the ROM 41b, a special LD By setting a specific value as the upper address of the data to be read out by the command, and when the main control unit 41 calls game data in which the upper address of the top address becomes the specific value, only the lower address is specified using a special LD command. Even in the case of reading out these game data, it is possible to reduce the waste of a program for specifying an address when reading out these game data.

  In addition, non-gaming data that is particularly frequently used among the non-gaming data stored in the ROM 41b is stored in an area where the top address becomes a specific value in the non-gaming data area of the ROM 41b, and in the vector table area of the ROM 41b. When a special value is set as the upper address of data to be read by a special LD command, and the main control unit 41 calls non-gaming data in which the upper address of the top address becomes the specific value, only the lower address is used using the special LD command. By designating, even when the non-play data is read out, it is possible to reduce the waste of a program for designating an address when the non-play data is read out.

  Even in these cases, the upper address used when calling by a special LD instruction may be set to a specific register of the main control unit 41 instead of the vector table area.

  The main control unit 41 is activated by the occurrence of a system reset by the input of a system reset signal, the WDT reset by the WDT 506b, and the above-mentioned illegal access reset. At this time, the value set in the vector table area Is a value indicating the area of the address set in 0000H to HPRGEND, that is, the area where the program etc. is actually stored in the program area, or FFFFH (value set in an unused vector table area) It is determined whether there is any, and if the value set in the vector table area is neither the value indicating the area of the address set in 0000H to HPRGEND nor FFFFH, the activation is not performed.

  As described above, the main control unit 41 indicates that the value set in the vector table area, that is, the upper address of the subroutine of the CALLV instruction described later and the start address of the timer interrupt processing (main) indicate outside the area where the program is set. By not activating in the case of the value, it is possible to prevent in advance the execution of an originally unintended process due to the occurrence of an interrupt or the like.

  The game program is a program relating to the progress of the game as described above, and is a program for executing a process that hinders the progress of the game unless the process based on the program is executed.

  On the other hand, the non-game program is a program not involved in the progress of the game as described above, and even when the game program is called and the processing based on the program is not executed, the game is progressed. Is a program for performing processing that can be performed.

  As shown in FIG. 7, the game program includes a game dedicated program included only in the game program, and a common determination program and a common general purpose program included in both the game program and the non-game program.

  The game dedicated program includes, for example, a BET process, an internal lottery process, a reel rotation process, a payout process, and an external output 1 process. The bet process is a process for starting the game by operating the start switch 7 after the bet number is set by inserting a medal or the like after the control of one game is finished and the bet number of the specified number is set. The internal lottery process is a process of performing an internal lottery and setting a winning flag, etc. The reel rotation process starts the rotation of the reel and operates the stop switches 8L, 8C, and 8R. The payout process determines whether or not a prize has occurred according to the stop position of the stopped reel, and pays out medals, sets replay, changes the gaming state, etc. The external output 1 process is a process for controlling the output of the medal IN signal, the medal OUT signal, the in-RB signal, the in-BB signal, and the in-RT signal among the external output signals. Although not particularly illustrated, the game program also includes the processing related to the above-mentioned AT (control for lottery and navigation notification according to AT, etc.) and the processing for transmitting the above-mentioned internal winning command.

  The common determination program in the game program includes, for example, an insertion determination process and a payout determination process. The insertion determination process is a process of determining whether or not the medals are normally passed by the inserted medal sensor 31, and is a process executed in a state in which medals can be inserted for setting the number of bets and the like. The payout determination process is a process of determining whether or not the medal passes normally by the payout sensor 34c, and is a process performed in a state where payout of medals is permitted at the time of winning a small winning combination or settlement of credits. It is.

  The common general-purpose program in the game program is a process called and executed from a plurality of types of processes constituting the game program, and, for example, counter update process, port input process, data conversion process, LED display process, data setting process, Includes command setting processing. The counter update process is a process for updating the designated counter value, the port input process is a process for acquiring the input state of the designated port, and the data conversion process is input using game data. The LED display process is a process of converting the data to be output, the LED display process is a process of setting a designated value to be displayed on the LED, and the data setting process is a process of setting the designated data. The command setting process is a process of setting a designated command in a command queue.

  As shown in FIG. 7, the non-gaming program includes a non-gaming exclusive program included only in the non-gaming program, and a common determination program and a common general-purpose program that are the same as the gaming program.

  The non-game dedicated program includes, for example, test signal output processing, foreign object detection processing, door monitoring processing, external output 2 processing, inserted medal error determination processing, payout medal error determination processing, activation processing, set value abnormality confirmation processing, error processing Including. The test signal output process is a process for outputting a test signal generated in association with the game result, and the foreign matter detection process is a process for detecting a foreign matter in the medal passage by the insertion port sensor 26, The door monitoring process is a process for detecting the opening of the front door 1b, and the external output 2 process is a process of the security signal (door opening signal, setting change signal, closing error signal, payout error signal) among the external output signals. It is a process for performing output control, and the inserted medal error determination process detects the backflow of the inserted medal, detects the clogging of the medal in the medal selector 29, and detects the foreign matter in the medal selector 29 based on the detection condition of the inserted medal sensor 31. The payout medal error determination process is based on the detection condition of the payout sensor 34c, detects the backflow of the payout medal, and clogs the medal near the payout opening. This is a process to detect foreign objects near the payout port, and the startup process is a process to make the game possible when power is turned on (random error check, RAM error check, backup error check, register initialization Etc., and the set value abnormality confirmation process is a process for determining whether or not the set value is a value in a normal range, and the error process includes various types of Detection of foreign objects in the room, reel rotation error, medal payout error, foreign object detection near the payout outlet, RAM error, setting error, empty hopper tank 34a, overflow tank 35 full detection, etc. Is a process to disable the

  The common general-purpose program in the non-gaming program is a process called and executed from a plurality of types of processes constituting the non-gaming program, and, like the common general-purpose program in the gaming program, for example, counter update processing, port input processing, It includes data conversion processing, LED display processing, data setting processing, and command setting processing.

  In particular, in the non-game program, when the abnormality is detected as described above, the release condition according to the type of abnormality (random number abnormality, RAM abnormality, backup abnormality, setting value reset in the case of setting value abnormality, In the case of other abnormalities, it includes an error process that disables the progress of the game until the reset operation is established.

  Further, the non-game program includes a process of determining whether or not a predetermined detection condition is detected based on the detection condition of the detection means (the insertion port sensor 26, the full tank sensor 35a, the door opening detection switch 25) not involved in the progress of the game. .

  In addition, the non-game program functions as a detection means related to the progress of the game in a specific control state among a plurality of control states (BET processing, internal lottery processing, reel rotation processing, payout processing), and other control states Whether the detection means (for example, the inserted medal sensor 31 and the payout sensor 34c) functioning as the detection means not involved in the progress of the game is a predetermined detection state based on the detection situation in the control state not involved in the progress of the game A process of determining whether or not it is included (for example, a process of detecting an inserted medal or a process of detecting a paid-out medal for detecting an abnormality due to the insertion of a medal during reel rotation or the discharge of a medal is detected). In addition, since such determination processing is the same processing as processing to determine whether or not a predetermined detection status is based on the detection status in the control state related to the progress of the game in the game program, it corresponds to the common determination program .

  Among the processes included in the game program, an external output 1 process, a process of counting the number of medals inserted in the BET process, a process of switching the flow path switching solenoid 30, a process of counting the number of medals dispensed in the payout process, hopper A process of detecting that the tank 34a is empty, a process of updating software random numbers, a process related to AT, a process of transmitting an internal winning command, and the like, if not directly related to the progress of the game. All or part of the processing may be included in the non-game program. On the other hand, if the processing included in the non-game program is indirectly related to the progress of the game, such as activation processing, setting value abnormality confirmation processing, etc., all or part of these processing is included in the game program It may be

  In the present embodiment, as shown in FIG. 8, the CPU 41a of the main control unit 41 calls a non-gaming program in the processing based on the gaming program and executes the processing based on the non-gaming program, and after the processing based on the non-gaming program is finished , Return to the processing based on the game program.

  As shown in FIG. 9, when the non-gaming program is called from the processing based on the gaming program, the CPU 41a uses the arithmetic registers (A, F, BC, DE, etc.) used for computation at the beginning of the non-gaming program. All the values of the HL register, hereinafter, the register for operation are simply referred to as a register) are saved in the stack area to protect the data used by the game program. Then, after all the processing based on the non-game program is finished, the value saved in the stack area is returned to the register, and thereafter, the processing based on the game program is returned.

  In this embodiment, the value of the register used by the game program is protected by saving it to the stack area, but the game program is used by changing the values of the front register and the back register. Alternatively, the value of the register may be protected.

  Further, in the present embodiment, when the non-gaming program is called from the processing based on the gaming program, the value of the register used by the gaming program is protected at the beginning of the non-gaming program, and the last of the non-gaming program is Although the value of the protected register is restored, the value of the register used by the gaming program immediately before calling the non-gaming program from the processing based on the gaming program is protected, and the processing based on the non-gaming program is all After termination, the configuration of restoring the value of the protected register at the initial stage of returning to the game program, and when calling the non-game program from the processing based on the game program, the game program is the first of the non-game programs. After protecting the value of the used register, after all processing based on non-gaming program is finished The structure of restoring the value of the protected register at the initial stage of returning to the game program, protects the value of the register used by the game program immediately before calling the non-game program from the processing based on the game program, At the end of the game program, the value of the protected register may be restored.

  As shown in FIG. 8, in executing the processing based on the gaming program in principle, the CPU 41a refers to the gaming data in the gaming data area to execute the processing based on the gaming program and uses the gaming RAM area as a work. It is possible to refer to and update the contents of the game RAM area. Further, when executing the processing based on the non-gaming program in principle, the CPU 41a refers to the gaming data of the non-gaming data area to execute the processing based on the non-gaming program and uses the non-gaming RAM area as a work. It is possible to refer to and update the contents of the non-play RAM area.

  Further, when executing processing based on the gaming program, the CPU 41a does not refer to the non-gaming data area and does not update the non-gaming RAM area, but can refer to the non-gaming RAM area When performing processing based on a non-gaming program, the gaming data area is not referred to, and the gaming RAM area is not updated, but it is possible to refer to the gaming RAM area.

  Further, the processing based on the game program can be referred to only a specific area required for the game program in the non-game RAM area (for example, a setting area of an error flag indicating detection of abnormality). In the processing based on this, reference can be made to only a specific area (for example, an internal winning flag setting area, a gaming state setting area, an RT setting area, etc.) required for the non-game program in the game RAM area. Further, in the non-gaming RAM area, a specific area to which processing based on the gaming program can be referred, and a specific area to which processing based on the non-gaming program can be referred to among the gaming RAM area may be allocated to continuous address areas. Although it is preferable, the configuration may be such that part or all of the addresses are allocated to non-consecutive address areas.

  However, RAM anomaly check, backup anomaly check, RAM 41c initialization, and power-off process to be described later in the boot process are included in the non-game program, but with the exception of these processes, it is possible to access the entire area of RAM 41c. It is done.

  As described above, in the present embodiment, a game program area in which a game program related to the progress of a game is stored, a game data area in which game data referred to by the game program is readably stored, and work data referred to by the game program Are a game RAM area stored so as to be readable and writable, a non-game program area where a non-game program which is called by a game program and which is not involved in the game progress is stored, and a non-game Since the non-gaming data area in which the data is readably stored and the non-gaming RAM area in which the work data to which the non-gaming program refers are stored so as to be readable and writable are separately allocated, Game data and work data of a game program, Game program, the workpiece data of the non game data and non-game program, can be easily identified according to a difference in the storage area.

  Also, by dividing the game program area and the game data area from the non-game program area and the non-game data area, the area occupied by the ROM 41b can be compactly managed according to the respective functions. It will be easier to identify the relevant data.

  Further, in the present embodiment, when executing the game program, it is possible to refer to the non-game RAM area, and when executing the non-game program, it is possible to refer to the game RAM area. When executing the game program, data used by the non-game program can be easily used, and when executing the non-game program, data used by the game program can be easily used. On the other hand, when executing the game program, it is impossible to update the non-game RAM area, and when executing the non-game program, it is impossible to update the game RAM area. The non-gaming program does not affect the processing of the gaming program, without affecting the processing of the non-gaming program.

  Further, in the present embodiment, the processing based on the game program can be referred to only the specific area required for the game program in the non-game RAM area (for example, the setting area of the error flag indicating detection of abnormality). The processing based on the non-gaming program can be referred to only the specific area required for the non-gaming program in the gaming RAM area (for example, the setting area of the internal winning flag, the setting area of the gaming state, the setting area of RT) Since the game program can refer to data that can be referred to in the non-game RAM area and data that can refer to the non-game program is restricted to a specific area, it is possible to easily identify the referent of the game program or the non-game program. be able to.

  Further, in the present embodiment, when the non-game program detects an abnormality, it includes an error process that disables the progress of the game until the release condition is satisfied according to the type of the abnormality, so the process in the non-game program It is possible to prevent the game from proceeding as it is when an abnormality or the like is detected.

  Further, in the present embodiment, since the non-game program includes the same common determination program as the common determination program (for example, insertion determination process, payout determination process) included in the game program, the game program and the non-game program mutually The same determination can be made without affecting the result of.

  Further, in the present embodiment, the non-game program is a process which is called and executed from a plurality of types of processes constituting the non-game program, and includes a common general-purpose program similar to the common general-purpose program included in the game program. Since the game program and the non-game program respectively have the same general-purpose program with the same process content, are they included in the game program or the non-game program even if they are the same general-purpose program? Can be easily identified.

  Further, in this embodiment, it is determined whether or not the non-game program is a predetermined detection condition based on the detection condition of the detection means (the insertion port sensor 26, the full tank sensor 35a, the door opening detection switch 25) not involved in the progress of the game. Since the determination process is included, the determination as to whether or not the predetermined detection has been made by the detection means that is not involved in the progress of the game is performed by the non-game program so that the game program will not be complicated.

  Further, in the present embodiment, the non-game program functions as a detection means related to the progress of the game in a specific control state among a plurality of control states (BET processing, internal lottery processing, reel rotation processing, payout processing). In other control states, detection means (for example, inserted medal sensor 31, payout sensor 34c) functioning as detection means not involved in the progress of the game is based on the detection status in the control state not involved in the progress of the game A process of determining whether or not a predetermined detection condition (for example, a process of detecting an inserted medal or a process of detecting a paid-out medal for detecting an abnormality due to the insertion of a medal during reel rotation or the detection of the medal's payout) Since it includes, in the situation where the detection result of the above-mentioned detection means is not used for the progress of a game, the judgment of whether predetermined detection was carried out by the detection means concerned is not a game By performed by programs, detection result of the detection means in terms of also using the detection results of the detecting means in a situation that is not used in the progress of the game, never game program becomes unnecessarily complex.

  Further, in this embodiment, when the game program calls a non-game program and executes a non-game program, all areas of the register are protected regardless of whether the game program is a register actually used or not. Since the processing to be performed is performed, when returning to the game program, it is possible to reliably return from the state at the time when the non-game program is called.

  Further, in the present embodiment, when the non-gaming program is called from the processing based on the gaming program, the value of the register used by the gaming program is protected at the beginning of the non-gaming program, and the last of the non-gaming program is Since the value of the protected register is restored, the capacity of the game program can be reduced.

  It should be noted that the value of the register used by the gaming program is protected immediately before calling the non-gaming program from the processing based on the gaming program, and at the first stage after returning to the gaming program after all the processing based on the non-gaming program is finished. The value of the protected register may be restored. With this configuration, the register protection process is performed before calling the non-game program, and the register recovery process is performed after the non-game program is restored. Therefore, the data stored in the register by the non-gaming program does not affect the gaming program.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described below based on FIGS.

  When activated by the occurrence of a reset, the main control unit 41 sets the activation time. In the startup setting, the status flag provided in the main control unit 41 is initialized. The status flag is data for holding the operation result of the instruction and the state of the execution result, and particularly includes an interrupt master permission flag for setting the inhibition / permission of the interrupt. Since the initial value of the interrupt master permission flag is a value indicating that the interrupt is prohibited, the main control unit 41 is activated in the state in which the interrupt is prohibited.

  Thereafter, after setting various functions with reference to the HW parameter, the main control unit 41 performs the initial setting process shown in the flowchart of FIG. 10 according to the program stored in the program / data area. In the initial setting process, first, the value of the interrupt master permission flag is set to a value indicating that the interrupt is prohibited, so that the interrupt is prohibited (Sa1). As described above, the main control unit 41 is activated in the interrupt inhibited state, but in Sa1, the interrupt is inhibited again. Next, initialization data is set (Sa2), and each output port including the parallel output port 513 is initialized (Sa3). Next, the built-in register is set (Sa4).

  Next, it is determined whether the power supply voltage is normal (Sa5). If the power supply voltage is not normal, the determination is repeated until it becomes normal. If the power supply voltage is normal, the upper address of the interrupt vector is set (Sa6). Then, access to the RAM 41c is permitted (Sa7), and the stack pointer is initialized (Sa8).

  Next, RAM parity (hereinafter referred to as RAM parity 1) of all areas (including unused area 3) of the game RAM area of RAM 41c and RAM of all areas (including unused area 4) of the non-game RAM area Parity (hereinafter referred to as RAM parity 2) and RAM parity (hereinafter referred to as RAM parity 3) of the stack area (unused stack area and used stack area) are calculated (Sa9). Then, it is determined whether the calculated RAM parity 1 to 3 is 0 (Sa10). As will be described later, if power interruption processing (main) is normally performed at the previous power shutoff, RAM parity 1 to 3 should all be 0, so in step Sd10, RAM parity 1 to 3 is performed. If any one is not 0, the data stored in the RAM 41c is not normal. In this case, the process proceeds to the step of Sa14, and the data for destruction diagnosis is cleared (Sa14). On the other hand, if all of the RAM parity 1 to 3 become 0, then the destruction diagnostic data 1 stored in the game RAM area, the destruction diagnostic data 2 stored in the non-game RAM area, and the stack area Acquire the stored data for destruction diagnosis 3 (Sa11), determine whether the acquired data for destruction diagnosis 1 to 3 is correct (Sa12), and clear the data for destruction diagnosis 1 to 3 (Sa13) .

  Next, it is determined whether the setting key switch 37 is in the ON state (Sa14). When the setting key switch 37 is in the ON state, timer interrupt setting is performed (Sa19). Specifically, the setting of the register of the timer circuit 509 incorporated in the main control unit 41 is performed so that the timer interrupt is periodically executed at predetermined time intervals. In this embodiment, by setting a value corresponding to about 0.56 ms in a predetermined register (time constant register), a timer interrupt is periodically generated every about 0.56 ms. Further, in the timer circuit 509, the setting of the register is performed to initialize the timer and start time counting from the initial value. When the setting of the timer interrupt in step Sa19 is completed, the process shifts to setting change processing.

  On the other hand, when the setting key switch 37 is in the OFF state, it is determined whether the storage content of the RAM 41c is destroyed (Sa15). In the step of Sa15, it is determined whether or not the RAM abnormality flag described later is set, and whether or not the storage content of the RAM 41c is destroyed based on the determination of Sa10 and Sa12. If the storage content of the RAM 41c is not destroyed, a return command is sent to the sub control unit 91 (Sa16). In the case where the storage contents of the RAM 41c are not destroyed, it is determined that the RAM abnormality flag is not set, and the RAM parity 1 to 3 are all 0 in the step of Sa10, and further in the step of Sa12. It is a case where it is determined that all of the destruction diagnostic data 1 to 3 are correct.

  After the step of Sa16, all the registers are restored (Sa17), and the same timer interrupt setting as the step of Sa19 is performed (Sa18). Then, the process shifts to the process of Sd24 of the timer interrupt process (main) described later. As a result, the processing being executed before the power failure is restored.

  Also, if the storage content of the RAM 41c is destroyed in the step of Sa15, the start address (0000h) of the RAM is set in the register (Sa20), and from the designated address to the final address (0FFFh) of the usable area The area, ie, all areas of the usable area are initialized (Sa21).

  Next, a RAM abnormality flag indicating that the storage content of the RAM 41c is not normal is set in the RAM 41c (Sa22), and the process shifts to error processing. In the error processing, the progress of the game is disabled. Further, in the error state where the RAM abnormality flag is set and shifted, the setting key switch 37 can be turned on and the power switch 39 can be turned on, whereby the setting change processing can be canceled. On the other hand, when the power switch 39 is turned on without turning on the setting key switch 37, the RAM abnormality flag remains set, and an error state occurs again.

  Next, setting change processing executed by the main control unit 41 will be described.

  As shown in FIG. 11, the main control unit 41 first sets the start address (0000h) of the RAM in the register (Sb1). Next, as in the step of Sa15 shown in FIG. 10, it is determined whether the stored contents of the RAM 41c are destroyed (Sb2). If the contents of the RAM are not destroyed, that is, if the contents of the RAM are not abnormal, the start address of the RAM to be initialized at the start of the setting change is set in the register (Sb3). That is, the address set in Sb1 is changed. If the content of the RAM is destroyed, that is, if the content of the RAM is abnormal, the process proceeds to the step of Sb4.

  Next, the area from the address designated in the step of Sb1 or Sb3 to the final address of the usable area is initialized (Sb4). In the step Sb1, the start address of the RAM is set. In this case, all the available areas are initialized in the step Sb4. On the other hand, in the step Sb3, the start address of the RAM to be initialized at the start of the setting change is set. In this case, in the step Sb4, the areas other than the important work and the special work among the usable areas are initialized. It will be done.

  Next, a setting command indicating the start of the setting change state is transmitted to the sub control unit 91 (Sb5), and the interrupt is permitted (Sb6).

  Next, it is determined whether the reset / setting switch 38 has changed from OFF to ON (Sb7). When the reset / setting switch 38 changes from OFF to ON, the set value of the register is updated (1 is added in the case of 1 to 5 and updated to 1 in the case of 6) (Sb8). If the reset / setting switch 38 has not changed, it is determined whether the start switch 7 has changed from OFF to ON (Sb9). If the start switch 7 has not changed, the process returns to the step of Sb7. On the other hand, when the start switch 7 changes from OFF to ON, it is determined whether the setting key switch 37 is in the OFF state (Sb10). If the setting key switch 37 is not in the OFF state, the determination is repeated until the setting key switch 37 is in the OFF state. If the setting key switch 37 is off, data of the setting value set in the register is stored in the RAM 41c (Sb11).

  Next, a setting command indicating the end of the setting change state is transmitted to the sub control unit 91 (Sb12). Then, the start address of the initialization object RAM at the end of the setting change is set in the register (Sb13), and the processing shifts to the main processing.

  Next, the main processing performed by the main control unit 41 will be described. The main processing is repeatedly executed for each unit of game. And one cycle of the main processing corresponds to one unit of the game.

  As shown in FIG. 12, the main control unit 41 first prohibits an interrupt (Sc1). Next, the final address of the initialization target RAM is set (Sc2).

  Next, the area of the RAM indicated by the designated address is cleared (Sc3). At this time, if the main process is started after the setting change process, the start address of the initialization object RAM at the time of the setting change end is set, and the final address of the initialization object RAM at the setting change end is the step Sc2 Since the setting is made, an area other than the important work and the special work in the usable area is initialized. In addition, at the end of a game that is not the end of a specific gaming state, the start address of the initialization target RAM at the end of the game is set in the step of Sc10 described later, and in the step of Sc2, the initialization target RAM at the end of the game Since the final address of is set, the unused area and the unused stack area of the available area are initialized. In addition, at the end of the specific gaming state, and at the end of the game, the top address of the initialization target RAM at the end of the specific gaming state is set in the step of Sc11 described later, and in the step of Sc2, the specific Since the final address of the initialization target RAM at the end of the gaming state is set, the general area, the unused area and the unused stack area among the usable areas are initialized.

  After the initialization of the RAM in the step of Sc3, an interruption is permitted (Sc4), and a game start waiting process is executed (Sc5). In the game start waiting process, the bet number is waited in a settable state, a defined number of bets according to the game state is set, and the game is started when the start switch 7 is operated.

  Next, an internal lottery process is executed (Sc6). In the internal lottery process, whether to allow winning in each combination described above based on the random number value for internal lottery latched simultaneously with the game start by the detection of the start switch 7 in the step of Sc5 (that is, derivation of the display result) Perform processing to determine whether to allow or not.

  Next, the reel control process is executed (Sc7). In the reel control process, a process of rotating the respective reels 2L, 2C, 2R in response to the operation of the start switch 7, the result of the internal lottery in the step of Sd2 and the operation of the stop switches 8L, 8C, 8R by the player are detected A process of stopping the rotation of the corresponding reels 2L, 2C, 2R is executed according to the operation.

  Next, the game end setting process is executed (Sc8). In the game end setting process, when it is determined that the rotation of all the reels 2L, 2C, 2R has stopped in the process of Sc7, a prize is generated according to the display result derived to each reel 2L, 2C, 2R Execute processing to determine whether or not. When it is determined that a winning has occurred, processing such as addition of credits and payout of medals is performed based on the number of payouts corresponding to the winning. When a winning is generated, processing for setting the gaming state is performed in preparation for the next game after the payout of medals and the like is completed. In addition, when the prize does not occur, after the reel is stopped, processing for setting the gaming state in preparation for the next game is executed.

  When the game end setting process is completed, it is determined whether or not a specific game state is over (Sc 9). If it is not a specific game state over time, the start address of the initialization object RAM at the game end is used. Set (Sc10) and return to the step of Sc1. Further, if it is at the end of the specific gaming state, the start address of the initialization object RAM at the end of the specific gaming state is set (Sc11), and the process returns to the step Sc1.

  Also, in the main processing, command storage processing is performed that generates commands according to the progress of the game and sets them in the command queue, and the set commands are normally executed in the subsequent timer interrupt processing (main) It is transmitted to the sub control unit 91 by command transmission processing.

  FIGS. 13 and 14 are flowcharts showing control contents of timer interrupt processing (main) executed by the main control unit 41 by interrupting basic processing (main processing mainly) at a constant interval (about 0.56 ms interval). is there. The timer interrupt process (main) is a process executed by an interrupt generated according to the count of the timer circuit 509. The address at which the program of the timer interrupt process (main) is stored is the vector table. It is set as a value corresponding to the timer interrupt of. When a timer interrupt occurs, processing from the address is executed. Further, during the execution of the timer interrupt process (main), other interrupts are automatically inhibited.

  As shown in FIG. 13, in the timer interrupt process (main), first, the register in use is saved in the stack area (Sd1).

  Next, a power failure determination process is performed (Sd2). In the power failure determination process, it is determined whether or not the voltage drop signal is input from the power failure detection circuit 48. If the voltage drop signal is input, the voltage drop signal is also input in the previous power failure determination process. If a voltage drop signal is input even in the previous power failure determination process, it is determined that a power failure has occurred, and a power failure flag indicating that is set.

  After the power failure determination process in step Sd2, it is determined whether or not the power-off flag is set (Sd3). If the power-off flag is not set, the process proceeds to Sd4 and detection data of various switches from the input port Perform port input processing to input. On the other hand, when the power-off flag is set, after executing the command transmission processing upon power-off to transmit various commands set in the command queue to the sub control unit 91 (Sd19), the power-off processing (main) Migrate to

  Next, the branch counter for identifying a timer interrupt to be executed in the timer interrupt process (main) is advanced by one from the four types of timer interrupts 1 to 4 (Sd5). In the step Sd5, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process (main) is executed.

  Then, it determines whether it is 2 or 3 with reference to the branch counter value, that is, timer interrupt 3 or timer interrupt 4 (Sd6), and is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interruption 2, motor phase signal output processing is executed to output phase signal data of the reel motors 32C, 32C, 32R (Sd7).

  Next, it is determined whether or not it is 1 by referring to the branch counter value, that is, whether or not it is the timer interrupt 2 (Sd8), and in the case of not the timer interrupt 2, that is, in the case of the timer interrupt 1, the reel motor Reel start processing (Sd9) that controls step time interval at start of 32L, 32C, 32R, motor step processing (Sd10) that changes phase signal data of reel motor 32L, 32C, 32R, reel motor 32L, 32C After the motor 32R is stopped, a motor phase signal standby process (Sd11) is sequentially performed to change the phase signal to one-phase excitation after a predetermined time has elapsed, and then the process proceeds to step Sd24.

  When it is determined in step Sd8 that timer interruption 2 is performed, LED dynamic display processing (Sd12) for dynamically lighting various displays, and control for outputting data such as lighting signals of various LEDs to the output port Signal output processing (Sd13), time counter update processing for updating various time counters (Sd14), monitoring of detection status of door open detection switch 25, door monitoring processing for performing transmission request of door command (Sd15), command queue After the normal command transmission process (Sd16) for transmitting various commands set in the above to the sub control unit 91 and the external output signal update process (Sd17) for updating the external output signal are sequentially executed, the process proceeds to step Sd24.

  If it is determined in step Sd6 that the timer interrupt 3 or the timer interrupt 4 is present, it is further determined whether the branch counter value is 3 or not, that is, whether or not the timer interrupt 4 (Sd18), If it is not timer interruption 4, that is, if it is timer interruption 3, the origin passing process (Sd19) for checking passing of the origin of the rotating reels 2L, 2C, 2R (passing of the reel reference position) (Sd19) After sequentially executing switch input determination processing (Sd20) for determining whether or not there is a change in the detection state, the process proceeds to step Sd24.

  If it is determined in step Sd18 that timer interruption 4 is to be performed, stop switch processing (Sd21) for determining the stop position according to the detection of the stop switches 8L, 8C, 8R, and two phases when it is time to stop After the stop process (Sd22) for starting the brake by excitation and the final stop process (Sd23) for three-phase excitation after a predetermined time since the start of the brake in the stop process, the process proceeds to step Sd24.

  In step Sd24, the register saved in the stack area in Sd1 is restored, and the process returns to the process before the interrupt.

  As described above, in the present embodiment, the main control unit 41 is activated in the interrupt disabled state when the reset occurs, and then the program is also interrupted at the start of the initial setting process to be executed first. Even when the main control unit 41 is activated in a state in which the interruption is not prohibited for some reason, it is possible to prevent an unintended interruption from occurring.

  Further, after the start, the main control unit 41 permits interruption after setting of the timer interruption in the timer circuit 509, and the interruption occurs when the timer interruption does not operate normally. Can be prevented. The timer circuit 509 performs timer interrupt setting to initialize the timer and start timing from the initial value, and the time from the start until the first interrupt occurs is The time until the occurrence of the second and subsequent interrupts does not deviate, and timer interrupts can be generated at fixed time intervals. Further, the main control unit 41 is configured to update the setting of the timer circuit 509 to an initial value by a program in the initial setting process, and the setting of the timer circuit 509 is rewritten due to some reason at the time of activation. Even if there is, it is possible to prevent an unintended interruption from occurring.

  Further, when the setting key switch 37 is in the ON state at the time of activation, the main control unit 41 shifts to setting change processing, and initializes the RAM 41 c at the start of the setting change processing. At this time, if the data in the RAM 41c is normal, the important work and the special work are held and the other areas are initialized, so that the control state (such as the setting value and the game state) before the change even after the setting change While it is possible to hold a part, if the data in RAM 41c is not normal, initialize all areas in the usable area including the important work and the special work to ensure that the data in RAM 41c is abnormal. It can be eliminated.

  In addition, since the RAM abnormal flag is set when the RAM abnormal state is determined, the main control unit 41 is turned off after the occurrence of the RAM abnormal error, and the RAM parity is 0 when the power is turned on again. Even if it is determined that the destruction diagnostic data is normal, it is possible to determine whether the data in the RAM 41c is destroyed based on the RAM abnormality flag.

  Further, after the setting change process is completed, the main control unit 41 executes a main process in which the process is performed step by step according to the progress of the game for each gaming unit. Further, in the main processing, the RAM 41c is initialized for each gaming unit, and the RAM 41c is also initialized at the end of the setting change processing. Then, after the setting change process is finished, the main process is started from the stage before the process of initializing the RAM 41c in the main process, the initialization of the RAM 41c after the setting change process is finished, and the gaming unit It is possible to perform initialization of each RAM 41c by common processing.

  Further, when initializing the RAM 41c, the main control unit 41 prohibits interrupts until the initialization is completed, and the timer interrupt process (main) is performed while the initialization of the RAM 41c is being executed. By being generated, it is possible to prevent that the contents of initialization are changed or the process performed in the timer interrupt process (main) is not normally performed.

  Further, the main control unit 41 updates the output state of the external output signal in the main processing, and changes the output state of the external output signal in the subsequent timer interrupt processing (main) based on the updated output state. At the same time, when updating the output state of the external output signal, interrupts are inhibited until the update is completed, and timer interrupt processing (main) occurs before the output state of the external output signal is completed. By doing this, it is possible to prevent an external output signal indicating unintended data from being output.

  The main control unit 41 of this embodiment generates a command according to the progress of the game in the setting change process and the main process described above, stores the generated command in the command queue, and performs normal operation in the timer interrupt process (main) Each time command transmission processing is executed, the unsent command stored in the command queue is transmitted to the sub control unit 91.

  FIG. 15 is a flowchart showing control contents of command storage processing executed when the various commands generated by the main control unit 41 are stored in the command queue. The command transmitted by the main control unit 41 is composed of 2 bytes, the first byte indicates MODE (classification of command), and the second byte indicates EXT (content of command). Also, the form of the command shown in the present embodiment is an example, and other data forms may be used. Further, in the present embodiment, the command is configured by 2-byte signals, but these commands may be configured by 1-byte signals or signals of 3 bytes or more.

  In the command storage process, first, MODE and EXT that constitute a command to be transmitted are generated (Se1). Then, after MODE and EXT of the generated command are stored in the area of the area number indicated by the storage pointer, that is, in the free area of the command queue (Se2), 1 is added to the area number indicated by the storage pointer (Se3). Since the area number is a numerical value in the range of 0 to 31, 1 is added when the serial number indicated by the storage pointer is 31, and is updated to 0 when it is 32.

  Next, it is checked whether the unsent flag is set (Se4), and if the unsent flag is not set, the unsent flag is set (Se5). Then, it is checked whether the area number indicated by the storage pointer matches the area number indicated by the transmission pointer, that is, whether all areas of the command queue are full with unsent commands, If not, it waits until the unsent command stored in the command queue is sent and the area number indicated by the storage pointer does not match the area number indicated by the transmission pointer, and the area number indicated by the storage pointer And when the area number indicated by the transmission pointer no longer matches, that is, when the command queue is free, the command storage processing is terminated (Se6).

  FIG. 16 is a control of normal command transmission processing executed in the timer interrupt 2 of the timer interrupt processing (main) described above for the main control unit 41 to transmit the command stored in the command queue by the command storage processing. It is a flowchart which shows the content.

  In the normal-time command transmission process, first, it is checked whether the unsent flag is set, that is, whether the unsent command is stored in the command queue (Sf1), and the unsent flag is not set. In this case, the detection status of the door open detection switch 25 is acquired to generate MODE and EXT constituting a door command, and the generated MODE and EXT are stored in the area number area indicated by the storage pointer, that is, the free area of the command queue. Store (Sf2, Sf3).

  If it is determined in step Sf1 that the unsent flag is set, and after MODE and EXT constituting the door command are stored in the command queue in steps Sf2 and Sf3, an area indicated by the transmission pointer value of the command queue The command stored in is transmitted to the sub control unit 91 (Sf4 to Sf7). Specifically, first, the MODE that constitutes the command stored in the area indicated by the transmission pointer value of the command queue is output (Sf4), and a strobe signal for notifying the sub control unit 91 that the command has been output is given for a predetermined time (In this embodiment, 10 μs) is output (Sf5). Then, the EXT that constitutes the command stored in the area indicated by the transmission pointer value is output (Sf6), and the strobe signal is output again for a predetermined time (Sf7).

  Next, 1 is added to the area number indicated by the transmission pointer (Sf8). Since the area number is a numerical value in the range of 0 to 31, 1 is added when the area number indicated by the transmission pointer is 31, and is updated to 0 when it is 32. After that, it is checked whether the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, whether or not the command to be transmitted is stored in the command queue (Sf9). That is, when the command to be transmitted is not stored in the command queue, the non-transmission flag is cleared to end the normal time command transmission processing (Sf10). On the other hand, when the area number indicated by the transmission pointer and the serial number indicated by the storage pointer do not match, that is, when the command to be transmitted is stored in the command queue, the unsent flag is maintained and the command transmission is performed normally. End the process. By maintaining the unsent flag, the unsent command left in the command queue is transmitted in the timer interrupt process (main) from the next time on.

  When the power-off flag is set in the above-described timer interrupt processing, the main control unit 41 of this embodiment executes the power-off command transmission processing before executing the power-off processing (main). Also in the normal command transmission process, the unsent command stored in the command queue is transmitted to the sub control unit 91.

  FIG. 17 is a flowchart showing control contents of a power-off command transmission process which is executed before the main control unit 41 performs the power-down process (main) in the timer interrupt process (main).

  In the power-off command transmission process, first, it is checked whether the unsent flag is set, that is, whether the unsent command is stored in the command queue (Sg1), and the unsent flag is set. If yes, all commands stored in the command queue are sent to the sub control unit 91 (Sg1 to Sg7).

  Specifically, first, the MODE that constitutes the command stored in the area indicated by the transmission pointer value of the command queue is output (Sg2), and a strobe signal for notifying the sub control unit 91 that the command has been output is given for a predetermined time (In this embodiment, 10 μs) is output (Sg3). Then, the EXT that constitutes the command stored in the area indicated by the transmission pointer value is output (Sg4), and the strobe signal is output again for a predetermined time (Sg5). Thereafter, 1 is added to the area number indicated by the transmission pointer (Sg6). As in the case of adding the transmission pointer in the normal command transmission processing, the area number is a numerical value in the range of 0 to 31 and therefore, when the area number indicated by the transmission pointer is 31, 1 is added and 32 Update to 0.

  Next, it is determined whether the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, whether the command to be transmitted is stored in the command queue (Sg7), the area indicated by the transmission pointer If the serial number indicated by the storage pointer does not match the serial number indicated by the storage pointer, ie, the command to be transmitted is stored in the command queue, the area number indicated by the transmission pointer and the serial number indicated by the storage pointer in step Sg7 Steps Sg2 to Sg7 are repeatedly executed until it is determined that they match, and all the commands stored in the command queue are transmitted to the sub control unit 91.

  If it is determined in step Sg7 that the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, all the commands stored in the command queue are transmitted to the sub control unit 91. If no command remains in the command queue, the main control unit 41 clears the unsent flag (Sg8), ends the power-off command transmission process, and shifts to the power-off process (main).

  As described above, in the normal-time command transmission process, one command (one set of two-byte commands) is added to the sub control unit 91 each time the normal-time command transmission process is executed in the timer interrupt process (main). In the power-off command transmission process, all commands stored in the command queue are sent to the sub control unit 91 before the power-off process (main) is performed in the timer interrupt process. Is supposed to be sent.

  In FIG. 18, when the main control unit 41 determines that the power-off flag is set in the above-described timer interrupt processing (main), the power-off processing (main) executed after the power-off command transmission processing is performed. It is a flow chart which shows control contents. In the present embodiment, the power-off process is included in the non-game program.

  In the power-off process (main), first, all registers that may be used are saved in the stack area (Sg1).

  Next, the destruction diagnostic data 1 is set in the game RAM area, the destruction diagnosis data 2 in the non-game RAM area, and the destruction diagnosis data 3 in the stack area (Sg2). The data for destruction diagnosis are all 5A (H). Then, all output ports including the parallel output port 513 for outputting a command are initialized (Sg3). As a result, the output state of the output port corresponding to the last command output by the power-off command transmission process is initialized. Next, RAM parity adjustment data 1 is calculated so that the exclusive OR of all areas (including unused area 3) of the game RAM area becomes 0, and is set in the game RAM area, and RAM parity adjustment data 2 is calculated so that the exclusive OR of all areas (including unused area 4) becomes 0 and set in the non-play RAM area, and all areas of the stack area (unused stack (unused stack) RAM parity adjustment data 3 is calculated and set in the stack area so that the exclusive OR of the area and the stack area in use becomes 0 (Sg4), and the access to the RAM 41c is prohibited (Sg5). After that, the voltage decreases and the CPU 41a of the main control unit 41 stops and shifts to the standby state. Then, when the voltage drops in the standby state, the main control unit 41 is internally stopped to operate, and reliably shuts off at the time of power interruption.

  When the power supply of AC 100 V is stopped by the above process, the power-off process is executed, the data for destruction diagnosis 1 to 3 and the data for RAM parity adjustment 1 to 3 are stored in the backup RAM, and the RAM access is performed. It is disabled and the output port is cleared.

  As described above, in the present embodiment, in the power-down process that is executed when a power-down is detected, a process of calculating data for RAM parity adjustment for determining whether the data in the RAM 41 c is normal or not, The process of calculating the RAM parity to determine whether it is normal or not, and the process of determining whether the data of the RAM 41c is normal based on the RAM parity when the power is turned on, are divided into the game RAM area and the non-game RAM area Therefore, it is possible to easily identify the storage area of data required to design these processes.

  In this embodiment, the adjustment data is set as the target area so that the calculation result of the target area in the power-off process becomes a specific value (0 in the present example), and the target is set in the start processing. It is determined whether the data in the RAM 41c is normal or not depending on whether the calculation result of the area becomes a specific value or not, but the calculation result of the area targeted in the power-off process and the area targeted in the activation process Whether or not the data in the RAM 41c is normal may be determined based on whether or not the calculation result of the above and the comparison result. Further, the calculation method is not limited to exclusive OR, and another calculation method (for example, sum) may be used.

  Further, in the present embodiment, RAM parity adjustment data 1 is calculated using data stored in all areas of the game RAM area including the unused area 3 in the power-off process, and the non-game including the unused area 4 is calculated. RAM parity adjustment data is calculated using data stored in all areas of RAM area, RAM calculated using data stored in all areas of game RAM area including unused area 3 in startup processing It is determined whether the RAM 41c is normal or not based on the RAM parity 2 calculated using data stored in all areas of the non-playing RAM area including the parity 1 and the unused area 4 If an illegal program is stored in the used areas 3 and 4, it is determined that the RAM is abnormal, so that it is prevented that an unauthorized program is stored in the unused areas 3 and 4. That.

  In this embodiment, RAM parity adjustment data 1 is calculated using data stored in all areas of the game RAM area including the unused area 3 in the power-off process, and the non-game including the unused area 4 is calculated. RAM parity adjustment data is calculated using data stored in all areas of RAM area, RAM calculated using data stored in all areas of game RAM area including unused area 3 in startup processing The configuration is to determine whether the RAM 41c is normal or not based on the RAM parity 2 calculated using data stored in all areas of the non-gaming RAM area including the parity 1 and the unused area 4 RAM parity adjustment data 1 is calculated using data stored in the game RAM area not including area 3 and stored in a non-game RAM area not including unused area 4 The RAM parity adjustment data is calculated using the data, and the RAM parity 1 calculated using data stored in the game RAM area not including the unused area 3 in the activation process and the non-game not including the unused area 4 Whether or not the RAM 41c is normal may be determined based on the RAM parity 2 calculated using data stored in the RAM area.

  In addition, RAM parity adjustment data 1 is calculated using data stored in all areas of the game RAM area including the unused area 3 in the power-off process, and stored in the non-game RAM area not including the unused area 4 RAM parity adjustment data calculated using the stored data, RAM parity 1 calculated using data stored in all areas of the game RAM area including the unused area 3 in startup processing, unused area 4 It may be configured to determine whether the RAM 41c is normal or not based on the RAM parity 2 calculated using data stored in the non-playing RAM area not including If an illegal program is stored in 3, it is determined that the RAM is abnormal, so that the illegal program can be prevented from being stored in the unused area 3.

  In addition, RAM parity adjustment data 1 is calculated using data stored in the game RAM area not including unused area 3 in the power-off process, and stored in all areas of non-gaming RAM area including unused area 4 RAM parity adjustment data is calculated using the stored data, and RAM parity 1 calculated using data stored in the game RAM area not including unused area 3 in startup processing, and non-playing area 4 including unused area 4 It may be configured to determine whether the RAM 41c is normal or not based on the RAM parity 2 calculated using data stored in all the areas of the RAM area. Even in such a configuration, the unused area 4 may be used. If an illegal program is stored in the RAM, it is determined that the RAM is abnormal, so that the illegal area can be prevented from being stored in the unused area 4.

  Further, in the present embodiment, in the power-off processing that is executed when a power failure is detected, processing for calculating data for RAM parity adjustment for determining whether the data in the RAM 41 c is normal or not, the data is normal when the power is turned on. The process of calculating the RAM parity for determining whether or not, and the process of determining whether the data of the RAM 41c is normal based on the RAM parity when the power is turned on are divided into a game RAM area and a non-game RAM area However, in the power-off process, the game RAM area is calculated by calculating adjustment data in which the calculation result using both the data stored in the game RAM area and the data stored in the non-game RAM area becomes a specific value. Alternatively, it is set in the non-gaming RAM area, and both of the data stored in the gaming RAM area and the data stored in the non-gaming RAM area are used in the activation processing. It is determined whether or not the data in the RAM 41c is normal based on whether or not the calculation result becomes a specific value, that is, adjustment data for determining whether the data in the RAM 41c is normal in the power-off process. The process of calculating the game, the process of calculating the data to determine whether the data is normal when the power is turned on, the process of judging whether the data of the RAM 41c is normal based on the data calculated when the power is turned on The configuration may be performed without distinction between the area and the non-game RAM area. With such a configuration, adjustment data for determining whether or not the data in the RAM 41 c is normal is calculated in the power-off process. Processing, processing of calculating data for determining whether data is normal at power on, data of RAM 41 c based on data calculated at power on It can be reduced program capacity necessary for processing for determining normal or not.

  Also in such a configuration, adjustment data is calculated using data of all areas including unused areas 3 and 4 as well as the game RAM area and the non-game RAM area in the power-off process, and the activation process Also in the game RAM area, non-game RAM area, as well as whether the result calculated using data of all areas including unused areas 3 and 4 becomes a specific value, the data in RAM 41c is normal or not In such a configuration, if an unauthorized program is stored in the unused areas 1 and 2, it is determined that the RAM is abnormal. Can prevent unauthorized programs from being stored.

  In the present embodiment, as shown in FIG. 19, the reset circuit 49 of the game control board 40 has a monitor voltage (DC + 24 V) higher than the drive voltage (DC + 5 V) of the main control unit 41 among the power supply voltages supplied from the power supply board 101. ), And when the monitoring voltage exceeds the operable voltage (main) (+3.5 V) at which the main control unit 41 can operate when the power is turned on, the reset signal is turned on to the main control unit 41. After that, the reset signal is turned off when the time sufficient for the driving voltage (DC + 5 V) of the main control unit 41 to stabilize (the time sufficient for the monitoring voltage to rise to +24 V) has elapsed. The control unit 41 is activated. On the other hand, the reset circuit 95 of the effect control board 90 sets the sub control unit 91 at a timing earlier than the timing when the reset signal is turned off by the reset circuit 49 when the power is turned on, that is, the timing when the main control unit 41 is activated. When the power is turned on, the sub control unit 91 is activated at an earlier stage than the main control unit 41 by turning off the reset signal to be output, and the return command or setting command transmitted from the main control unit 41 (start ) In a state where the sub control unit 91 can receive.

  Then, when the reset signal output from the reset circuit 49 is turned off and started up, the main control unit 41 executes the above-mentioned initial setting process, and when the state before power interruption can be restored, the initial setting is performed. After sending the return command at the end of the process, the timer interrupt is permitted, and then the timer interrupt process is executed at regular intervals. In addition, when the reset signal is turned OFF and started, the setting key switch 37 is in the ON state, the RAM 41c is initialized, and the setting change state is started without returning to the state before the power interruption. Before the timer interrupt is permitted at the end of the initial setting process, the setting command (start) is transmitted to the sub control unit 91 instead of the return command, and then the timer interrupt is permitted, and then the timer Interrupt processing is executed at regular intervals. On the other hand, the sub control unit 91 is activated before the main control unit 41 is activated, executes and completes the initial setting process, and waits until reception of a return command or a setting command (start) in a state in which commands can be received. Do.

  Next, after transmitting a return command or a setting command, the main control unit 41 executes timer interrupt processing (main) at regular intervals, and executes normal command transmission processing in the timer interrupt processing (main). If the command to be transmitted is not stored in the command queue, a door command is generated and transmitted based on the detection state of the door open detection switch 25. On the other hand, the sub control unit 91 starts output control of the rendering device by receiving a return command or a setting command (start).

  Further, the main control unit 41 transmits a door command or the like by the normal time command transmission process executed in the timer interrupt process (main), and after the start of the main control unit 41, the timer division is performed until the end of the initial setting process. After the main control unit 41 is activated, transmission of a command such as a door command transmitted by normal command transmission processing is permitted after transmission of a return command or setting command (start) after activation of the main control unit 41. It will be.

  Further, as shown in FIG. 19, the main control unit 41 executes the power failure determination process in the timer interrupt process (main), and based on whether the voltage drop signal is input from the power failure detection circuit 48 or not. Identify the occurrence of a power failure. The power failure detection circuit 48 monitors the aforementioned monitor voltage (DC + 24 V) higher than the drive voltage (DC + 5 V) of the main control unit 41, and detects a voltage drop higher than the drive voltage (DC + 5 V) of the main control unit 41. As the voltage drop signal is output when the voltage (main) or less (+20 V) or less, the occurrence of power interruption is identified when the monitoring voltage becomes less than or equal to the voltage drop detection voltage (main). . Then, when the occurrence of power failure is identified in the power failure determination processing, the main control unit 41 executes command transmission processing upon power failure to send all commands stored in the command queue to the sub control unit 91. After transmission, the power-off process (main) is executed.

  Also, in the reset circuit 49, the monitoring voltage is lower than the voltage drop detection voltage (main) (+20 V) and becomes lower than the operation limit voltage (main) (+8 V) higher than the operable voltage (main) (+3.5 V). Thus, the reset signal is turned ON to make the main control unit 41 inoperable. After the operating limit voltage (main) falls below the voltage drop detection voltage (main) at which the power failure detection circuit 48 detects the occurrence of a power cut, the time until the operating limit voltage (main) drops is the voltage drop. The main control unit 41 identifies the occurrence of power interruption after becoming lower than the detection voltage (main), executes the command transmission processing at power interruption, and secures the time required to execute the power interruption processing. It is set to.

  When the voltage drop detection voltage (main) or less is reached, the main control unit 41 identifies the occurrence of power interruption, executes command transmission processing at power interruption, and the time required to execute the power interruption processing is: The maximum time until the main control unit 41 detects a power failure (0.56 ms because the occurrence of power failure is specified for each timer interrupt processing (main)) In the case of the maximum number of transmissions, the time required to transmit the maximum number (32) of storable commands (40 μs for one command transmission (MODE transmission 10 μs, transmission interval 10 μs, EXT transmission 10 μs, transmission interval 10 μs) is required. It is a time obtained by adding × 32 = 1280 μs and the time required for the power interruption process (main).

  On the other hand, the power failure detection circuit 98 monitors the aforementioned monitor voltage (DC + 24 V) higher than the drive voltage (DC + 5 V) of the sub control unit 91, and the monitor voltage is lower than the operation limit voltage (main) (+8 V), The sub control unit 91 outputs a voltage drop signal when the voltage drop detection voltage (sub) (+6 V) higher than the drive voltage (DC + 5 V) of the sub control unit 91 is equal to or lower than the drive voltage (DC + 5 V). The occurrence of power interruption is identified by the following. Then, when the occurrence of power failure is identified in the power failure determination process, the sub control unit 91 executes the power failure process (sub).

  Also, in the reset circuit 95, the monitoring voltage is lower than the voltage drop detection voltage (sub) (+6 V) and becomes lower than the operation limit voltage (sub) (+ 4 V) higher than the operable voltage (sub) (+ 3.5 V). Thus, the reset signal is turned on to make the sub control unit 91 inoperable. After the operating limit voltage (sub) becomes equal to or lower than the voltage drop detection voltage (sub) at which the power failure detection circuit 98 detects the occurrence of a power failure, the time until the operating limit voltage (sub) drops is the voltage drop It is set so that the sub control unit 91 specifies the occurrence of power interruption after becoming lower than the detection voltage (sub) and secures the time required to execute the power interruption process.

  In addition, the sub control unit 91 makes the main control unit 41 inoperable after the monitoring voltage is the operation limit voltage (main), that is, the command transmission processing upon power interruption by the main control unit 41 and the power interruption processing (main) are completed. When the voltage drop detection voltage (sub) lower than the voltage is lower than or equal to the voltage drop signal that is output, the occurrence of the power interruption is identified by the voltage drop signal that is output, and the power interruption processing (sub) is performed. Since the state where the command can be received is maintained until the command transmission processing upon power interruption is completed, the main control unit 41 executes the power interruption processing in a state where all the commands transmitted by the command transmission processing upon power interruption have been received. It is possible to Even when the timing at which the sub control unit 91 identifies the occurrence of power interruption is the timing before the main control unit 41 becomes inoperable, the command transmitted by the main control unit 41 by the command transmission processing at power interruption is If the configuration in which the command can be received until the timing sufficient to receive all is maintained, the main control unit 41 executes the power-off processing in the state where all the commands transmitted by the command transmission processing at power-off have been received. can do.

  As described above, the main control unit 41 according to the present embodiment generates a command according to the progress of the game in the main processing or the like, stores the generated command in the command queue, and performs the normal command in the timer interrupt process (main) Each time transmission processing is executed, an unsent command stored in the command queue is transmitted to the sub control unit 91.

  In such a configuration, power supply to the slot machine 1 may be interrupted and power interruption may occur in a state where a plurality of commands are stored in the command queue, and main control is performed when the main control unit 41 detects power interruption. In the part 41 side, a plurality of commands have not been sent, and the unsent command is held as it is even after power interruption, and the command which has been held before the power interruption after power interruption recovery is sent to the sub control unit 91 If it transmits, the control state by the side of the main control part 41 at the time of a power failure and a power failure return will differ from the control state by the side of the main control portion 41 specified by the sub control part 91 side.

  On the other hand, in the present embodiment, the main control unit 41 is stored in the command queue before executing the power-off process (main) for enabling restoration to the control state before power-off at the time of power-off detection. Since the command transmission processing at power cut-off is executed to transmit all the commands to the sub control unit 91, the control state on the main control unit 41 side at the time of power cut off and power restoration, and the sub control unit 91. The control state on the side of the main control unit 41 specified on the side can be matched as much as possible.

  Further, at the time of detection of a power failure, the main control unit 41 has a maximum number of commands that can be stored in the command queue (a maximum of 32 commands in the present embodiment) during a period from the power supply being stopped until it becomes uncontrollable. Is sent to the sub-control unit 91 and longer than the time required to complete the power-off process (main). Therefore, after power-off detection, all commands stored in the command queue are transmitted. The processing up to the power interruption processing (main) can be reliably executed.

  In the present embodiment, the main control unit 41 which is the first control means for controlling the game transmits a command as control information to the sub control unit 91 which is the second control means for controlling the effect. However, the first control means may be control means for performing control other than game control, for example, effect control. Further, the second control means may be any control means that performs some control based on the control information transmitted from the first control means. For example, the first control means is a control means for controlling an effect In some cases, control means for controlling the rendering device based on the control information transmitted from the first control means may be used as the second control means.

  Further, in this embodiment, as the power interruption process (main) executed by the main control unit 41 (first control means), the RAM parity adjustment is performed so that the RAM parity (exclusive OR) of the backup area becomes 0. By setting data and performing processing for setting destruction diagnosis data (data other than 0), the RAM parity is 0 at the time of power failure recovery, and the data for backup area matches because the destruction diagnosis data match. Is a configuration that makes it possible to determine that it is normal, but in the case of a power-off process that enables restoration to the control state before power-off when power supply to the slot machine 1 is stopped and power interruption occurs. Preferably, for example, a checksum of the backup area may be set, and it may be possible to determine that the data of the backup area is normal by matching the checksum calculated at the time of power failure recovery.

  Further, in the present embodiment, the reset circuit 49 of the game control board 40 resets the monitor voltage before it becomes lower than the operable voltage (main) at which the main control unit 41 becomes inoperable when the monitor voltage drops when the power failure occurs. Is supplied to the main control unit 41, and the main control unit 41 stops any operation by supplying a reset signal, that is, the control can not be performed. During the period from when the reset signal is supplied to the uncontrollable state, the maximum number of commands that can be stored in the command queue is transmitted to the sub control unit 91, and it is necessary for the power interruption process (main) to be completed. The monitoring voltage is lower than the operable voltage (main) of the main control unit 41 in the configuration in which the main control unit 41 is not supplied with the reset signal at the time of power interruption although the configuration is longer than the period. A configuration in which the period until it becomes uncontrollable is longer than the period required for the maximum number of commands that can be stored in the command queue to be sent to the sub control unit 91 and power failure processing (main) is completed. Even in this case, after power failure detection, processing from transmission of all commands stored in the command queue to power failure processing (main) can be reliably executed.

  Further, in the present embodiment, the operation limiting voltage (main) for stopping the operation of the main control unit 41 at the time of the power interruption occurs and the voltage drop detection voltage (main) or less at which the power interruption detection circuit 48 detects the occurrence of the power interruption. The main control unit 41 identifies the occurrence of power interruption after the time to drop to the operation limiting voltage (main) becomes equal to or lower than the voltage drop detection voltage (main), and the command transmission processing at power interruption is performed. By setting to secure the time required to execute and execute the power-off process, the period until the main control unit 41 becomes inoperable after the power-off occurs is stored in the command queue The configuration is such that the maximum possible number of commands are transmitted to the sub control unit 91 and the period longer than the time required to complete the power interruption process (main) is longer. Decrease the driving voltage of the capacitor During the period until the main control unit 41 becomes inoperable after power interruption by delaying with a battery, capacitor, etc., the maximum number of commands that can be stored in the command queue are transmitted to the sub control unit 91, and It is configured to be longer than the period required to complete the power-off process (main), or the period until the main control unit 41 becomes inoperable is the maximum number of commands that can be stored in the command queue. The maximum number that can be stored in the command queue may be set to be longer than the time required to complete the transmission to the main unit and the power-off process (main), or even if these configurations are used, After power failure occurs, processing from transmission of all commands stored in the command queue to power failure processing (main) can be reliably executed.

  In addition, the main control unit 41 of this embodiment executes a power-off command transmission process at the time of power failure detection, and after transmitting all commands stored in the command queue to the sub control unit 91, The power-off process (main) is executed, and each output port of the parallel output port 513 including the output port for outputting a command in the power-down process (main) is initialized. It is possible to prevent the command from being sent.

  Further, the main control unit 41 according to the present embodiment executes a normal command transmission process in the timer interrupt process (main) to obtain a predetermined number of commands stored in the storage area stored in the command queue. (In this embodiment, one command is transmitted to the sub control unit 91 at predetermined intervals (once in four timer interrupt processes (main)). Therefore, a predetermined number (one in this embodiment) is transmitted. Even if the above commands are stored in the command queue, the number of command transmissions sent in one timer interrupt process (main) is limited to a predetermined number, so commands in the normal command transmission process Can prevent the other control by the main control unit 41 from being delayed.

  In addition, the main control unit 41 of the present embodiment receives a command according to the progress of the game in the command queue (internal winning command) (when performing a normal command transmission process to be executed in the timer interrupt process (main)) at a predetermined timing. When the stop operation command or the like is not stored, a door command indicating the detection state of the door opening detection switch 25 is transmitted to the sub control unit 91 to open or close the open / close state of the front door 1b. Since the 91 can be specified and the door command is transmitted when the command corresponding to the progress of the game is not stored in the command queue at the predetermined timing, the transmission of the command corresponding to the progress of the game is the door command It may be delayed by transmission, or other control by the main control unit 41 by transmission of a door command (for example, each control in the main processing ) It is possible to prevent the delay.

  Also, after the main control unit 41 transmits a return command or a setting command (start) after its activation, transmission of a command such as a door command transmitted by the normal command transmission process is permitted. After the power is turned on, the door command is not transmitted until the state before power interruption is restored and a return command is transmitted, or the setting command (start) is transmitted without returning to the state before power interruption. Therefore, after it is determined whether or not to restore the main control unit 41, the sub control unit 91 can specify the state of the main control unit 41 side, and the main control unit 41 is in the control state before power interruption. When the sub control unit 91 receives a command in a state where it is not determined whether to return or not, it is possible to prevent an unintended operation from being performed.

  In this embodiment, when no command is stored in the command queue in the normal-time command transmission process, the door command indicating the detection state of the door opening detection switch 25 is generated and transmitted. When no command is stored in the command queue in the normal command transmission processing, the operation switches (MAX BET switch 6, start switch 7, stop switches 8L, 8C, 8R) are selected based on the output of the switch detection circuit 44. The control state on the main control unit 41 side can be specified, such as a command indicating a detection state (on / off), a command indicating presence / absence of detection of an error, and a type of detected error, and a command capable of specifying a game state of the game The command may be generated and transmitted to the sub control unit 91, Even with this configuration, the sub control unit 91 can specify the control state on the main control unit 41 side, and the command transmission according to the progress of the game can specify the control state of the main control unit 41. It is possible to prevent the other control by the main control unit 41 from being delayed by transmission of a command that can delay by transmission or can specify the control state of the main control unit 41.

  Next, a timer counter for measuring a time interval used by the main control unit 41 for progress control of a game and the like will be described with reference to FIGS.

  The main control unit 41 sets an initial value according to the clocking time as the timer value of the timer counter allocated to the RAM 41c when the clocking start condition is satisfied, and periodically executes the timer in the timer interrupt process (main). The value is subtracted, and when the timer value becomes 0, it is specified that the counted time has elapsed.

  Specifically, when the clocking start condition is satisfied in the main processing, the main control unit 41 sets an initial value of the timer value according to the clocking time in the area to which the timer counter corresponding to the condition is allocated. The set timer value is decremented by one every about 2.24 ms until it becomes 0 in the time counter update process of the timer interrupt process (main).

  Then, in the main processing, as shown in FIG. 20, the address of the corresponding timer counter is obtained (Si1), the obtained value is read (Si2), and it is judged whether the read value is not 0 (Si3) When it is determined that the read value is 0, it is specified that the counted time has elapsed.

  The timer counter used in this embodiment, as shown in FIG. 21, has 1 byte timer A whose initial value is 1 byte or less, 1 byte timer B, 1 byte timer C, initial value exceeds 1 byte and 2 bytes or less. It includes a 2-byte timer A, a 2-byte timer B, a 2-byte timer C, and a 2-byte timer D.

  The 1-byte timer is a timer for measuring a relatively short period that can be measured with a timer value within 1 byte, and, for example, an external output signal timer that measures an output period of an external output signal, an output update period of an LED LED update timer to measure the stop operation and stop invalid timer to measure the period until the stop operation is activated again after detection of the stop operation, wait for dispensation to measure the period from the reel stop to the start of medal payout Timer, insertion detection timer for measuring a period after detection of ON of the insertion medal sensor 31, detection for detecting a period from detection of ON for the insertion port sensor 26, detection of detection for ON of the payout sensor 34c There are a payout detection timer that measures a period after it has been started, and a start-up timer that measures a period until the stop operation becomes effective after the reel rotation starts. Among them, the stop invalid timer, the payout wait timer, and the start timer do not cross the timing at which the measurement period by these timers ends one game, but the external output signal timer, the LED update timer, the closing detection timer, the slot The detection timer and the payout detection timer may cross over the timing at which the time measured by the timer ends one game.

  The 2-byte timer is a timer for measuring a relatively long period which can not be measured with a timer value within 1 byte. For example, 1 gaming time timer which measures a prescribed time (about 4.1 seconds) required for 1 game A security signal timer that measures the minimum output period of the security signal among external output signals, a standby time timer that measures the period from the end of the game, a hopper empty that measures the period when the payout sensor 34c is not detected after driving the hopper motor 34b. There is a timer. Among them, the waiting time timer and the hopper empty timer do not cross the timing when the measurement period by these timers is over the end of one game, but the one gaming time timer and the security signal timer have the measuring time by one timer The timing of the end of the event may be crossed.

  Thus, the timer counter is a timing at which one game ends, that is, a timing at which a part of the RAM 41c is initialized according to the progress of the game (a part of the RAM 41c at the end of one game or at the end of a specific gaming state Includes a timer counter that measures the measurement period across which the timer is initialized, and a timer counter that does not cross over the timing when part of the RAM 41c is initialized according to the progress of the game, but any timer The counter is also assigned to the special work that is not initialized at the timing according to the progress of the game.

  Among these timer counters, 1 byte timers A to C are allocated to 1 byte each of continuous 3 byte areas (804 CH to 804 EH) of RAM 41 c, and 2 byte timers A to D are 8 bytes continuous of RAM 41 c. Two bytes are allocated to the area (804FH to 8055h). Furthermore, 1-byte timers A to C and 2-byte timers A to D are also allocated to continuous areas of the RAM 41c. Hereinafter, an area to which 1-byte timers A to C are allocated is referred to as a 1-byte timer group, and an area to which 2-byte timers A to D are allocated is referred to as a 2-byte timer group. That is, each of the 1-byte timer group and the 2-byte timer group is set in an area to which continuous addresses are allocated according to a predetermined rule. The area to which successive addresses are allocated according to a predetermined rule is, for example, an area to which an address N (N is a natural number) added from the start address and the start address is allocated.

  FIG. 22 is a flowchart showing the control contents of the time counter update process.

  In the time counter update process, first, the number (1 in this embodiment) of 1-byte timer counters to be updated is set as the number of 1-byte processes (Sj1), and the top address (804CH) of the 1-byte timer group is set. Set a pointer (Sj2).

  Then, if the 1-byte value stored in the designated address (the address indicated by the pointer) is not 0, the 1-byte value of the designated address is decremented by 1 (Sj3), and the number of times of processing set in Sj1 is decremented by 1. (Sj4) It is determined whether the number of times of processing after subtraction is 0 or not (Sj5).

  If the number of times of processing after subtraction in step Sj5 is not 0, that is, if updating of all 1-byte timers is not completed, the pointer is incremented by 1 (Sj6), and the process returns to step Sj3. As a result, the pointer is moved to the address of the unprocessed 1-byte timer, and subtraction is performed if the 1-byte value of the designated address is not 0.

  In the step Sj5, if the number of times of processing after subtraction is 0, that is, if all the 1-byte timers have been updated, the number of 2-byte timer counters to be updated as the 2-byte processing number (this embodiment) Then set 4) (Sj7) and add 1 to the pointer (Sj8). As a result, the pointer moves to the start address (804FH) of the 2-byte counter group.

  Next, if the 2-byte value stored in the area consisting of the designated address (the address indicated by the pointer) and the next address is not 0, the 2-byte value of the designated address and the next address is decremented by 1 (Sj9), Sj7 The number of processes set in step S is decremented by 1 (Sj10), and it is determined whether the number of processes after subtraction is 0 or not (Sj11).

  If the number of times of processing after subtraction in step Sj11 is not 0, that is, if updating of all 2-byte timers is not completed, the pointer is incremented by 2 (Sj12), and the process returns to step Sj9. As a result, the pointer is moved to the address of the unprocessed 2-byte timer, and subtraction is performed if the 2-byte value of the designated address and the next address is not zero.

  If the number of times of processing after subtraction is 0 in step Sj11, that is, if all the 2-byte timers have been updated, the processing is ended.

  As described above, in the present embodiment, the value of the timer counter allocated to the RAM 41c is periodically updated, and the passage of time is specified by becoming a specific value (0). Conventionally, when measuring a plurality of types of time intervals, timer values are set and updated within a plurality of types of processing requiring time counting, and each processing is a program for updating a plurality of types of timer values. Since it is necessary to provide it internally, it has become a factor that increases the program capacity. In addition, since multiple types of timer counters are assigned as data groups for each process in which they are used, it is necessary to read out the values of addresses that are not related to each other in order to update them collectively in one process. there were.

  On the other hand, in the present embodiment, an area in which a plurality of types of timer counter values are stored is set in an area to which continuous addresses are allocated according to a predetermined rule of the RAM 41c, and timer values stored in designated addresses are used. Since the processing to be updated is repeatedly executed while changing the designated address for the area where a plurality of types of timer counter values are stored by adding a constant to the current designated address, the plurality of timer values are updated. The program capacity can be reduced compared to the case where processing of specifying a plurality of types of addresses and updating the value of the address is performed in each processing.

  It should be noted that processing of updating the timer value stored in the designated address is repeatedly performed while changing the designated address to the area where plural types of timer counter values are stored by performing predetermined operation, thereby performing plural types of timers. Any configuration may be used as long as the value is updated. For example, by adding a constant to the current designated address, a plurality of types can be repeatedly executed while changing the designated address to the area where plural types of timer counter values are stored. The timer value may be updated, or a value corresponding to the processing number with respect to the reference address (for example, in the case of a 1-byte counter, +1 in the case of processing number 1 and +2 in the processing number 2) While changing the designated address for the area where multiple types of timer counter values are stored by adding or subtracting +3 ... in the case of 3. Ri may be configured to update a plurality of types of the timer value by return run.

  Further, in the present embodiment, the values of seven types of timer counters of 1 byte timers A to C and 2 byte timers A to D are provided, but at least two or more types of timer counters have predetermined rules of RAM 41c. In the process of updating the timer value stored in the specified address by changing the specified address for the area where multiple types of timer values are stored, set the area to which consecutive addresses have been assigned in step 2 and update the timer value stored in the specified address. However, as long as two or more types of timer values are updated by repeating execution, the program capacity can be reduced as described above.

  Further, only one of the 1-byte timer or 2-byte timer sets the value of the timer counter in the area to which the continuous address is allocated according to the predetermined rule of the RAM 41c, and updates the timer value stored in the designated address. The configuration may be such that the timer values of the plurality of types are updated by repeatedly executing while changing the designated address to the area in which the plurality of types of timer values are stored by performing the predetermined calculation.

  Further, only a part of timer counters included in the main control unit 41 sets a timer value in an area to which a continuous address is allocated according to a predetermined rule of the RAM 41 c, and updates the timer value stored in the designated address, The configuration may be such that the timer values of the plurality of types are updated by repeatedly executing while changing the designated address to the area in which the plurality of types of timer values are stored by performing the predetermined calculation.

  Further, although the present embodiment is configured to have a separate timer counter for each type of period to be measured, for example, one timer counter may be shared for a plurality of types of periods in which the periods to be measured do not overlap.

  Further, in the present embodiment, as the processing executed by the main control unit 41, timer interrupt processing (main), which periodically performs predetermined processing regardless of the progress status of the game, and the progress status of the game The main control unit 41 sets an initial value in the timer counter when the clocking condition is satisfied in the main processing, and the main control unit 41 sets a plurality of types in the timer interrupt processing (main). Since the timer value is updated, and there is no need to provide processing for updating multiple types of timer values in each of the processes constituting the main processing, the program capacity for updating multiple types of timer values is reduced. be able to.

  In the present embodiment, the main process is periodically interrupted to execute the timer interrupt process (main), but the timer process is periodically determined regardless of the progress of the game within the timer interrupt process. Alternatively, the main control unit 41 may be configured to perform both the periodic processing for performing the above-described processing and the main processing for performing different processing in stages according to the progress of the game. By setting an initial value in the timer counter when the clocking condition is satisfied in the process, and updating the timer values of the plural types in the periodic processing, the timer values of the plural types are included in each process constituting the main process. Since it is not necessary to provide a process for updating, it is possible to reduce the program capacity associated with updating of multiple types of timer values.

  In this embodiment, in the time counter update process, the value of the address is updated on condition that the value of the designated address is not 0, and the timer value is updated to an abnormal value. It can prevent.

  Further, in this embodiment, in the time counter updating process, the number of processes equal to the number of timer counters to be updated is set, and the process of updating the timer value is repeatedly executed by the set number of processes. Management of the number of timer counters to be performed is facilitated, and for example, in the case where a plurality of types of timer counters having different update intervals are provided, the type of timer value to be updated may be arbitrarily set according to the number of processes to be set. it can.

  The number of processes, that is, the number of timer counters to be updated may be set in a program, or values set in a table may be read and set.

  Further, the timer counter to be updated last is set in advance without setting the number of processes first, and the process of updating the timer value is repeatedly executed until the address of the timer counter is reached, or the last update is performed. A specific end value (for example, FFh) is stored at the address next to the timer counter, and the process of repeatedly executing the process of updating the timer value until the value read from the designated address becomes the specific end value is also possible. good.

  Further, in the present embodiment, a 1-byte timer counter and a 2-byte timer counter are provided, and processing for updating the 1-byte timer value and processing for updating the 2-byte timer value are separately provided. Therefore, the capacity of the program and the capacity occupied by the timer value in the RAM 41c can be reduced compared to the case where the process of updating the 1-byte timer value and the process of updating the 2-byte timer value are made common.

  In the present embodiment, although the configuration is such that a relatively long time corresponding to an initial value exceeding 1 byte is measured by providing a 2-byte timer counter, for example, a timer counter having a different update interval, for example, a timer By providing the first timer counter that is updated once in four times and the second timer counter that is updated once in fourteen interrupt processing (main), relative processing can be performed without providing a 2-byte counter. It is also possible to measure a long time interval, and it is not necessary to provide a process of updating the 1-byte timer value and a process of updating the 2-byte timer value. Can reduce the program capacity for updating.

  Further, in the present embodiment, a plurality of types of timer counters are allocated to the special work that is not initialized according to the progress of the game in the RAM 41c, and are not initialized according to the progress of the game Regardless of the progress of the game, it is possible to measure the time of the period crossing the timing when a part of the RAM 41c is initialized according to the progress of the game.

  In particular, in this embodiment, not only the timer counter that may cross the timing when the measurement period ends one game, that is, the timing when a part of the RAM 41c is initialized according to the progress of the game, the measurement period is game The timer counter that does not cross the timing at which a part of the RAM 41c is initialized according to the progress is also stored in the area assigned to the special work together with the other timer counters, so management of the timer counters becomes easy. At the same time, the timer counter does not straddle the timing when the measurement period is initialized in part of the RAM 41c in accordance with the progress of the game, and the timing in which the measurement period is initialized in part of the RAM 41c in accordance with the progress of the game The application of the timer counter can be easily changed by changing the design to the timer counter, etc. It can be. In addition, if one timer counter is shared for a plurality of types of periods in which the periods to be measured do not overlap as described above, there is a possibility that it crosses the timing when part of the RAM 41c is initialized according to the progress of the game. It becomes possible to measure the measurement period and the measurement period which does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game with one timer counter.

  Although the embodiments of the present invention have been described above with reference to the drawings, the present invention is not limited to these embodiments, and any changes or additions can be made without departing from the scope of the present invention. Needless to say.

  In the embodiment, an example in which the present invention is applied to a slot machine in which the number of bets is set using medals and credits as gaming value has been described, but a slot machine for setting the number of bets using gaming balls as gaming value Alternatively, the present invention may be applied to a full credit slot machine in which the number of bets is set using only credits as gaming value. When using game balls as game values, for example, one medal can be made to correspond to five game balls, and when setting 3 as the number of bets in the first embodiment, 15 game balls can be used. It corresponds to what sets a bet number using.

  Furthermore, the present invention is not limited to using only one of a plurality of types of game values such as medals and game balls, and, for example, can be used together with a plurality of types of game values such as medals and game balls It may be That is, it is possible to play a game by setting the number of bets regardless of any of a plurality of types of game values such as medals and game balls, and a plurality of types of games such as medals and game balls due to the occurrence of winnings. You may apply the slot machine which can pay out any value.

  In the embodiment, a slot machine has been described as an example of a gaming machine, but the main control unit 41 and the initialization processing related to the main control unit 41 disclosed in the above embodiment, timer interrupt processing, command storage processing, normal time Processing related to the sub control unit 91 and the sub control unit 91, such as command transmission processing, command transmission processing at power cut off, timer counter update processing, etc., by firing game balls in another game machine, for example, a game area A game may be performed, and the fired game ball may enter a winning opening provided in the game area to generate a prize, and the present invention may be applied to a pachinko game machine or the like in which the game ball is paid out as a prize ball.

1 Slot machine 2L, 2C, 2R Reel 6 MAX BET switch 7 Start switch 8L, 8C, 8R Stop switch 41 Main control unit 91 Sub control unit

Claims (2)

In a gaming machine that plays a game,
Storage means having a storage area capable of storing data;
Permission area setting means capable of setting an area for permitting execution of a program among the storage areas;
Equipped with
The storage area is
A first program storage area in which a first program related to the first control is stored;
A first data storage area in which first data used by the first program is stored;
A second program storage area in which a second program related to the second control is stored;
A second data storage area in which first data used by the second program is stored;
Including
The first program storage area is an area from the first address of the storage area to the first address,
The first data storage area is an area from the next address to the second address of the first address of the storage area,
The second program storage area is an area from a third address to a fourth address after the second address of the storage area,
The second data storage area is an area from an address following the fourth address of the storage area to a fifth address,
In the area from the address next to the second address to the address before the third address of the storage area and the area from the next address to the final address of the fifth address, 0 is stored in all areas. It is an unused area,
The permission area setting unit sets an area from the start address of the storage area to the first address and an area from the third address to the fourth address as areas for permitting execution of the program. Machine. In a gaming machine that plays a game,
Storage means having a storage area capable of storing data;
Permission area setting means capable of setting an area for permitting access to data stored in the storage area;
Equipped with
The storage area is
A first program storage area in which a first program related to the first control is stored;
A first data storage area in which first data used by the first program is stored;
A second program storage area in which a second program related to the second control is stored;
A second data storage area in which first data used by the second program is stored;
Including
The first program storage area is an area from the first address of the storage area to the first address,
The first data storage area is an area from the next address to the second address of the first address of the storage area,
The second program storage area is an area from a third address to a fourth address after the second address of the storage area,
The second data storage area is an area from an address following the fourth address of the storage area to a fifth address,
In the area from the address next to the second address to the address before the third address of the storage area and the area from the next address to the final address of the fifth address, 0 is stored in all areas. It is an unused area,
The gaming machine, wherein the permission area setting unit sets the area from the top address of the storage area to the fifth address collectively as an area for permitting access to the stored data .

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