JP6646938B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine and a slot machine.

  As a gaming machine of this type, in a configuration including game control means for controlling a game, and effect control means for controlling an effect based on a command transmitted from the game control means, the game It has been proposed that both the control means and the effect control means can return to the control state before the power interruption (for example, see Patent Document 1).

  In such a gaming machine, even if a plurality of commands remain untransmitted on the game control means side when the power failure is detected, the untransmitted commands are retained as they are even after the power failure, and from the time before the power failure is recovered after the power failure is recovered. The held command is transmitted (for example, see Patent Document 1).

JP 2010-158306 A

  In the gaming machine described in Patent Document 1, even if a plurality of commands remain untransmitted on the game control unit side when a power failure is detected, the untransmitted commands are retained as they are after the power failure, and the power is restored after the power failure is recovered. Since the command held before the power failure is transmitted, if there is an untransmitted command at the time of power failure detection, the control state of the game control means at the time of power failure and at the time of power failure recovery, The control state on the game control means side specified on the effect control means side will be different.

  The present invention focuses on such a problem, the control state of the game control means side at the time of power interruption and at the time of power interruption recovery, the control state of the game control means side specified by the effect control means side It is an object of the present invention to provide a gaming machine that can make the game machine match as much as possible.

In order to solve the above-mentioned problem, a gaming machine according to a first aspect of the present invention includes:
In a gaming machine (slot machine 1) that performs a game,
A first control unit (main control unit 41) capable of performing the first control and maintaining the control state even when the power supply to the gaming machine (slot machine 1) is stopped;
Performs a second control based on the first control information transmitted from the control unit (command), the gaming machine (slot machine 1) second possible retention power supply control state be stopped to Control means (sub-control unit 91);
With
The first control means includes:
When the power-off condition is satisfied (input of the voltage drop signal), power-off processing (power-off processing (main power-off processing (main Means for executing power interruption processing for executing
Control information storage means (command storage processing) for creating control information (commands) to be transmitted to the second control means (sub-control unit 91) in accordance with the progress of control and storing the control information (commands) in a storage area (command queue);
The control information (command) stored in the storage area (command queue) is transmitted to the second control means (sub-control unit 91) at predetermined times (once every four times of timer interrupt processing (main)). Control information transmitting means (normal command transmission processing) for transmitting
When the power interruption condition is satisfied (input of the voltage drop signal), the control information (command) stored in the storage area (command queue) before executing the power interruption processing (power interruption processing (main)). A second control information transmitting unit (a command transmission process at the time of power interruption) for transmitting all the data to the second control unit (sub-control unit 91);
When control information according to the progress of control is not stored in the storage area at the predetermined opportunity, specific control information transmitting means capable of transmitting specific control information indicating a state of the first control means,
When the power supply to the gaming machine starts, when returning to the control state before the power supply to the gaming machine is stopped, a predetermined control information transmitting unit that transmits predetermined control information,
Including
When the power supply to the gaming machine is started, the specific control information is transmitted until the predetermined control information is transmitted, even if the control information according to the progress of the control is not stored in the storage area. Not
The period from when the power interruption condition is satisfied (input of the voltage drop signal) to when the first control means (main control unit 41) becomes inoperable (the period until it becomes inoperable by the reset signal) is the aforementioned The maximum number of control information (32 commands) that can be stored in the storage area (command queue) is transmitted to the second control unit (sub-control unit 91), and the power interruption processing (power interruption processing (main )) Is longer than it takes to complete.
According to this feature, when the power-off condition is satisfied, the first control means executes the power-off processing after transmitting all the control information stored in the storage area to the second control means. Therefore, it is possible to make the control state of the game control means at the time of power interruption and recovery from the power interruption coincide with the control state of the game control means specified by the effect control means as much as possible. Further, the period from when the power interruption condition is satisfied to when the first control means becomes inoperable, transmits the maximum number of control information that can be stored in the storage area to the second control means, and Since it is longer than the period required to complete the power-off process, after the power-off condition is satisfied, the process from transmitting the control information to the power-off process can be reliably executed.

The first control means may be a control means for controlling a game, or may be a control means for controlling other than the control of the game, for example, controlling an effect. The second control means may be any control means that performs some control based on the control information transmitted from the first control means. For example, the second control means may be a control means in which the first control means controls a game. In some cases, the control means for controlling the effect based on the control information transmitted from the first control means may be used as the second control means, or the first control means may be a control means for controlling the effect. In some cases, the control means for controlling the effect device based on the control information transmitted from the first control means may be used as the second control means.
In addition, the power interruption processing for enabling the power supply to the gaming machine to return to the control state before the power supply is stopped is, for example, when the power supply is restored, whether or not the data is normal by a checksum or parity diagnosis. For example, a process of setting data for making it possible to determine whether or not the data is available corresponds.
In addition, the period until the first control unit becomes inoperable is a period until the voltage becomes lower than the operable voltage of the first control unit and becomes inoperable, or the first control unit operates due to a decrease in power supply. This is a period until the operation becomes inoperable due to the input of the reset signal before the operation becomes inoperable below the operable voltage.
Further, the period from when the power interruption condition is satisfied to when the first control means becomes inoperable, transmits the maximum number of control information that can be stored in the storage area to the second control means. The term “longer than the time required for completing the power interruption process” means that, for example, the period from when the power interruption condition is satisfied to when the first control unit becomes inoperable is stored in the storage area. The maximum possible number of control information is transmitted to the second control means, and the voltage and the first voltage at which the power interruption condition is satisfied are set to be longer than a period required for completing the power interruption processing. A configuration in which the time during which the control means falls to a voltage at which the control means cannot operate may be set, or a period from when the power interruption condition is satisfied to when the first control means does not operate, may be stored in the storage area. The maximum number of pieces of control information to the second control means. In addition, a configuration may be employed in which a decrease in the supply voltage to the first control means is delayed by a capacitor or the like after the power interruption condition is satisfied so that the period is longer than a period required for completing the power interruption processing. The maximum number of pieces of control information that can be stored in the storage area for the second control means in a period shorter than a period from when the power interruption condition is satisfied to when the first control means becomes inoperable. And the maximum number of control information that can be stored in the storage area may be set so that the power interruption processing can be completed.

The gaming machine according to the second aspect of the present invention is the gaming machine according to the first aspect,
The power interruption condition is satisfied (input of a voltage drop signal), and all control information (commands) stored in the storage area (command queue) is transmitted to the second control unit (sub-control unit 91). Thereafter, an output port (parallel output port 513) for outputting control information (command) is initialized.
According to this feature, after all of the control information stored in the storage area is transmitted after the power interruption condition is satisfied, the output port for outputting the control information is initialized, so that the power supply is unstable. It is possible to prevent the control information from being transmitted by mistake.

The gaming machine according to the third aspect of the present invention is the gaming machine according to the first or second aspect,
The first control information transmission means (normal command transmission processing) controls the control information (command) stored in the storage area (command queue) at predetermined times (once every four timer interrupt processing (main)). Among them, a predetermined number of control information (1 command) is transmitted to the second control means (sub-control unit 91).
According to this feature, even when control information of a predetermined number or more is stored in the storage area, the number of control information transmitted at one time is limited to the predetermined number. It is possible to prevent the other control by the control means from being delayed.

The gaming machine of the means 4 of the present invention is the gaming machine according to any one of the means 1 to 3,
The first control information transmission means (normal command transmission processing) stores control information (internal winning) in a storage area (command queue) according to the progress of control in a predetermined opportunity (once every four timer interrupt processing (main)). When no command or the like is stored, specific control information (door command) indicating the state of the first control means (main control unit 41) is transmitted.
According to this feature, the state of the first control unit can be specified by the second control unit by transmitting the specific control information, and the specific control information is stored in the storage area at a predetermined opportunity according to the progress of the control. Since the information is transmitted when the information is not stored, the transmission of the control information in accordance with the progress of the control is delayed by the transmission of the specific control information, or the other control by the first control unit is performed by the transmission of the specific control information. Delay can be prevented.

The gaming machine according to the fifth aspect of the present invention is the gaming machine according to the fourth aspect,
The first control means (main control unit 41)
Predetermined control information transmitting means for transmitting predetermined control information (return command) when power supply to the gaming machine (slot machine 1) is started and control is returned to a control state before power supply to the gaming machine is stopped; and ,
When power supply to the gaming machine (slot machine 1) is started, transmission restricting means for restricting transmission of the specific control information (door command) until the predetermined control information (return command) is transmitted;
It is characterized by including.
According to this feature, the state of the first control unit can be specified on the second control unit side after it is determined that the first control unit returns.

The gaming machine of the means 6 of the present invention is the gaming machine according to any one of the means 1 to 5,
Interrupt processing executing means for executing processing (timer interrupt processing (main)) according to the interrupt program based on the interrupt;
Address storage means (vector table) capable of storing an address of an interrupt program (timer interrupt processing (main));
Determining means for determining at start-up whether or not the address stored in the address storage means (vector table) is within a predetermined range (area of the program area where programs and the like are actually stored);
Activation limiting means for restricting activation when it is determined that the address stored in the address storage means (vector table) is not within a predetermined range. Do not start if it is not the area actually stored)
It is characterized by having.
According to this feature, execution of unintended interrupt processing can be prevented in advance.

The gaming machine of the means 7 of the present invention is the gaming machine according to any one of the means 1 to 6,
Storage area setting means for setting a storage area (program / data area) in which a specific program is stored at the time of startup;
Specific program execution means (program execution by the main control unit 41) for executing processing according to a specific program stored in a storage area (program / data area) set by the storage area setting means;
Abnormality control execution means for executing abnormality control (illegal access reset) when the specific program execution means calls a program stored in an area other than the storage area (program / data area) set by the storage area setting means;
With
The predetermined range is characterized by including at least an address of an area where the specific program is stored.
According to this feature, execution of an unauthorized program can be prevented.

The gaming machine of the means 8 of the present invention is the gaming machine according to any one of the means 1 to 7,
A plurality of timer value storage areas (for example, one-byte timers A to C) are provided, and data storage means for storing data;
When any one of a plurality of types of timing conditions (for example, the timing conditions of the one-byte timers A to C) is satisfied, a timer value storage area (for example, the one-byte timer A) corresponding to the timing condition is satisfied. To C) a timer value storage means (main processing) for storing a timer value according to the timing condition;
Timer value updating means (time counter updating processing) capable of updating timer values stored in a plurality of timer value storage areas (for example, one-byte timers A to C) at predetermined intervals (about 2.24 ms);
With
Addresses (7E2Ch to 7E2Eh) that are continuous according to a predetermined rule (+1) are assigned to a plurality of timer value storage areas (for example, 1-byte timers A to C).
The timer value updating means performs a predetermined operation (designated address + 1) on an update process (a process of subtracting 1 from the value indicated by the pointer) for updating the timer value stored in the timer value storage area corresponding to the designated address. Thus, a plurality of types of timer values can be updated by repeatedly executing while changing the designated address for the timer value storage area.
According to this feature, continuous addresses are assigned to the plurality of timer value storage areas according to a predetermined rule, and an update process for updating the timer value stored in the timer value storage area corresponding to the specified address is performed by a predetermined process. When multiple types of timer values are updated by repeatedly executing while changing the designated address for the timer value storage area by performing the above operation, the process of updating multiple types of timer values is performed for each type of timer value Program capacity can be reduced.
It should be noted that continuous addresses are assigned according to a predetermined rule, for example, when a start address and an address added by N (N is a natural number) from the start address are assigned.
Further, changing the designated address for the timer value storage area by performing a predetermined operation means, for example, changing the designated address by adding or subtracting a value corresponding to the number of processes to the current designated address; Changing the designated address by adding or subtracting a constant from the reference address corresponds to this. At this time, the value or the constant according to the number of processes may be different depending on the storage capacity of the timer value. For example, if the timer value is stored byte by byte, the value according to the number of processes is equal to the number of processes. .. And the constant is 1. However, if the timer value is stored in units of 2 bytes, the value corresponding to the number of processes becomes 2, 4, 6,. , And the constant is 2.

  It should be noted that the present invention may have only the matters specifying the invention described in the claims of the present invention, or may have configurations other than the matters specifying the invention together with the matters specifying the invention described in the claims of the present invention. It may be something.

It is a front view of the slot machine of the example to which the present invention is applied. FIG. 3 is a perspective view showing the internal structure of the slot machine. FIG. 3 is a block diagram showing a configuration of the slot machine. FIG. 3 is a block diagram illustrating a configuration of a main control unit. FIG. 3 is a diagram illustrating a memory map of a RAM mounted on a main control unit. 6 is a flowchart illustrating control contents of an initial setting process executed by a main control unit. 6 is a flowchart illustrating control contents of a setting change process executed by a main control unit. 6 is a flowchart illustrating control contents of a main process executed by a main control unit. 9 is a flowchart illustrating the control content of a timer interrupt process (main) executed by a main control unit. 9 is a flowchart illustrating the control content of a timer interrupt process (main) executed by a main control unit. 5 is a flowchart illustrating control contents of a command storage process executed by a main control unit. 6 is a flowchart illustrating control contents of a normal command transmission process executed by a main control unit. 9 is a flowchart showing the control contents of a power-off command transmission process executed by the main control unit. 5 is a flowchart illustrating control contents of a power interruption process executed by a main control unit. 6 is a timing chart for explaining a control flow when the main control unit and the sub control unit are activated and when power is cut off. 5 is a flowchart illustrating control contents when a main control unit determines a value of a timer counter in a main process. FIG. 4 is a diagram illustrating a storage area of a timer counter in a RAM. 9 is a flowchart illustrating the control content of a time counter update process executed by a main control unit.

  Embodiments for implementing a gaming machine according to the present invention will be described below based on embodiments.

  An embodiment of a slot machine, which is a gaming machine to which the present invention is applied, will be described with reference to the drawings. As shown in FIG. 1, a slot machine 1 of the present embodiment And a front door 1b rotatably supported at the side end of the body 1a.

  As shown in FIG. 2, inside the housing 1a of the slot machine 1 of this embodiment, reels 2L, 2C, and 2R (hereinafter, left reel, middle reel, right reel) on which a plurality of types of symbols are arranged on the outer periphery. ) Are arranged side by side in the horizontal direction, and as shown in FIG. 1, three continuous symbols among the symbols arranged on the reels 2L, 2C, and 2R can be seen from the see-through window 3 provided on the front door 1b. Are arranged as follows.

  On the outer peripheral portions of the reels 2L, 2C, 2R, a predetermined number of symbols (identification information) of a plurality of types that can be identified from each other are drawn in a predetermined order. The symbols drawn on the outer peripheral portions of the reels 2L, 2C, 2R are displayed in upper, middle, lower, and upper tiers, respectively, in the see-through window 3 provided substantially at the center of the front door 1b.

  Each of the reels 2L, 2C, 2R is rotated by a correspondingly provided reel motor 32L, 32C, 32R (see FIG. 3), so that the symbols of the respective reels 2L, 2C, 2R are continuously connected to the see-through window 3. While the reels 2L, 2C, and 2R are stopped rotating, three consecutive symbols are derived and displayed on the see-through window 3 as a display result.

  Inside the reels 2L, 2C, 2R, a reel sensor 33L, 33C, 33R for detecting a reference position and a reel LED 55 for irradiating the reels 2L, 2C, 2R from the back are provided for the reels 2L, 2C, 2R, respectively. , Are provided. The reel LED 55 includes twelve LEDs corresponding to three consecutive symbols on the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  A display area 51a of a liquid crystal display 51 (see FIG. 1) is arranged at a position on the front side (player side) of each of the reels 2L, 2C, 2R of the front door 1b. The liquid crystal display 51 has a liquid crystal panel having transparency when no voltage is applied to the liquid crystal element. The liquid crystal display 51 is provided with a transparent region 51 b corresponding to the transparent window 3 of the display region 51 a and a transparent window 3. Each reel 2L, 2C, 2R can be visually recognized from the player side.

  In the front door 1b, as shown in FIG. 1, a medal insertion section 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and a credit (the number of medals stored as a game value owned by the player). The MAXBET switch 6, which is operated when setting the maximum bet number among the predetermined number of bets determined according to the game state within the range, setting of medals and bets stored as credits The adjustment switch 10 operated when the medals used in the game are settled (the medals used for setting the credit and the bet amount are returned), the start switch 7 operated when starting the game, the reels 2L, 2C And stop switches 8L, 8C, 8R which are operated when stopping the rotation of the 2R, respectively, are provided so as to be operable by the player.

  As shown in FIG. 1, the front door 1b displays a credit indicator 11 displaying the number of medals stored as credits, and shows the number of medals paid out due to the occurrence of a prize and the contents of the error when an error occurs. A game auxiliary display 12 for displaying an error code, etc., a 1 BET LED 14 for notifying by light that the bet number is set to 1, a 2 BET LED 15 for notifying by light that the bet number is set to 2, and a setting of 3 bet numbers A 3BET LED 16 for notifying that the game has been started, a request LED 17 for notifying that a medal can be inserted, and a start valid LED 18 for notifying that the start operation of the game by operating the start switch 7 is effective. , Wait (because a certain period of time has not elapsed since the last game started, reel rotation starts Waiting to have state) in wait for notifying by lighting the effect that in LED 19, a game display section 13 in the replay LED20 is provided for informing it is provided by lighting the effect that during replay game, which will be described later.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 3) for notifying by lighting that the setting operation of the bet amount by operating the MAXBET switch 6 is valid, and the stop switches 8L, 8C, Inside the 8R, left, middle, and right stop valid LEDs 22L, 22C, and 22R (see FIG. 3) are provided to notify by lighting that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is valid. Have been.

  As shown in FIG. 2, inside the front door 1b, as shown in FIG. 2, a reset switch 23 for detecting a reset operation for releasing an error state described later and a hit state described later by a predetermined key operation, and a change of a set value described later A set value display 24 on which the set value at that time is displayed during or while the set value is being checked. A hit control for controlling a stop state (a state in which the progress of the game is restricted until a reset operation is performed) at a predetermined opportunity A hitting switch 36a for selecting the validity / invalidity of the stopping function, an automatic control for controlling the automatic payment processing (processing for paying out (returning) a medal stored as a credit regardless of a player's operation) at a predetermined timing. An automatic payment switch 36b for selecting the validity / invalidity of the payment function, and a flow path of the medals inserted from the medal insertion section 4 are connected to a hopper tank 34a (described later) provided inside the housing 1a. 2) A flow path switching solenoid 30 for selectively switching to either the medal payout exit 9 side or the medal payout exit 9 side, and an inserted medal sensor 31 that detects medals that are inserted from the medal insertion section 4 and flow down to the hopper tank 34a side. A medal selector 29 having an insertion port sensor 26 for detecting insertion of a foreign substance on the upstream side of the insertion medal sensor 31 and a door open detection switch 25 (see FIG. 3) for detecting an open state of the front door 1b are provided.

  As shown in FIG. 2, the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R (see FIG. 3) and the reel reference positions of the reels 2L, 2C, and 2R are respectively provided inside the housing 1a. A reel unit 2 including detectable reel sensors 33L, 33C, 33R (see FIG. 3), an external output board 1000 (see FIG. 3) for outputting an external output signal, and storing medals inserted from the medal insertion section 4. Hopper tank 34a, a hopper motor 34b (see FIG. 3) for paying out medals stored in the hopper tank 34a from the medal payout port 9, and a payout sensor 34c for detecting medals paid out by driving the hopper motor 34b ( (See FIG. 3) and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 for storing medals overflowing from the hopper tank 34a is provided. Inside the overflow tank 35, there is provided a full sensor 35a (see FIG. 3) for detecting that the stored medals are full.

  As shown in FIG. 2, the front of the power supply box 100 functions as a setting key switch 37 for switching to a setting change state or a setting confirmation state, and functions as a reset switch for canceling an error state or a stop state in a normal state. In a setting change state, a reset / setting switch 38 functioning as a setting switch for changing a setting value of a winning probability (a payout rate) of an internal lottery described later, and a power supply operated when turning on / off the power supply A switch 39 is provided.

  The power supply box 100 is provided inside the housing 1a, and the front door 1b is provided on the front of the power supply box 100 because the front door 1b can be opened by a predetermined key operation held by a clerk or the like. The set key switch 37, the reset / setting switch 38, and the power switch 39 can be operated only by a person such as a clerk having the key, and cannot be operated by the player. The same applies to the reset switch 23 detected by a predetermined key operation. In particular, since the setting key switch 37 requires further key operation after opening the front door 1b by key operation, among the clerks at the amusement arcade, only the clerk having the key for operating the setting key switch 37 is available. Operation is allowed.

  When playing a game in the slot machine 1 of this embodiment, first, medals are inserted from the medal insertion unit 4 or the number of bets is set using credits. To use the credit, the MAXBET switch 6 may be operated. When a predetermined number of bets set according to the game state is set, the pay line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the game can be started. Become. When medals are inserted in more than the maximum number among the prescribed numbers corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether the combination of the symbols displayed in the perspective windows 3 of the reels 2L, 2C, and 2R is a combination of the winning symbols. In the present embodiment, as shown in FIG. 1, only the winning line LN set across the middle row of the reel 2L, the middle section of the reel 2C, and the middle section of the reel 2R, that is, the middle row, is a winning line. Stipulated. In this embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

  Further, in this embodiment, in order to make it easy to recognize that the combination of the symbols constituting the prize is arranged in the prize line LN, the invalid lines LM1 to LM4 are set separately from the prize line LN. The invalid lines LM1 to LM4 are not determined based on the combination of the symbols arranged on the invalid lines LM1 to LM4. When the combination of the symbols constituting the specific prize is arranged on the prize line LN, the invalid lines LM1 to LM4 are invalid. When a combination of symbols (for example, bell-bell-bell) that wins when the winning line LN is aligned with any of the LM1 to LM4 is arranged, a symbol forming a specific winning on the winning line LN is formed. This is to make it easy to recognize that the combination is complete.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, 2R rotate, and the symbols on the reels 2L, 2C, 2R change continuously. When any of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the see-through window 3.

  When one of the reels 2L, 2C, and 2R is stopped, one game is completed, and a predetermined symbol combination (hereinafter, also referred to as a combination) is displayed on each of the reels 2L, 2C, and 2R on the winning line LN. As a result, when the game stops, a prize is generated, and a predetermined number of medals are awarded to the player according to the prize and added to the credit. When the number of credits reaches the upper limit (50 in this embodiment), medals are paid directly from the medal payout port 9 (see FIG. 1). Further, when a combination of symbols accompanied by a transition of the gaming state is stopped on the pay line LN as a result of displaying the reels 2L, 2C, 2R, the game state is shifted to a gaming state corresponding to the combination of the symbols. .

  In this embodiment, the game starts when the operation of the start switch 7 is detected in a state where the operation of the start switch 7 is valid, and ends when all the reels stop. One unit of control (game control) for executing the game is started when all controls accompanying the end of the previous game are completed, and when all controls accompanying the end of the game are completed. finish.

  Further, in the present embodiment, the configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, and a configuration using four or more reels may be used. In a configuration using two or more reels, the winning may be determined based on a combination of display results derived for all of the two or more reels. Further, in this embodiment, the variable display device is constituted by physical reels, but the variable display device may be constituted by an image display device such as a liquid crystal display.

  Further, in the slot machine 1 according to the present embodiment, after the game is started and the reels 2L, 2C, 2R are rotated and the symbols start to change, one of the stop switches 8L, 8C, 8R is operated. Then, the rotation of the reel corresponding to the stop switch 8L, 8C, 8R is stopped, and the symbol is stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (millisecond).

  The reels 2L, 2C, and 2R rotate 80 times per minute, and change 80 × 21 (the number of symbols per reel) = 1,680 symbols, so that a maximum of four symbols are drawn during 190 ms. You can do it. That is, the symbols that can be selected as the stop symbols are the symbols displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols four frames away from the symbols, for a total of five symbols.

  Therefore, for example, when one of the stop switches 8L, 8C, and 8R is operated and the symbol displayed on the lower row of the reel corresponding to the stop switch is set as a reference, the symbol from the symbol to four frames ahead is displayed. Since the symbol can be displayed in the lower row, when one of the stop switches 8L, 8R is operated on each of the reels 2L, 2C, 2R, the symbol displayed in the middle row of the reel corresponding to the stop switch is operated. Can be displayed on the winning line, including symbols arranged within five frames.

  Hereinafter, the reels 2L, 2C, and 2R may be simply referred to as reels unless it is particularly necessary to distinguish them. The reel 2L may be referred to as a left reel, the reel 2C may be referred to as a middle reel, and the reel 2R may be referred to as a right reel. An operation of stopping the reels 2L, 2C, 2R by operating the stop switches 8L, 8C, 8R may be referred to as a stop operation.

  FIG. 3 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 3, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. Is produced, and a drive power supply for the electric components constituting the slot machine 1 is generated by the power supply board 101 and supplied to each unit.

  A power supply of AC 100 V is supplied to the power supply board 101 from the outside, and a DC voltage required for driving the electric components constituting the slot machine 1 is generated from the power supply of AC 100 V, and the game control board 40 and the production control board 90. It is supplied to. The hopper motor 34b, the payout sensor 34c, the full tank sensor 35a, the setting key switch 37, the reset / setting switch 38, and the power switch 39 are connected to the power supply board 101.

  On the game control board 40, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, 8R, the settlement switch 10, the reset switch 23, the stop switch 36a, the automatic settlement switch 36b, the inserted medal sensor 31, and the door opening are provided. The detection switch 25, the reel sensors 33L, 33C, 33R are connected, and the payout sensor 34c, the full tank sensor 35a, the setting key switch 37, and the reset / setting switch 38 are connected via the power supply board 101, The detection signals of these connected switches are input. In addition, the game control board 40 includes the above-described credit indicator 11, game assist indicators 12, 1 to 3 BET LEDs 14 to 16, insertion request LED 17, start valid LED 18, waiting LED 19, replay LED 20, BET switch valid LED 21, , Middle and right stop effective LEDs 22L, 22C, 22R, a set value display 24, a flow path switching solenoid 30, and reel motors 32L, 32C, 32R are connected, and the hopper motor 34b described above is connected via a power supply board 101. These electric components are connected and driven based on the control of a main control unit 41 described later mounted on the game control board 40.

  The game control board 40 includes a main control unit 41 that performs processing relating to the progress of the game, a control clock generation circuit 42 that generates a control clock CCLK, a random number clock generation circuit 43 that generates a random number clock RCLK, and switches. A switch detection circuit 44 which takes in the input detection signal and transmits it to the main control unit 41, a motor drive circuit 45 which transmits a motor drive signal (phase signal of the stepping motor) to the reel motors 32L, 32C, 32R, and a solenoid drive signal. A solenoid drive circuit 46 for transmitting the flow path switching solenoid 30; an LED drive circuit 47 for transmitting the LED drive signal to various displays and LEDs; and a voltage drop signal indicating the voltage drop when the voltage drop is detected. The power failure detection circuit 48 outputs a signal when the power is turned on or when the power is turned off. Source reset circuit 49 to provide the system reset signal to the main control unit 41 is mounted in an unstable state.

  FIG. 4 shows a configuration example of the main control unit 41 mounted on the game control board 40. 4 is a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a matching block 503, a unique information storage circuit 504, an arithmetic circuit 505, and a reset / interrupt. A controller 506, a CPU (Central Processing Unit) 41a, a ROM (Read Only Memory) 41b, a RAM (Random Access Memory) 41c, a free-run counter circuit 507, random number circuits 508a and 508b, a timer circuit 509, An interrupt controller 510, a parallel input port 511, a serial communication circuit 512, a parallel output port 513, and an address decode circuit 514 are provided. The reset / interruption controller 506 includes an out-of-designation area prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b.

  The reset / interrupt controller 506 controls various reset and interrupt requests generated inside and outside the main control unit 41. The reset / interruption controller 506 includes an out-of-designation area prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit for monitoring whether or not the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when detecting that the user program has been executed outside the designated area. In addition, the watchdog timer 506b has a function of generating a timeout signal every set period.

  The external bus interface 501 is a bus interface having an interface function between an external bus and an internal bus of a chip constituting the main control unit 41, an address bus, a data bus, and a direction control function of each control signal. The clock circuit 502 is a circuit that generates the internal system clock SCLK by dividing the control clock CCLK by two or the like. The verification block 503 has a function of connecting to an external verification machine and verifying a chip. The unique information storage circuit 504 is a circuit that stores a plurality of types of unique information serving as internal information of the main control unit 41. The arithmetic circuit 505 is a circuit that performs multiplication and division.

  The CPU 41a is a control CPU that executes a game control in the slot machine 1 by executing a user program (a game control processing program for game control) based on the control code read from the ROM 41b. When such game control is executed, a fixed data reading operation in which the CPU 41a reads fixed data from the ROM 41b, a variable data writing operation in which the CPU 41a writes various variable data in the RAM 41c and temporarily stores the same, and the CPU 41a is temporarily stored in the RAM 41c. A variable data reading operation for reading various kinds of variable data, a reception operation in which the CPU 41a receives an input of various signals from outside the main control unit 41 via the external bus interface 501, the parallel input port 511, the serial communication circuit 512, and the like; A transmission operation of outputting various signals to the outside of the main control unit 41 via the external bus interface 501, the serial communication circuit 512, the parallel output port 513, and the like is also performed.

  The ROM 41b stores control codes indicating user programs (game control processing programs for game control), fixed data, and the like. The RAM 41c provides a work area for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power supply. That is, even if the power supply to the slot machine 1 is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period.

  As the free-run counter circuit 507, an 8-bit free-run counter is mounted. The random number circuits 508a and 508b are circuits that generate numerical data such as an 8-bit random number and a 16-bit random number, which are random numbers having a predetermined update range. In this embodiment, the hardware random number generated by the 16-bit random number circuit 508b among the random number circuits 508a and 508b is used as a random number for an internal lottery described later. The timer circuit 509 is a 16-bit programmable timer, counts down the set timer value based on the input of the control clock CCLK, and outputs an interrupt request signal to the interrupt controller when the timer value reaches 0000h. In this embodiment, it is possible to perform a periodic interrupt request and time measurement using the timer circuit 509.

  The interrupt controller 510 is a circuit that controls an external interrupt request from an interrupt terminal and an internal peripheral circuit (for example, a serial communication circuit 512, random number circuits 508a and 508b, and a timer circuit 509). . The parallel input port 511 includes an input-only port having a width of 8 bits. The parallel output port 513 included in the main control unit 41 shown in FIG. 4 has a built-in 11-bit width dedicated output port. The serial communication circuit 512 is a circuit that performs asynchronous serial communication in input / output to / from the outside.

  The address decode circuit 514 is a circuit for decoding each functional block inside the main control unit 41 and decoding a chip select signal which is a decode signal for an external device. The chip select signal allows the internal circuit of the main control unit 41 or an external device serving as a peripheral device to selectively operate effectively, thereby enabling access from the CPU 41a.

  FIG. 5 is an address map of a memory area used by the main control unit 41. As shown in FIG. 5, the memory area used by the main control unit 41 includes a memory area (0000h to 7FFFFh) allocated to the RAM 41c and a memory area (8000h to FFFFh) allocated to the ROM 41b.

  The memory area of the RAM 41c includes an available area (0000h to 01FFh) usable as a work, and an internal function register area (1000h to 1000FF) in which a register group for controlling each function mounted on the main control unit 41 is stored. 1080h) and unused areas where access is prohibited (0200h to 0FFFh, A800h to FFFFh).

  The memory area of the ROM 41b includes a program / data area (8000h to A6FFh) in which programs and fixed data are stored, a ROM comment area (A700h to A7FFh) in which arbitrary data such as a program title and version can be set, and a CALLV A vector table area (A780h to A7A7h) in which a head address of an instruction subroutine and a head address of interrupt processing are set, and an HW parameter in which a parameter for setting an internal function of the main control unit 41 by hardware is set. Area (addresses A7A8h to A7FFh) and unused areas (A800h to FFFFh) where access is prohibited.

  The parameters set in the HW parameter area include the last address (HPREND) of the ROM area used in the program / data area, the start address (HRAMSTAT) and the last address (HRAMEND) of the RAM area whose access is prohibited.

  When there is an access to an area between the address set in HPREND and A6FFh, that is, an area in the program / data area where no program or the like is stored, the main control unit 41 sets the address set in HRAMSTAT. From the address set in the HRAMEND to the HWEND area, that is, when there is an access to the area for which access is prohibited among the available areas, when there is an access to the ROM comment area, and when there is an access to the ROM comment area. Is determined to be an unauthorized access, an illegal access reset is generated. When an illegal access reset occurs, the state is controlled to a special error state described later, the progress of the game is disabled, and the state shifts to a setting change state, which is not released until a new set value is set.

  As described above, the main control unit 41 determines whether an access is made to an area where a program or the like is not stored in the program / data area, or an access is made to an area of the available area for which access is prohibited. That is, by causing an illegal access reset when an access is made to a memory area that is not accessed in a normal operation, the progress of the game is disabled, so that it is not related to an unused area or operation of the ROM 41b. Even if an unauthorized program is stored in an area, an unused area of the RAM 41c, or the like, the execution of the unauthorized program can be prevented.

  The main control unit 41 is activated by the occurrence of the system reset due to the input of the system reset signal, the WDT reset by the WDT 506b, and the above-mentioned illegal access reset. At this time, the value set in the vector table area is set. Is 0000h (a value set in an unused vector table area) or a value indicating an area of an address set from 8000h to HPRGEND, that is, a value indicating an area in the program area where a program or the like is actually stored. If the value set in the vector table area is neither 0000h nor a value indicating the area of the address set from 8000h to HPRGEND, the system is not activated.

  As described above, the main control unit 41 starts up when the value set in the vector table area, that is, the start address of the subroutine of the CALLV instruction and the start address of the interrupt processing are values indicating outside the area where the program is set. By not doing so, it is possible to prevent in advance that an unintended process is executed due to the occurrence of an interrupt or the like.

  The main control unit 41 transmits various commands to the sub control unit 91 via the parallel output port 513. The command transmitted from the main control unit 41 to the sub control unit 91 is transmitted in only one direction, and the command is not transmitted from the sub control unit 91 to the main control unit 41. In the present embodiment, the command is transmitted to the sub-control unit 91 via the parallel output port 513, that is, the command is transmitted as a parallel signal. A configuration for transmitting a command to the sub-control unit 91, that is, a configuration for transmitting the command as a serial signal may be employed.

  In addition, the main control unit 41 receives detection states of various switches connected to the game control board 40 from the parallel input port 511. Then, the main control unit 41 executes a basic process of shifting stepwise according to the detection states of various switches input from the parallel input port 511. Further, the main control unit 41 can execute the interrupt process by interrupting the basic process when an interrupt occurs. In the present embodiment, a timer interrupt process (main), which will be described later, is executed when a timeout has occurred in the timer circuit 509, that is, at regular time intervals (about 0.56 ms in the present embodiment). Further, the main control unit 41 is set to prohibit other interrupts during execution of the interrupt processing, and when a plurality of interrupts occur simultaneously, the main control unit 41 gives priority to a predetermined order. Interrupts to execute are set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt occurs at that time. It will be.

  The main control unit 41 repeatedly loops processing according to the control state until the detection state of various switches connected to the game control board 40 changes as basic processing, and responds to the change in the detection state of various switches. Execute the process of shifting in stages. In addition, the main control unit 41 executes the timer interrupt processing (main) at regular time intervals (about 0.56 ms in the present embodiment). Note that the execution interval of the timer interrupt processing (main) is set to a time longer than the sum of the time taken for the repetition of the processing according to the control state in the basic processing and the execution time of the timer interrupt processing (main). Thus, at least one cycle of the process repeated according to the control state between the current and next timer interrupt processes (main) is performed at least.

  The rendering control board 90 is connected to rendering devices such as a liquid crystal display 51, rendering effect LEDs 52, speakers 53 and 54, reel LEDs 55, and the like. These rendering devices include sub-controls mounted on the rendering control board 90 and described later. It is driven based on the control by the unit 91. In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, and the reel LED 55. However, an output control unit that directly performs output control of the effect device separately from the sub-control unit 91 is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output pattern of the rendering device may be determined, and the output control unit may control the output of the rendering device based on the output pattern determined by the sub-control unit 91. In such a configuration, the sub-control unit 91 and the output control The output control of the rendering device is performed by both of the units. Further, in the present embodiment, the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, and the reel LED 55 are illustrated as the effect devices, but the effect device is not limited to these, and for example, a display that is driven mechanically. A device or a mechanically driven role object may be applied as the rendering device.

  The effect control board 90 is composed of a microcomputer having a sub CPU 91a, a ROM 91b, a RAM 91c, and an I / O port 91d, and a sub control unit 91 for controlling the effect, and a liquid crystal display connected to the effect control board 90. A display control circuit 92 for controlling display of the display 51; an effect effect LED 52; an LED drive circuit 93 for controlling drive of the reel LED 55; an audio output circuit 94 for controlling audio output from the speakers 53 and 54; A reset circuit 95 for giving a reset signal to the sub CPU 91a when no initialization command is input for a certain period of time, a switch detection circuit 96 for detecting a detection signal input from switches connected to the effect control board 90, date information and time Clock device 97 for outputting time information including information, slot machine 1 A power cutoff detection circuit 98 for monitoring the supplied power supply voltage and outputting a voltage drop signal to the sub CPU 91a when a voltage drop is detected to the sub CPU 91a, and other circuits are mounted. The CPU 91a receives commands transmitted from the game control board 40, performs various controls for performing the effect, and directly or indirectly controls each unit of the control circuit mounted on the effect control board 90.

  In the reset circuit 95, the voltage at which the reset signal is released is set lower than that of the reset circuit 49 that supplies a system reset signal to the main control unit 41 in the game control board 40. When the power is turned on, the sub control unit 91 performs the main control. It is designed to be started earlier than the section 41. On the other hand, in the power interruption detection circuit 98, the voltage at which the voltage drop signal is output is set to be lower than that of the power interruption detection circuit 48 which outputs the voltage drop signal to the main control unit 41 in the game control board 40. In, the sub-control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  The sub-control unit 91 has an interrupt function similarly to the main control unit 41, generates an interrupt when receiving a command from the main control unit 41, and acquires the command transmitted from the main control unit 41. , Execute the command reception interrupt processing stored in the buffer. Further, the sub-control unit 91 generates an interrupt every time the number of input system clocks reaches a certain number, that is, at certain time intervals (about 2 ms), and executes a timer interrupt process (sub) described later. Further, unlike the main control unit 41, when an interrupt occurs based on the reception of a command, the sub-control unit 91 interrupts the timer interrupt process (sub) even during execution of the process. , A command reception interrupt process is executed, and even if interrupts that trigger the timer interrupt process (sub) occur simultaneously, the command reception interrupt process is executed with the highest priority. The backup power is also supplied to the sub-control unit 91 at the time of a power failure, and the data stored in the RAM 91c is retained while the backup power is supplied.

  In the slot machine 1 of the present embodiment, the payout rate of medals changes according to the set value. More specifically, the medal payout rate is changed by using a winning probability according to a set value in a lottery that affects the degree of advantage to a player, such as an internal lottery, a navigation stock lottery, and an additional lottery described later. The set value is made up of six levels from 1 to 6, with 6 being the highest payout rate and the payout rate decreasing as the value decreases in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is the highest for the player, and as the value decreases in the order of 5, 4, 3, 2, and 1, the advantage gradually decreases.

  To change the set value, it is necessary to turn on the power of the slot machine 1 after turning on the setting key switch 37. When the power is turned on with the setting key switch 37 in the ON state, the setting value read from the RAM 41c is displayed on the setting value display 24 as a display value, and the setting value can be changed by operating the reset / setting switch 38. Move to change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the set value display 24 is updated by one (when further operated from the set value 6, the set value is changed to 1). Return). Then, when the start switch 7 is operated, the display value is determined as the set value. Then, when the setting key switch 37 is turned off, the determined display value (set value) is stored in the RAM 41c of the main control unit 41, and the game shifts to a state where the game can proceed.

  Note that, when the power is turned on while the setting key switch 37 is ON, the configuration may be changed to the setting change state on condition that the door opening detection switch 25 detects that the front door 1b is opened. By adopting such a configuration, it is possible to prevent the setting from being illegally changed while the front door 1b is not opened. Further, in a configuration in which the state is changed to the setting change state on condition that the detection corresponding to the opening of the front door 1b is performed, the door opening detection switch 25 is used to respond to the opening of the front door 1b after shifting to the setting change state. It is preferable that the setting change state is maintained even if the detection of the change is not performed. Therefore, even if the front door 1b is temporarily closed during the setting change, the operation for shifting to the setting change state again is performed. It is not necessary, and the setting change operation does not become complicated. When the setting key switch 37 is turned off after the start switch 7 is operated and the set value is determined after shifting to the setting change state, the door opening detection switch 25 detects the opening corresponding to the opening of the front door 1b. It is also possible to adopt a configuration in which the setting change state is ended and the game can proceed to a possible state, provided that the front door 1b is not opened even in such a configuration. It is possible to prevent the setting from being changed.

  Further, in order to confirm the set value, the setting key switch 37 may be turned on after the game is over and the bet amount is not set. If the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 41c is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the progress of the game is not possible, and the setting key switch 37 is turned off, thereby terminating the setting confirmation state and returning to a state in which the game can proceed.

  When the setting key switch 37 is turned ON after the game is over and the bet amount is not set, the door open detection switch 25 must detect that the front door 1b has been opened. Alternatively, the configuration may be changed to a setting confirmation state. With such a configuration, it is possible to prevent a setting value from being illegally confirmed in a state where the front door 1b is not opened. Further, in a configuration in which the state is shifted to the setting confirmation state on condition that the detection corresponding to the opening of the front door 1b is performed, the door opening detection switch 25 responds to the opening of the front door 1b after shifting to the setting confirmation state. It is preferable that the setting confirmation state be maintained even if the detection of the setting is not detected. Therefore, even if the front door 1b is temporarily closed during the setting confirmation, the operation for shifting to the setting confirmation state again is performed. It is not necessary, and the setting confirmation operation does not become complicated. When the setting key switch 37 is turned off after the start switch 7 is operated and the set value is determined after shifting to the setting confirmation state, the door opening detection switch 25 detects the opening corresponding to the opening of the front door 1b. It is also possible to have a configuration in which the setting confirmation state is terminated and the game can be advanced to a state in which the game can be advanced, provided that the front door 1b is not opened even in such a configuration. It is possible to prevent the setting value from being confirmed.

  In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not the voltage drop signal from the power interruption detection circuit 48 is detected every time the timer interrupt processing (main) is executed. When the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process, the power interruption process (main) for setting data for determining whether the data in the RAM 41c is normal at the next recovery is performed. Execute.

  Then, the main control unit 41 returns the processing state of the main control unit 41 to the state before the power failure based on the data stored in the RAM 41c on condition that the data in the RAM 41c is normal at the time of activation. However, when the data of the RAM 41c is not normal, it is determined that the RAM is abnormal, the RAM abnormal error code is set in the register, the state is controlled to the RAM abnormal error state, and the progress of the game is disabled.

  The error state is a normal error state that is released by a reset operation (operation of the reset / setting switch 38 or the reset switch 23), and the state is changed to the above-described setting change state and is released until a new set value is set. There is no special error state, and the RAM abnormal error state is a special error state. Once controlled to the RAM abnormal error state, the state shifts to the setting change state and is released until a new set value is set Never be.

  The sub-control unit 91 also determines whether or not the voltage drop signal from the power interruption detection circuit 98 has been detected in the timer interrupt processing (sub), and when it is determined that the voltage drop signal has been detected, At the next recovery, a power interruption process (sub) for setting data for determining whether the data in the RAM 91c is normal is executed.

  Then, the sub-control unit 91 returns the processing state of the sub-control unit 91 to the state before the power interruption based on the data stored in the RAM 91c, on condition that the data in the RAM 91c is normal at the time of activation. However, if the data in the RAM 91c is not normal, it is determined that the RAM is abnormal, and the RAM 91c is initialized. In this case, unlike the main control unit 41, the execution of the effect is not disabled only by initializing the RAM 91c.

  Further, even when it is determined that the data in the RAM 91c is normal at the time of the startup, the sub-control unit 91 receives the setting command described later indicating that the state has shifted to the setting change state from the main control unit 41. The RAM 91c is also initialized when neither the later-described return command nor the setting command indicating that the control state of the main control unit 41 has returned after a certain period of time has elapsed. Also in this case, the execution of the effect is not disabled only by initializing the RAM 91c.

  Next, initialization of the RAM 41c of the main control unit 41 will be described. The usable area of the storage area of the RAM 41c of the main control unit 41 is divided into an important work, a special work, a general work, an unused area, and a stack area, and an important work, a special work, a general work, and an unused area. , And the stack area.

  In this embodiment, the main control unit 41 determines whether the data in the RAM 41c is destroyed when the setting key switch 37 is turned off and the data in the RAM 41c is destroyed when the setting key switch 37 is turned on. When the data is not destroyed, when the setting key switch 37 is turned on and the data in the RAM 41c is destroyed, when the setting change is completed, when a specific game state is completed, and when one game is completed, the number is changed from six. When the following initialization conditions are satisfied, four types of initialization with different areas to be initialized are performed according to the respective initialization conditions.

  Initialization 0 is performed when the data in the RAM 41c is destroyed when the setting key switch 37 is turned off and the data in the RAM 41c is destroyed when the setting key switch 37 is started while the setting key switch 37 is turned on. In the initialization 0, all the available areas are initialized. Initialization 1 is an initialization performed when the setting key switch 37 is turned on and the data in the RAM 41c is not destroyed at the time of startup. In the initialization 1, the usable area other than the important work and the special work is included. Area is initialized. The initialization 2 is an initialization performed at the end of a specific gaming state. In the initialization 2, a general work, an unused area, and an unused stack area among available areas are initialized. The initialization 3 is an initialization performed at the end of one game. In the initialization 3, an unused area and an unused stack area of the available area are initialized. The storage area for the set value and the data indicating the gaming state is allocated to the special work, and when the data in the RAM 41c is not destroyed at the time of startup with the setting key switch 37 being ON, ie, the data in the RAM 41c If the setting is changed normally, the data indicating the set value and the game state will be held. A storage area for a timer counter, which will be described later, is allocated to a special work, and is held without being initialized at the end of a game or at the end of a specific game state.

  In the slot machine 1 of the present embodiment, a specified number of bets that can be set according to the game state is determined, and the game is performed on the condition that the specified number of bets is set according to the game state. Can be started. In the present embodiment, the pay line LN is activated when a prescribed number of bets is set according to the gaming state.

  In this embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line (in this embodiment, all the pay lines are always activated. A winning combination is achieved when a combination of symbols called combinations is arranged on the winning line that has been formed (hereinafter, simply referred to as a winning line). The combination may be a combination of the same symbols or a combination including different symbols.

  The types of winning combinations are determined according to the state of the game, but can be broadly divided into small winning combinations with medal payout and re-starting so that the next game can be started without setting the number of bets. There are a gaming role and a special role accompanied by a transition to a gaming state advantageous to the player. Hereinafter, the small role and the replaying role are also collectively referred to as a general role. In order for the winning of each combination determined according to the gaming state to occur, it is necessary to win the internal lottery described later and set the winning flag of the combination in the RAM 41c. Note that among the winning flags of these roles, the winning flags of the small role and the replaying role are valid only in the game in which the flag is set, and are invalid in the next game. The combination is enabled until the combination of the permitted combinations is completed by the flag, and is invalid in the game in which the combination of the permitted combinations is completed. That is, once the special combination winning flag is won, even if the combination of combinations permitted by the flag cannot be aligned, the winning flag is not invalidated and is carried over to the next game. Becomes

  Hereinafter, the internal lottery of the present embodiment will be described. In the internal lottery, the main control unit 41 determines whether or not to permit winning of each of the above-mentioned roles before the display results of all the reels 2L, 2C, and 2R are derived (specifically, the start switch 7). At the time of detection). In the internal lottery, first, when the start switch 7 is detected, a random number for the internal lottery (an integer from 0 to 65535) is obtained. Specifically, the value generated by the random number circuit 508b and stored in the random number value register of the random number circuit 508b is set in the lottery work assigned to the RAM 41c. Then, for each combination determined according to the gaming state, according to the numerical data stored in the lottery work and the number of judgment values of each combination determined according to the current gaming state, the number of bets and the set value. It is determined whether or not a prize is allowed.

  In the internal lottery, the number of determination values determined according to the role to be subjected to the internal lottery, the current game state and the set value are sequentially changed to the random number value for the internal lottery (numerical data stored in the lottery work). If the result of the addition overflows, it is determined that the winning combination has been won. For this reason, the winning combination is determined based on the probability (the number of judgment values / 65536) according to the magnitude of the number of judgment values.

  When the winning of any of the winning combinations is determined, the winning flag corresponding to the winning-determined winning combination is set in the internal winning flag storing work allocated to the RAM 41c. The internal winning flag storage work is composed of a 2-byte storage area, of which the upper byte is assigned as a special role storing work in which the special role winning flag is set, and the lower byte is a general role winning work. Assigned as a general role storage work for which the flag is set. Specifically, when the special combination is won, the special combination winning flag indicating that the special combination has been won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When the general role is won, a general role winning flag indicating that the general role has been won is set in the general role storing work. If any of the combinations and combinations of combinations are not won, only the general combination storage work is cleared.

  Next, stop control of the reels 2L, 2C, 2R will be described. The main control unit 41 refers to the table index and the table creation data stored in the ROM 41b when the rotation of the reels has started and when the reels have stopped and the reels that are still rotating still remain. Then, a stop control table is created for each rotating reel. The stop control table is data that can specify the number of sliding frames for each timing when the stop operation is performed. When any one of the stop switches 8L, 8C, 8R corresponding to the spinning reel is effectively detected, the stop control table of the corresponding reel is referred to, and the slippage of the stop control table referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In this embodiment, a value of 0 to 4 is determined as the number of sliding frames, and it is possible to stop the reel by drawing up to four symbols after detecting the stop operation. In other words, the stop position of the symbol can be specified from a range of up to five frames including the stop operation position where the stop operation is detected. Further, since it is necessary to move one frame to move the reel for one symbol, it is possible to draw up to four symbols and stop the reel after detecting the stop operation. The stop position of the symbol can be designated from a maximum of five symbols including the operation position.

  In the present embodiment, if any one of the winning combinations is won, when the stop operation is performed, the winning combinations within the pull-in range of a maximum of four frames can be aligned and stopped on the pay line. If possible, a control is performed to stop the rolls in a uniform manner, and for the winning combination, a control is performed to stop the rolls without aligning them in the pull-in range of a maximum of four frames. When the special role and the small role are elected at the same time, such as when the small role is elected while the special role has been carried over from before the previous game, when the stop operation is performed, the maximum If it is possible to stop all the winning combinations in the 4-frame pull-in range, control is performed to align and stop the winning small roles. If it is not possible to draw in, if it is possible to stop all the special roles that have been won in the pay-in range of a maximum of four frames on the winning line, control will be performed to align and stop them. That is, control is performed to stop the four frames without being aligned in the pull-in range. That is, in such a case, the control for aligning the small role on the pay line is given priority over the special role, and the special role can be won only when the small role cannot be drawn. When the special role and the small role can be drawn in at the same time, only the small role is drawn in, and the small role and the special role are not aligned on the winning line at the same time. In addition, when the special role and the small role are elected at the same time, the control to arrange the special role on the winning line has priority over the small role, and only when the special role cannot be drawn, the small role is placed on the winning line. Alignment control may be performed.

  Further, in the present embodiment, when the special role and the replaying role are simultaneously won, for example, when the replaying role is won while the special role has been carried over from before the previous game, a stop operation is performed. At this time, a control is performed in which the symbols of the replaying game are aligned and stopped within a pull-in range of a maximum of four frames on the winning line. In this case, the symbols constituting the replaying game or the symbols forming the replaying game simultaneously won are arranged within 5 symbols, that is, at intervals of 4 frames or less on any of the reels 2L, 2C and 2R. Since the stop can be stopped at an arbitrary position within the pull-in range of 4 frames, if the special role and the replaying role are simultaneously won, regardless of the operation timing of the stop switches 8L, 8C, 8R by the player. Instead, the re-game players will always win. In other words, in such a case, the control for aligning the re-gaming combination on the winning line is given priority over the special combination, and the re-gaming combination always wins. When the special role and the replaying role can be drawn in at the same time, only the replaying role is drawn in and the special role does not coincide with the replaying role on the winning line.

  In this embodiment, the reel stop control is performed by using the stop control table that can specify the number of sliding frames for each timing at which the stop operation is performed. A configuration in which the stop position is specified from the table and stop control for stopping the reel at the specified stop position is performed.The stop position that can be stopped at the timing of the stop operation is searched without using the stop control table or the stop position table. Specified and configured to perform stop control to stop the reel at the specified stop position, stop control using stop control table, stop control using stop position table, stop possible without using stop control table or stop position table A configuration in which stop control by searching and specifying a stop position is used together, and a configuration in which stop control is performed by partially changing the stop control table and stop position table It may be.

  In the present embodiment, the main control unit 41 counts the game time, which is the time that has elapsed since the start of the game, each time the reel rotation is started, that is, the time elapsed from the start of the reel rotation. After the end of one game, when a predetermined number of bets is set by inserting medals or the like and the game start operation is performed in a state where the game start operation is enabled, the reel rotation of the previous game is started. If the game time from which the timing was started is equal to or longer than the specified time (4.1 seconds in this embodiment), that is, if the specified time has elapsed since the start of reel rotation of the previous game, no wait is generated. At that time, the rotation of the reel for the game in the game is started. On the other hand, after the end of one game, when a predetermined number of bets is set by inserting medals or the like and the game start operation is performed in a state where the game start operation is enabled, the reel rotation of the previous game is started. If the game time that started counting from the point in time is less than the specified time, that is, if the specified time has not elapsed since the start of reel rotation in the previous game, a wait is generated and the reel rotation is started at that point. Instead, the game waits until the game time that has started timing from the start of reel rotation of the previous game reaches a specified time, and starts reel rotation when the specified time is reached.

  In the present embodiment, the main control unit 41 performs control to output an external output signal indicating a game state, an error occurrence state, and the like. These external output signals are output to a hall device such as a hall computer through an external output board 1000 and an information providing terminal board of a game shop (hall) in which the slot machine 1 is installed.

  The main control unit 41 provides a medal IN signal indicating the number of medals used for setting the number of bets, a medal OUT signal indicating the number of medals awarded to the player due to the occurrence of a prize, and a gaming state during RB (regular bonus). RB signal indicating that the game state is BB (Big Bonus), BB signal indicating that the gaming state is during RT2, RT signal indicating that RT2 is being performed, a door opening signal indicating that the front door 1b is being opened, which will be described later. A setting change signal indicating that the mode has shifted to the setting change mode, a throw-in error signal indicating an abnormality of the medal selector, and a pay-out error signal indicating an abnormality of the hopper unit 34 are output.

  The external output board 1000 is provided with a relay circuit, a parallel-serial conversion circuit, and a terminal for each output signal, and is provided with a connector to be electrically connected to a circuit of the information providing terminal board. Among the signals output from the game control board 40, the medal IN signal, the medal OUT signal, the RB signal, and the BB signal are output to the information providing terminal plate as pulse signals as they are via the relay circuit. On the other hand, the door opening signal, the setting change signal, the closing error signal, and the dispensing error signal are converted by a parallel-serial conversion circuit into security signals, which are serial signals that can be individually identified, and information is provided. Output to terminal board.

  Next, a command transmitted from the main control unit 41 to the sub control unit 91 will be described.

  In the present embodiment, the main control unit 41 instructs the sub-control unit 91 to insert the number of coins command, credit command, game status command, internal winning command, reel acceleration information command, stop operation command, sliding frame number command, stop A plurality of types of commands including a command, a game end command, a winning number command, a payout start command, a payout end command, a standby command, a stop command, an error command, a return command, a setting command, a setting confirmation command, and a door command are transmitted.

  The inserted number command is a command capable of specifying the inserted number of medals, that is, the number of medals used for setting the bet amount, and is a state from the end of the game (after changing the setting) to the start of the game. Or, when a medal is inserted in a state where the specified number of bets is not set, or when the MAXBET switch 6 is operated to set the number of bets, this is transmitted. Further, since the inserted number command is transmitted when the operation of setting the bet amount is performed, it is possible to specify that the operation of setting the bet amount has been performed by receiving the inserted number command. The credit command is a command capable of specifying the number of medals stored as credit, and is a state from the end of the game (after changing the setting) to the start of the game. In a state in which a specified number of bets is set, Sent when medals are inserted and credits are added.

  The game state command is a command that can specify the game state of the game, and is transmitted when the start switch 7 is operated to start the game. The internal winning command is a command that can specify an internal lottery result, is a time when the game is started by operating the start switch 7, and is transmitted after the transmission of the gaming state command. Since the game state command and the internal winning command are transmitted when the game is started by operating the start switch 7, it is possible to specify that the game is started by operating the start switch 7 by receiving these commands. It is.

  The reel acceleration information command is a command that can specify that the rotation of the reel starts with the progress of the game, and is transmitted when the rotation of the reel starts with the progress of the game. The stop operation command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and the area number of the stop operation position of the corresponding reel. It is transmitted each time the accompanying stop control is performed. The number of sliding frames command is a command capable of specifying whether the reel to be stopped is the left reel, the middle reel, or the right reel, or the number of sliding frames to be moved from when the corresponding reel is stopped to when it is stopped. Each time the stop control associated with the stop operation of each reel is performed, it is transmitted after the corresponding stop operation command is transmitted. The stop command is a command capable of specifying whether the reel to be stopped is the left reel, the middle reel, or the right reel, and the area number of the stop position of the corresponding reel, and the stop control accompanying the stop operation of each reel. Is transmitted after the corresponding slide frame number command is transmitted. The stop operation command, the number of sliding frames command, and the stop command can specify whether the reel to be stopped is a left reel, a middle reel, or a right reel, and is associated with the stop operation of each reel. Since the command is transmitted every time the stop control is performed, by receiving these commands, it is possible to specify that any one of the reels has been stopped and the reel to be stopped.

  The game end command is a command that can specify that the game has ended, and is transmitted when the player presses a stop switch to stop the third stop reel and releases the stop switch. The winning number command is a command capable of specifying the combination of symbols aligned on the winning line LN, the presence or absence of a winning, the type of winning, and the number of medals to be paid out at the time of winning, so that the player stops the third stop reel. This is when the stop switch is pressed down and the stop switch is released, and is transmitted after the transmission of the game end command. Since both the game end command and the winning number command are transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch, by receiving these commands, It is possible to specify that all the operations necessary to advance one game are completed.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals due to winning or the settlement of credits (including medals used for setting the number of bets) is started. The payout end command is a command for notifying the end of payout of medals, and is transmitted when payout of medals due to winning and credit settlement is completed.

  The standby command is a command indicating that a transition to a standby state is performed. After the end of one game, when the estimated end time (60 seconds in this embodiment) elapses without a bet amount being set and a transition is made to the standby state, a credit is issued. The payout of the medals due to the settlement of the medals (including the medals used for setting the number of bets) is completed, and is transmitted after the payout end command is transmitted.

  The stop command is a command indicating the occurrence or release of the stop state. After the BB ends, the stop command indicating the occurrence of the stop state is transmitted when the ending effect waiting time has elapsed, and the reset operation is performed. At the time when the stop state is released, a stop command indicating the release of the stop state is transmitted. The error command is a command that indicates the occurrence or release of an error state and the type of the error state.When an error is determined, and when the state is controlled to the error state, an error command that indicates the occurrence and the type of the error state is transmitted and reset. When the operation is performed and the error state is released, an error command indicating the release of the error state is transmitted.

  The return command is a command indicating that the main control unit 41 has returned to the control state before the power failure, and is transmitted when the main control unit 41 has returned to the control state before the power failure at the time of activation. The setting command is a command that indicates the start or end of the setting change state, the setting value after the setting change, a setting command indicating the start of the setting change state is transmitted at the time of transition to the setting change state, and when the setting change state ends, A setting command indicating the end of the setting change state and the setting value after the setting change is transmitted. In addition, since the control state of the main control unit 41 is initialized along with the transition to the setting change state, it is possible to specify that the control state of the main control unit 41 has been initialized by the setting command indicating the start of setting. . The setting confirmation command is a command that indicates the start or end of the setting confirmation state. A setting confirmation command that indicates the start of the setting confirmation is sent when moving to the setting confirmation state, and a setting that indicates the end of the setting confirmation when the setting confirmation state ends. A confirmation command is sent.

  The door command is a command indicating the detection state of the door open detection switch 25, that is, ON (open state) / OFF (closed state), and when a predetermined condition is satisfied (when the command queue is empty at the time of executing the normal command transmission processing). At some point).

  Among these commands, commands other than the door command are generated in the main processing, temporarily stored in a command queue provided in the RAM 41c, and thereafter, a normal-time command transmission processing of a timer interrupt processing (main) and a command transmission at the time of power failure. Sent in processing. On the other hand, the door command is generated when no command is stored in the command queue in the normal command transmission processing, temporarily stored in the command queue provided in the RAM 41c, and transmitted in the normal command transmission processing. You.

  Next, an effect control performed by the sub-control unit 91 based on a command transmitted from the main control unit 41 to the sub-control unit 91 will be described. When receiving a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt processing, the command acquired from the command transmission line is stored in a reception buffer provided in the RAM 91c.

  In the timer interrupt processing (sub), the sub control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. The control pattern table stored in the ROM 91b is referred to based on the command received in the step, and the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, the reel LED 55, and the like are controlled based on the control contents registered in the control pattern table. Controls the output of various effect devices. In the control pattern table, for each of a plurality of types of effect patterns, a display pattern of the liquid crystal display 51 corresponding to the type of command, a lighting mode of the effect LED 52, an output mode of the speakers 53 and 54, a lighting mode of the reel LED 55, and the like. The control patterns of these effect devices are registered, and upon receiving the command, the sub-control unit 91 sets the control pattern of the control pattern registered in the control pattern table corresponding to the effect pattern set in the RAM 91c in the game. The control device refers to the control pattern corresponding to the type of the received command, and controls the output of the effect device based on the control pattern. As a result, an effect according to the effect pattern and the progress of the game is executed.

  When a new command is received during the execution of the effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and returns to the newly received command. An effect based on the corresponding control pattern is executed. In other words, when a new command is received even in a state where the production has not been completed to the end, the production that was being executed is canceled and a new production is performed unless the received new command is not a command that triggers a new production. An effect based on the command will be executed.

  The effect pattern is selected at the selection rate according to the result of the internal lottery indicated by the internal winning command when the internal winning command is received, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b. When the internal control command is received, the sub-control unit 91 sets the effect in the effect table according to the result of the internal lottery indicated by the internal win command. With reference to the registered selection rate, one of a plurality of effect patterns is selected from the plurality of effect patterns in accordance with the selected rate, and the selected effect pattern is set as the effect pattern of the game in the RAM 91c. Also, even if the same command is received, different control patterns are selected depending on the effect pattern selected at the time of receiving the internal winning command, and as a result, different effects may be performed depending on the effect pattern.

  The sub control unit 91 determines whether the detection state of the door opening detection switch 25 has changed from OFF (closed state) to ON (open state) based on the detection state of the door opening detection switch 25 specified from the door command. It is determined whether or not the front door 1b is being opened, and if it has changed from OFF (closed state) to ON (opened state), door opening notification is performed to notify that the front door 1b is being opened.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described below with reference to FIGS.

  When the main control unit 41 is activated by the occurrence of a reset, the main control unit 41 performs a startup setting. In the setting at the time of starting, the status flag provided in the main control unit 41 is initialized. The status flag is data that holds the state of the operation result or execution result of the instruction, and particularly includes an interrupt master permission flag for setting the inhibition / permission of the interrupt. Since the initial value of the interrupt master permission flag is a value indicating that the interrupt is prohibited, the main control unit 41 starts up in a state where the interrupt is prohibited.

  Then, after setting various functions with reference to the HW parameters, the main control unit 41 performs an initial setting process shown in the flowchart of FIG. 6 according to the program stored in the program / data area. In the initial setting process, first, the value of the interrupt master permission flag is set to a value indicating the prohibition of the interrupt, thereby prohibiting the interrupt (Sa1). As described above, the main control unit 41 is activated in a state where the interrupt is prohibited, but in Sa1, the main control unit 41 prohibits the interrupt again. Next, initialization data is set (Sa2), and each output port including the parallel output port 513 is initialized (Sa3). Next, the internal register is set (Sa4).

  Next, it is determined whether or not the power supply voltage is normal (Sa5). If the power supply voltage is not normal, the determination is repeated until the power supply voltage becomes normal. If the power supply voltage is normal, the upper address of the interrupt vector is set (Sa6). Then, access to the RAM 41c is permitted (Sa7), and the stack pointer is initialized (Sa8).

  Next, the RAM parity is calculated (Sa9). Then, it is determined whether or not the calculated RAM parity becomes 0 (Sa10). If the RAM parity does not become 0, the process proceeds to step Sa13 to clear the destruction diagnosis data (Sa13). On the other hand, when the RAM parity becomes 0, destruction diagnosis data is acquired from the RAM 41c (Sa11), it is determined whether the acquired destruction diagnosis data is correct (Sa12), and the destruction diagnosis data is cleared. (Sa13).

  Next, it is determined whether or not the setting key switch 37 is ON (Sa14). When the setting key switch 37 is in the ON state, the timer interrupt is set (Sa19). Specifically, a register of a timer circuit 509 incorporated in the main control unit 41 is set so that a timer interrupt is periodically executed at predetermined time intervals. In this embodiment, a value corresponding to about 0.56 ms is set in a predetermined register (time constant register), so that a timer interrupt is periodically generated about every 0.56 ms. In addition, in the timer circuit 509, by setting the register, the timer is initialized, and the timer starts counting from the initial value. When the setting of the timer interrupt in the step of Sa19 is completed, the processing shifts to the setting change processing.

  On the other hand, when the setting key switch 37 is in the OFF state, it is determined whether or not the storage content of the RAM 41c is destroyed (Sa15). In step Sa15, it is determined whether or not a RAM abnormality flag to be described later is set and whether or not the storage content of the RAM 41c is destroyed based on the determinations in Sa10 and Sa12. If the content stored in the RAM 41c has not been destroyed, a return command is transmitted to the sub control unit 91 (Sa16). Note that the case where the storage content of the RAM 41c is not destroyed means that the RAM abnormality flag is not set, the RAM parity is determined to be 0 in the step Sa10, and the destruction diagnosis data is further determined in the step Sa12. This is the case where it is determined to be correct.

  After the step Sa16, all registers are restored (Sa17), and the same timer interrupt setting as the step Sa19 is performed (Sa18). Then, the processing shifts to Sd24 processing of timer interrupt processing (main) described later. As a result, the process returns to the process executed before the power interruption.

  If the contents stored in the RAM 41c are destroyed in the step Sa15, the start address (0000h) of the RAM is set in the register (Sa20), and the address from the specified address to the final address (0FFFh) of the usable area is set. The area, that is, all the usable areas are initialized (Sa21).

  Next, a RAM abnormality flag indicating that the storage content of the RAM 41c is not normal is set in the RAM 41c (Sa22), and the process proceeds to error processing. In the error processing, the progress of the game is disabled. Further, in the error state in which the RAM abnormality flag is set and the state is shifted, the setting key switch 37 is turned on and the power switch 39 is turned on, so that the state can be canceled by shifting to the setting change processing. On the other hand, when the power switch 39 is turned on without setting the setting key switch 37 to the ON state, the RAM abnormality flag is still set and the error state is returned.

  Next, a setting change process executed by the main control unit 41 will be described.

  As shown in FIG. 7, the main control unit 41 first sets a start address (0000h) of the RAM in a register (Sb1). Next, it is determined whether or not the storage contents of the RAM 41c are destroyed, similarly to the step of Sa15 shown in FIG. 6 (Sb2). If the contents of the RAM have not been destroyed, that is, if the contents of the RAM are not abnormal, the start address of the initialization target RAM at the start of the setting change is set in the register (Sb3). That is, the address set in Sb1 is changed. If the contents of the RAM are destroyed, that is, if the contents of the RAM are abnormal, the process proceeds to step Sb4.

  Next, the area from the address specified in step Sb1 or Sb3 to the last address of the usable area is initialized (Sb4). In the step Sb1, the start address of the RAM is set. In this case, in the step Sb4, all the available areas are initialized. On the other hand, in step Sb3, the start address of the initialization target RAM at the time of starting the setting change is set. In this case, in step Sb4, the area other than the important work and the special work in the usable area is initialized. Will be done.

  Next, a setting command indicating the start of the setting change state is transmitted to the sub control unit 91 (Sb5), and the interruption is permitted (Sb6).

  Next, it is determined whether the reset / setting switch 38 has changed from OFF to ON (Sb7). When the reset / setting switch 38 changes from OFF to ON, the set value of the register is updated (1 is added for 1 to 5, and 1 is updated for 6) (Sb8). If the reset / setting switch 38 has not changed, it is determined whether the start switch 7 has changed from OFF to ON (Sb9). If the start switch 7 has not changed, the process returns to step Sb7. On the other hand, when the start switch 7 changes from OFF to ON, it is determined whether the setting key switch 37 is in the OFF state (Sb10). If the setting key switch 37 is not turned off, the determination is repeated until the setting key switch 37 is turned off. When the setting key switch 37 is OFF, the data of the set value set in the register is stored in the RAM 41c (Sb11).

  Next, a setting command indicating the end of the setting change state is transmitted to the sub control unit 91 (Sb12). Then, the start address of the initialization target RAM at the end of the setting change is set in the register (Sb13), and the process proceeds to the main processing.

  Next, a main process executed by the main control unit 41 will be described. The main processing is repeatedly executed for each game of one unit. One cycle of the main processing corresponds to one unit of the game.

  As shown in FIG. 8, the main control unit 41 first prohibits an interrupt (Sc1). Next, the last address of the initialization target RAM is set (Sc2).

  Next, the RAM area indicated by the specified address is cleared (Sc3). At this time, if the main processing is started after the setting change processing, the start address of the initialization target RAM at the time of the end of the setting change is set. In the step Sc2, the final address of the initialization target RAM at the time of the end of the setting change ( Since 0FFFh) is set, an area other than the important work and the special work in the usable area is initialized. At the end of the game, not at the end of the specific game state, the start address of the RAM to be initialized at the end of the game is set in the step of Sc10 described later, and in the step of Sc2, the address indicated by the stack pointer as the last address is set. Is set, the general work, the unused area, and the unused stack area in the usable area are initialized. At the end of the specific game state, and at the end of the game, the start address of the initialization target RAM at the end of the specific game state is set in the step of Sc11 described later, and the last address is set in the step of Sc2. As the address indicated by the stack pointer is set, the unused area and the unused stack area of the usable area are initialized.

  After the initialization of the RAM in the step of Sc3, an interruption is permitted (Sc4), and a game start waiting process is executed (Sc5). In the game start waiting process, the process waits in a state where the number of bets can be set, sets a specified number of bets according to the game state, and starts the game when the start switch 7 is operated.

  Next, an internal lottery process is executed (Sc6). In the internal lottery process, it is determined whether the winning of each of the above combinations is permitted based on the random number value for the internal lottery latched at the same time as the start of the game by the detection of the start switch 7 in the step Sc5 (that is, the display result is derived). A process is performed to determine whether to allow or not.

  Next, a reel control process is executed (Sc7). In the reel control process, the process of rotating the reels 2L, 2C, 2R in response to the operation of the start switch 7, the result of the internal lottery in the step Sd2, and the operation of the stop switches 8L, 8C, 8R by the player are detected. In response to this, a process of stopping the rotation of the corresponding reels 2L, 2C, 2R is executed.

  Next, a game end time setting process is executed (Sc8). In the game end setting process, when it is determined in the process of Sc7 that the rotation of all the reels 2L, 2C, 2R has stopped, a prize is generated according to the display result derived on each of the reels 2L, 2C, 2R. A process is performed to determine whether or not it is. Then, when it is determined that a winning has occurred, processing such as adding credits and paying out medals is performed based on the number of payouts according to the winning. If a prize has been won, a process of setting a game state in preparation for the next game is executed after the payout of medals or the like is completed. If no winning has occurred, after the reels have stopped, a process of setting a gaming state in preparation for the next game is executed.

  When the game end time setting process ends, it is determined whether or not a specific game state has ended (Sc9). If the specific game state has not ended, the start address of the initialization target RAM at the time of game end is determined. Set (Sc10) and return to the step of Sc1. If it is the end of the specific game state, the start address of the initialization target RAM at the end of the specific game state is set (Sc11), and the process returns to the step of Sc1.

  In the main process, a command storing process of generating a command in accordance with the progress of the game and setting the command in a command queue is executed, and the set command is executed in a normal timer interrupt process (main). The command is transmitted to the sub-control unit 91 by the command transmission process.

  FIGS. 9 and 10 are flowcharts showing the control contents of the timer interrupt processing (main) executed by the main control unit 41 interrupting the basic processing (mainly the main processing) at a constant interval (interval of about 0.56 ms). is there. The timer interrupt process (main) is a process executed by an interrupt generated according to the count of the timer circuit 509, and the address where the program of the timer interrupt process (main) is stored is a vector table. Is set as a value corresponding to the timer interrupt. Then, when a timer interrupt occurs, the processing from that address is executed. Further, other interrupts are automatically prohibited during the execution of the timer interrupt processing (main).

  As shown in FIG. 9, in the timer interrupt processing (main), first, a register in use is saved in a stack area (Sd1).

  Next, a power failure determination process is performed (Sd2). In the power failure determination process, it is determined whether or not a voltage drop signal has been input from the power interruption detection circuit 48. If the voltage drop signal has been input, it is determined whether or not the voltage drop signal has been input in the previous power failure determination process. If a voltage drop signal is also input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that fact is set.

  After the power failure determination process in step Sd2, it is determined whether or not the power failure flag is set (Sd3). If the power failure flag is not set, the process proceeds to Sd4, and the detection data of various switches is input from the input port. Performs port input processing for inputting. On the other hand, when the power interruption flag is set, the power interruption processing (main) is performed after executing a power interruption command transmission process of transmitting various commands set in the command queue to the sub-control unit 91. .

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt processing (main) from the four types of timer interrupts 1 to 4 is advanced by 1 (Sd5). In step Sd5, 1 is added when the branch counter value is 0 to 2 and updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Every time the timer interrupt processing (main) is executed.

  Next, it is determined with reference to the branch counter value whether it is 2 or 3, that is, whether it is timer interrupt 3 or timer interrupt 4 (Sd6), and if it is not timer interrupt 3 or timer interrupt 4, that is, if it is not timer interrupt 4, In the case of 1 or timer interrupt 2, a motor phase signal output process for outputting phase signal data of the reel motors 32C, 32C, 32R is executed (Sd7).

  Next, it is determined whether or not it is 1 by referring to the branch counter value, that is, whether or not it is the timer interrupt 2 (Sd8). If it is not the timer interrupt 2, that is, if it is the timer interrupt 1, the reel motor Reel start processing (Sd9) for controlling the step time interval at the start of 32L, 32C, 32R, motor step processing (Sd10) for changing the phase signal data of reel motors 32L, 32C, 32R, reel motors 32L, 32C , 32R are stopped, and after a lapse of a predetermined time, motor phase signal standby processing (Sd11) for changing the phase signal to one-phase excitation is sequentially performed, and then the process proceeds to step Sd24.

  If it is determined in step Sd8 that the interrupt is the timer interrupt 2, an LED dynamic display process (Sd12) for dynamically lighting various indicators and a control for outputting data such as lighting signals of various LEDs to the output port are performed. Signal output processing (Sd13), time counter update processing for updating various time counters (Sd14), monitoring of the detection state of the door open detection switch 25, door monitoring processing for performing a door command transmission request (Sd15), command queue After executing the normal command transmission process (Sd16) for transmitting the various commands set to the sub-control unit 91 and the external output signal update process (Sd17) for updating the external output signal, the process proceeds to step Sd24.

  If it is determined in step Sd6 that the interrupt is timer interrupt 3 or timer interrupt 4, it is further determined whether the branch counter value is 3, that is, timer interrupt 4 (Sd18). If it is not the timer interrupt 4, that is, if it is the timer interrupt 3, the origin passing process (Sd19) for checking the passing of the origin of the rotating reels 2L, 2C, and 2R (passing of the reel reference position) (Sd19), After sequentially executing a switch input determination process (Sd20) for determining whether or not the detection state has changed, the process proceeds to step Sd24.

  If it is determined in step Sd18 that the interrupt is the timer interrupt 4, a stop switch process (Sd21) for determining a stop position in response to the detection of the stop switches 8L, 8C, and 8R. A stop process (Sd22) for starting the braking by excitation, a final stop process (Sd23) for three-phase excitation after a predetermined time from the start of the brake in the stop process, and then the process proceeds to step Sd24.

  In step Sd24, the register saved in the stack area in Sd1 is restored, and the process returns to the process before the interrupt.

  As described above, in the present embodiment, when a reset occurs, the main control unit 41 starts up in an interrupt-prohibited state, and thereafter, at the start of the initial setting process to be executed first, the program is used to execute the interrupt. The prohibition is performed, and even if the main control unit 41 is activated in a state where the interrupt is not prohibited for some reason, it is possible to prevent the occurrence of an unintended interrupt.

  Further, the main control unit 41 allows the interrupt after setting the timer interrupt in the timer circuit 509 after the activation, and the interrupt occurs when the timer interrupt does not operate normally. Can be prevented. In addition, the timer circuit 509 sets a timer interrupt so that the timer is initialized and starts counting time from an initial value. Second, the timer interrupt can be generated at fixed time intervals without deviation from the time until the second and subsequent interrupts occur. In addition, the main control unit 41 updates the setting of the timer circuit 509 to an initial value by a program in the initial setting process, and when the setting of the timer circuit 509 is rewritten for some reason at startup. Even if there is, unintended interruption can be prevented from occurring.

  If the setting key switch 37 is ON at the time of activation, the main control unit 41 shifts to the setting change process, and initializes the RAM 41c at the start of the setting change process. At this time, if the data in the RAM 41c is normal, the important work and the special work are retained and the other areas are initialized, so that the control state (setting value, game state, etc.) before the change even after the setting is changed. If the data in the RAM 41c is not normal while a part of the data can be retained, the entire area of the usable area including the important work and the special work is initialized, so that the abnormality in the data in the RAM 41c is ensured. Can be eliminated.

  Further, the main control unit 41 sets the RAM abnormality flag when the RAM abnormality is determined. Therefore, when the power is turned off after the occurrence of the RAM abnormality error and the power is turned on again, the RAM parity is set to 0. That is, even when the destruction diagnosis data is determined to be normal, it is possible to determine whether or not the data in the RAM 41c is destroyed based on the RAM abnormality flag.

  Further, after the end of the setting change process, the main control unit 41 executes a main process of performing a process stepwise according to the progress of the game for each game unit. In the main process, the RAM 41c is initialized for each game unit, and the RAM 41c is also initialized at the end of the setting change process. Then, after the setting change processing is completed, the main processing is started from the stage before the processing of initializing the RAM 41c in the main processing, and the initialization of the RAM 41c after the completion of the setting change processing and the game unit The initialization of each RAM 41c can be performed by a common process.

  Further, when performing initialization of the RAM 41c, the main control unit 41 is configured to prohibit an interrupt until the initialization is completed, and the timer interrupt processing (main) is performed during execution of the initialization of the RAM 41c. This can prevent the initialized contents from being changed, and prevent the processing performed in the timer interrupt processing (main) from being performed normally.

  Further, the main control unit 41 updates the output state of the external output signal in the main processing, and changes the output state of the external output signal in the subsequent timer interrupt processing (main) based on the updated output state. In addition, when updating the output state of the external output signal, interrupts are prohibited until the update is completed, and the timer interrupt processing (main) occurs before the output state of the external output signal is completed. By doing so, it is possible to prevent an external output signal indicating unintended data from being output.

  The main control unit 41 of the present embodiment generates a command in accordance with the progress of the game in the setting change process and the main process described above, stores the generated command in a command queue, and performs a normal operation in the timer interrupt process (main). Each time a command transmission process is executed, an untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

  FIG. 11 is a flowchart showing the control contents of the command storage processing executed when the various commands generated by the main control unit 41 are stored in the command queue. The command transmitted by the main control unit 41 is composed of 2 bytes, the first byte represents MODE (classification of command), and the second byte represents EXT (contents of command). Further, the form of the command shown in this embodiment is an example, and another data form may be used. Further, in the present embodiment, the commands are composed of 2-byte signals, but these commands may be composed of 1-byte signals or signals of 3 bytes or more.

  In the command storing process, first, MODE and EXT constituting a command to be transmitted are generated (Se1). After the MODE and EXT of the generated command are stored in the area of the area number indicated by the storage pointer, that is, in the free area of the command queue (Se2), 1 is added to the area number indicated by the storage pointer (Se3). Since the area number is a numerical value in the range of 0 to 31, when the serial number indicated by the storage pointer is 31, 1 is added, and when it becomes 32, it is updated to 0.

  Next, it is confirmed whether or not the unsent flag is set (Se4). If the unsent flag is not set, the unsent flag is set (Se5). Then, it is checked whether or not the area number indicated by the storage pointer matches the area number indicated by the transmission pointer, that is, whether or not all areas of the command queue are full with untransmitted commands. If not, wait until the unsent command stored in the command queue is transmitted and the area number indicated by the storage pointer does not match the area number indicated by the transmission pointer, and the area number indicated by the storage pointer When the command no longer matches the area number indicated by the transmission pointer, that is, when a command queue becomes available, the command storing process is terminated (Se6).

  FIG. 12 shows a control of a normal command transmission process executed in the timer interrupt 2 of the above-described timer interrupt process (main) so that the main control unit 41 transmits the command stored in the command queue by the command storage process. It is a flowchart which shows the content.

  In the normal command transmission processing, first, it is checked whether or not the untransmitted flag is set, that is, whether or not an untransmitted command is stored in the command queue (Sf1), and the untransmitted flag is not set. In this case, the detection state of the door opening detection switch 25 is acquired, MODE and EXT constituting the door command are generated, and the generated MODE and EXT are stored in the area of the area number indicated by the storage pointer, that is, in the empty area of the command queue. It is stored (Sf2, Sf3).

  When it is determined in step Sf1 that the untransmitted flag is set, and after MODE and EXT constituting the door command are stored in the command queue in steps Sf2 and Sf3, the area indicated by the transmission pointer value in the command queue Is transmitted to the sub-control unit 91 (Sf4 to Sf7). Specifically, first, a MODE constituting the command stored in the area indicated by the transmission pointer value of the command queue is output (Sf4), and a strobe signal for notifying the sub-control unit 91 that the command has been output is output for a predetermined time. (10 μs in this embodiment) is output (Sf5). Then, the EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sf6), and the strobe signal is output again for a predetermined time (Sf7).

  Next, 1 is added to the area number indicated by the transmission pointer (Sf8). Since the area number is a numerical value in the range of 0 to 31, when the area number indicated by the transmission pointer is 31, 1 is added, and when it becomes 32, it is updated to 0. Thereafter, it is checked whether the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, whether a command to be transmitted is stored in the command queue (Sf9). That is, if the command to be transmitted is not stored in the command queue, the untransmitted flag is cleared, and the normal command transmission process ends (Sf10). On the other hand, when the area number indicated by the transmission pointer does not match the serial number indicated by the storage pointer, that is, when a command to be transmitted is stored in the command queue, the non-transmission flag is maintained and the normal command transmission is performed. The process ends. By maintaining the untransmitted flag, the untransmitted command left in the command queue is transmitted in the next and subsequent timer interrupt processing (main).

  The main control unit 41 of the present embodiment executes the power interruption command transmission processing before executing the power interruption processing (main) when the power interruption flag is set in the above-described timer interruption processing, The non-transmitted command stored in the command queue is transmitted to the sub-control unit 91 other than the normal command transmission process.

  FIG. 13 is a flowchart showing the control contents of the power interruption command transmission processing executed before the main control unit 41 performs the power interruption processing (main) in the timer interruption processing (main).

  In the command transmission process at the time of power interruption, first, it is checked whether or not an unsent flag is set, that is, whether or not an unsent command is stored in a command queue (Sg1), and the unsent flag is set. If it is, all the commands stored in the command queue are transmitted to the sub-control unit 91 (Sg1 to Sg7).

  More specifically, first, a MODE constituting the command stored in the area indicated by the transmission pointer value of the command queue is output (Sg2), and a strobe signal for notifying the sub-control unit 91 that the command has been output is output for a predetermined time. (Sg3) is output (10 μs in this embodiment). Then, the EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sg4), and the strobe signal is output again for a predetermined time (Sg5). Thereafter, 1 is added to the area number indicated by the transmission pointer (Sg6). As in the case of adding the transmission pointer in the normal command transmission process, the area number is a numerical value in the range of 0 to 31. Therefore, when the area number indicated by the transmission pointer is 31 and 1 is added to 32, Update to 0.

  Next, it is determined whether or not the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, whether the command to be transmitted is stored in the command queue (Sg7), and the area indicated by the transmission pointer is determined. If the number does not match the serial number indicated by the storage pointer, that is, if the command to be transmitted is stored in the command queue, the area number indicated by the transmission pointer and the serial number indicated by the storage pointer are determined in step Sg7. Until it is determined that they match, the steps of Sg2 to Sg7 are repeatedly executed, and all commands stored in the command queue are transmitted to the sub control unit 91.

  In step Sg7, when it is determined that the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, all commands stored in the command queue are transmitted to the sub control unit 91. If no command remains in the command queue, the main control unit 41 clears the non-transmission flag (Sg8), terminates the power-off command transmission process, and shifts to the power-off process (main).

  As described above, in the normal command transmission processing, one command (a set of two bytes) is transmitted to the sub control unit 91 each time the normal command transmission processing is executed in the timer interrupt processing (main). On the other hand, in the power-off command transmission process, all commands stored in the command queue are transmitted to the sub-control unit 91 before the power-off process (main) is performed in the timer interrupt process. To send.

  FIG. 14 shows the power interruption processing (main) executed after the power interruption command transmission processing when the main control unit 41 determines that the power interruption flag is set in the timer interruption processing (main) described above. It is a flowchart which shows the control content.

  In the power interruption processing (main), first, all registers that may be used are saved in the stack area (Sg1). The values of the I register and the IY register are used, but are not stored here because the same fixed value is always set at the time of initialization at the time of startup.

  Next, destruction diagnosis data (5A (H) in this embodiment) is set (Sg2). Then, all output ports including the parallel output port 513 for outputting a command are initialized (Sg3). Thus, the output state of the output port corresponding to the command output last by the command transmission processing at the time of power failure is initialized. Next, RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including the unused area and the unused stack area) of the RAM 41c becomes 0 (Sg4), and access to the RAM 41c is performed. Prohibition (Sg5). Thereafter, the voltage decreases, the CPU 41a of the main control unit 41 stops, and the state shifts to a standby state. When the voltage drops in the standby state, the operation of the main control unit 41 is internally stopped, and the operation is reliably stopped when the power is cut off.

  In this embodiment, as shown in FIG. 15, the reset circuit 49 of the game control board 40 controls the monitor voltage (DC + 24V) higher than the drive voltage (DC + 5V) of the main control unit 41 among the power supply voltages supplied from the power supply board 101. ) Is monitored, and when the monitored voltage exceeds an operable voltage (main) (+3.5 V) at which the main control unit 41 becomes operable, a reset signal is turned ON to instruct the main control unit 41 After that, when a sufficient time (sufficient time for the monitor voltage to rise to +24 V) elapses to stabilize the drive voltage (DC + 5 V) of the main control unit 41, the reset signal is turned OFF and the main signal is turned off. The control unit 41 is activated. On the other hand, when the reset signal is turned off by the reset circuit 49 when the power is turned on, that is, the sub-control unit 91 is activated at a timing earlier than the timing at which the main control unit 41 is activated. When the power is turned on, the sub-control unit 91 is started earlier than the main control unit 41 when the power is turned on, and the return command or the setting command (start command) transmitted from the main control unit 41 is turned off. ) Is put on standby in a state where the sub-control unit 91 can receive.

  The main control unit 41 executes the above-described initial setting process when the reset signal output from the reset circuit 49 is turned off and starts up. After transmitting the return command at the end of the process, the timer interrupt is permitted, and thereafter, the timer interrupt process is executed at regular intervals. When the setting key switch 37 is turned on when the reset signal is turned off and started, the RAM 41c is initialized, and the setting change state is started without returning to the state before the power failure. At the end of the initial setting process, before the timer interrupt is permitted, a setting command (start) is transmitted to the sub-control unit 91 in place of the return command, and then the timer interrupt is permitted. Execute interrupt processing at regular intervals. On the other hand, the sub-control unit 91 is activated before the main control unit 41 is activated, executes the initial setting process and completes the process, and waits until a return command or a setting command (start) is received in a state where the command can be received. I do.

  Next, after transmitting the return command or the setting command, the main control unit 41 executes the timer interrupt processing (main) at regular intervals, and executes the normal command transmission processing in the timer interrupt processing (main). If the command to be transmitted is not stored in the command queue, a door command is generated and transmitted based on the detection state of the door open detection switch 25. On the other hand, upon receiving the return command or the setting command (start), the sub control unit 91 starts the output control of the effect device.

  Further, the main control unit 41 transmits a door command or the like by a normal command transmission process executed in the timer interruption process (main), and after the main control unit 41 is started, the timer interruption is performed until the end of the initial setting process. After the main control unit 41 is started, a return command or a setting command (start) is transmitted, and then transmission of a command such as a door command transmitted by the normal command transmission process is permitted. It will be.

  Further, as shown in FIG. 15, the main control unit 41 executes a power failure determination process in a timer interrupt process (main) and determines whether a voltage drop signal has been input from the power interruption detection circuit 48 or not. Identify the occurrence of power interruption. The power interruption detection circuit 48 monitors the above-described monitoring voltage (DC + 24V) higher than the driving voltage (DC + 5V) of the main control unit 41, and detects a voltage drop where the monitoring voltage is higher than the driving voltage (DC + 5V) of the main control unit 41. When the voltage becomes lower than the voltage (main) (+20 V), a voltage drop signal is output. Therefore, the main control unit 41 specifies the occurrence of power interruption when the monitoring voltage becomes lower than the voltage drop detection voltage (main). . When the occurrence of a power failure is identified in the power failure determination process, the main control unit 41 executes a command transmission process at the time of a power failure, and sends all commands stored in the command queue to the sub control unit 91. After that, the power interruption processing (main) is executed.

  Further, the reset circuit 49 has a monitor voltage lower than the voltage drop detection voltage (main) (+20 V) and lower than or equal to the operation limit voltage (main) (+8 V) higher than the operable voltage (main) (+3.5 V). As a result, the reset signal is turned on, and the main control unit 41 is made inoperable. After the operation limit voltage (main) becomes equal to or lower than the voltage drop detection voltage (main) at which the power failure detection circuit 48 detects the occurrence of the power failure, the time required for the operation limit voltage to drop to the operation limit voltage (main) is equal to the voltage drop After the voltage becomes equal to or lower than the detection voltage (main), the main control unit 41 specifies the occurrence of the power failure, executes the command transmission processing at the time of power failure, and secures the time required for executing the power failure processing. Is set to

  The time required for the main control unit 41 to specify the occurrence of power interruption after executing the voltage drop detection voltage (main) or less, to execute the power interruption command transmission processing, and to execute the power interruption processing is as follows. The maximum time until the main control unit 41 detects a power failure (0.56 ms because occurrence of a power failure is specified for each timer interrupt process (main)) is stored in the command queue in the command transmission process at the time of power failure. The time required to transmit the maximum number (32) of commands that can be stored (40 μs per command transmission (MODE transmission 10 μs, transmission interval 10 μs, EXT transmission 10 μs, transmission interval 10 μs)) is 40 for the maximum number of transmissions. × 32 = 1280 μs) and the time required for the power interruption processing (main).

  On the other hand, the power interruption detection circuit 98 monitors the above-mentioned monitoring voltage (DC + 24 V) higher than the driving voltage (DC + 5 V) of the sub-control unit 91, and the monitoring voltage is lower than the operation limit voltage (main) (+8 V). The sub-control unit 91 outputs a voltage drop signal when the voltage drops below the voltage drop detection voltage (sub) (+6 V) higher than the drive voltage (DC + 5 V) of the sub-control unit 91. The occurrence of the power interruption is specified by the following. Then, when the occurrence of a power failure is identified in the power failure determination process, the sub-control unit 91 executes the power failure process (sub).

  Further, the reset circuit 95 has a monitoring voltage lower than the voltage drop detection voltage (sub) (+6 V) and lower than or equal to the operation limit voltage (sub) (+4 V) higher than the operable voltage (sub) (+3.5 V). As a result, the reset signal is turned ON, and the sub-control unit 91 is made inoperable. After the operation limit voltage (sub) becomes equal to or lower than the voltage drop detection voltage (sub) at which the power interruption detection circuit 98 detects the occurrence of the power interruption, the time required for the operation limit voltage (sub) to drop to the operation limit voltage (sub) is equal to the voltage drop. The sub-control unit 91 specifies the occurrence of a power interruption after the voltage becomes equal to or lower than the detection voltage (sub), and is set such that a time required for executing the power interruption processing is secured.

  Further, the sub-control unit 91 determines that the monitoring voltage is the operation limit voltage (main), that is, the main control unit 41 becomes inoperable after the power-off command transmission process and the power-off process (main) by the main control unit 41 are completed. When the voltage drops below the voltage drop detection voltage (sub) lower than the voltage, the voltage drop signal output specifies the occurrence of power interruption and executes power interruption processing (sub). At least the main control unit 41 Since the command receivable state is maintained until the power interruption command transmission processing is completed, the power interruption processing should be performed in a state where the main control unit 41 has received all the commands transmitted by the power interruption command transmission processing. Can be done. Note that even if the timing at which the sub-control unit 91 specifies the occurrence of power interruption is the timing before the main control unit 41 becomes inoperable, the command transmitted by the main control If the configuration is such that the command receivable state is maintained until a timing sufficient to receive all the commands, the power cutoff process is executed in a state where the main control unit 41 has received all the commands transmitted by the command transmission process at the time of power loss. can do.

  As described above, the main control unit 41 of the present embodiment generates a command in accordance with the progress of the game in the main processing and the like, stores the generated command in the command queue, and executes the normal time command in the timer interrupt processing (main). Each time the transmission process is executed, the unsent command stored in the command queue is transmitted to the sub-control unit 91.

  In such a configuration, in a state where a plurality of commands are stored in the command queue, power supply to the slot machine 1 may be stopped and a power failure may occur. The plurality of commands are in a non-transmitted state on the side of the unit 41, the untransmitted commands are kept as they are even after the power failure, and the commands held before the power failure after the power failure recovery are sent to the sub-control unit 91. When the transmission is performed, the control state of the main control unit 41 at the time of the power interruption and the restoration of the power interruption is different from the control state of the main control unit 41 specified by the sub-control unit 91.

  On the other hand, in the present embodiment, when the power failure is detected, the main control unit 41 stores the power in the command queue before executing the power failure process (main) for enabling the control state to be returned to the state before the power failure. Since the power-off command transmission process is executed to transmit all the commands to the sub-control unit 91, the control state of the main control unit 41 at the time of power-off and after the power-off is restored. The control state specified by the main control unit 41 can be matched as much as possible.

  The main controller 41 sets the command queue to the maximum number of commands that can be stored in the command queue (up to 32 commands in the present embodiment) during the period from the time when the power supply is stopped to the time when the control becomes uncontrollable. Is transmitted to the sub-control unit 91 and is longer than the period required for completing the power interruption processing (main). Therefore, after the power interruption is detected, all the commands stored in the command queue are transmitted. The processing up to the power interruption processing (main) can be reliably executed.

  In this embodiment, the main control unit 41 as the first control unit for controlling the game transmits a command as control information to the sub-control unit 91 as the second control unit for controlling the effect. However, the first control unit may be a control unit that performs a control other than the game control, for example, a control of an effect. The second control means may be any control means that performs some control based on the control information transmitted from the first control means. For example, the second control means may be a control means that controls the effect. In some cases, the control means for controlling the effect device based on the control information transmitted from the first control means may be used as the second control means.

  Further, in the present embodiment, as the power interruption processing (main) executed by the main control unit 41 (first control means), the RAM parity (exclusive OR) of the backup area is adjusted so that the RAM parity (exclusive OR) becomes zero. By performing a process of setting data and setting destructive diagnosis data (data other than 0), the RAM parity is 0 when power is restored, and the data in the backup area is determined by matching the destructive diagnostic data. Can be determined to be normal. However, if the power supply to the slot machine 1 is stopped and a power failure occurs, the power failure processing is to enable the control to return to the control state before the power failure. For example, a configuration may be adopted in which the checksum of the backup area is set and the data in the backup area can be determined to be normal by matching the checksum calculated at the time of power recovery.

  Further, in the present embodiment, the reset circuit 49 of the game control board 40 generates a reset signal before the monitor voltage drops below the operable voltage (main) at which the main control unit 41 becomes inoperable when the power interruption occurs, and the main control unit 41 becomes inoperable. Is supplied to the main control unit 41, and the main control unit 41 stops all operations by supplying a reset signal, that is, the main control unit 41 is in an uncontrollable state. The period from when the reset signal is supplied to when the control becomes uncontrollable is required to transmit the maximum number of commands that can be stored in the command queue to the sub-control unit 91 and to complete the power interruption processing (main). Although the configuration is longer than the period, in a configuration in which the reset signal is not supplied to the main control unit 41 at the time of power failure, the monitoring voltage is lower than the operable voltage (main) of the main control unit 41. A configuration in which the period until control becomes impossible becomes longer than the period required for transmitting the maximum number of commands that can be stored in the command queue to the sub-control unit 91 and completing the power interruption processing (main). Even after the power failure is detected, the processing from transmission of all commands stored in the command queue to power failure processing (main) can be reliably executed.

  Further, in this embodiment, the operation limit voltage (main) for stopping the operation of the main control unit 41 when the power failure occurs is set to be equal to or lower than the voltage drop detection voltage (main) at which the power failure detection circuit 48 detects the occurrence of the power failure. Then, after the time until the voltage drops to the operation limit voltage (main) becomes equal to or lower than the voltage drop detection voltage (main), the main control unit 41 specifies the occurrence of power interruption and executes the command transmission process at power interruption. By setting so as to secure the time required to execute the power-off process and to execute the power-off process, the period from the occurrence of the power-off until the main control unit 41 becomes inoperable is stored in the command queue. The maximum number of possible commands is transmitted to the sub-control unit 91, and the period is longer than the period required for completing the power interruption processing (main). Capacitors reduce drive voltage The period until the main control unit 41 becomes inoperable after the occurrence of power interruption by delaying with a battery, a capacitor, or the like, transmits the maximum number of commands that can be stored in the command queue to the sub control unit 91, and The period until the power interruption processing (main) is completed may be longer than the period required for the main control unit 41 to become inoperable. And the maximum number that can be stored in the command queue may be set so as to be longer than the period required for the power interruption processing (main) to be completed. After a power failure occurs, it is possible to reliably execute processing from transmission of all commands stored in the command queue to power failure processing (main).

  Further, the main control unit 41 of the present embodiment executes a command transmission process at the time of power failure when power failure is detected, and after transmitting all the commands stored in the command queue to the sub-control unit 91, The power interruption process (main) is executed, and each output port of the parallel output port 513 including the output port for outputting a command in the power interruption process (main) is initialized. The command can be prevented from being transmitted.

  In addition, the main control unit 41 of the present embodiment executes the normal command transmission process in the timer interrupt process (main), so that a predetermined number of commands stored in the storage area stored in the command queue are transmitted. Since (one in this embodiment) a command is transmitted to the sub-control unit 91 every predetermined trigger (once every four timer interrupt processing (main)), a predetermined number (one in this embodiment) 1) Even if more than one command is stored in the command queue, the number of commands transmitted in one timer interrupt process (main) is limited to a predetermined number. Can prevent the other control by the main control unit 41 from being delayed.

  Further, at a predetermined timing (when performing the normal command transmission process executed in the timer interrupt process (main)), the main control unit 41 of the present embodiment stores a command (internal winning command) according to the progress of the game in the command queue. , A stop operation command, etc.) is not stored, a door command indicating the detection state of the door open detection switch 25 is transmitted to the sub-control unit 91, so that the open / close state of the front door 1b is determined by the sub-control unit. 91 becomes identifiable, and the door command is transmitted when a command corresponding to the progress of the game is not stored in the command queue at a predetermined opportunity. Delayed by transmission or other control by the main control unit 41 by transmission of the door command (for example, each control in the main processing) ) It is possible to prevent the delay.

  Further, after the main control unit 41 is started, after transmitting a return command or a setting command (start), transmission of a command such as a door command transmitted by the normal command transmission process is permitted. After the power is turned on, the door command is not transmitted until a return command is transmitted after returning to the state before the power failure or a setting command (start) is transmitted without returning to the state before the power failure. Therefore, after determining whether or not to return the main control unit 41, the state of the main control unit 41 can be specified by the sub control unit 91, and the main control unit 41 returns to the control state before the power interruption. When the sub-control unit 91 receives the command in a state where it is not determined whether or not to return, it is possible to prevent an unintended operation from being performed.

  In the present embodiment, when no command is stored in the command queue in the normal command transmission processing, a door command indicating the detection state of the door open detection switch 25 is generated and transmitted. If no command is stored in the command queue in the normal command transmission process, the operation switches (MAXBET switch 6, start switch 7, stop switch 8L, 8C, 8R) are controlled based on the output of the switch detection circuit 44. A control state of the main control unit 41 can be specified, such as a command indicating a detection state (on / off), a command indicating presence / absence of error detection, a command indicating a type of the detected error, and a command capable of specifying a game state of the game. A command may be generated and transmitted to the sub-control unit 91. Even with such a configuration, the sub-control unit 91 can specify the control state of the main control unit 41 side, and the transmission of the command according to the progress of the game is the command of the command that can specify the control state of the main control unit 41. It is possible to prevent delay due to transmission and delay of other control by the main control unit 41 due to transmission of a command capable of specifying the control state of the main control unit 41.

  Next, a timer counter for measuring a time interval used by the main control unit 41 for controlling the progress of a game or the like will be described with reference to FIGS.

  The main control unit 41 sets an initial value according to the measured time as the timer value of the timer counter allocated to the RAM 41c when the time measurement start condition is satisfied, and periodically sets the timer value in the timer interrupt processing (main). The value is subtracted, and when the timer value becomes 0, it is specified that the counted time has elapsed.

  More specifically, when the timekeeping start condition is satisfied in the main process, the main control unit 41 sets an initial value of the timer value according to the timekeeping time in an area to which a timer counter according to the condition is assigned. The set timer value is decremented by one until it becomes 0 approximately every 2.24 ms in the time counter update process of the timer interrupt process (main).

  Then, in the main process, as shown in FIG. 16, the address of the corresponding timer counter is obtained (Si1), the obtained value is read (Si2), and it is determined whether the read value is not 0 (Si3). When it is determined that the read value is 0, it is specified that the clock time has elapsed.

  As shown in FIG. 17, the timer counter used in the present embodiment has a 1-byte timer A having an initial value of 1 byte or less, a 1-byte timer B, a 1-byte timer C, and an initial value of more than 1 byte and not more than 2 bytes. It includes a 2-byte timer A, a 2-byte timer B, a 2-byte timer C, and a 2-byte timer D.

  The 1-byte timer is a timer for measuring a relatively short period that can be measured with a timer value within 1 byte. For example, an external output signal timer that measures an output period of an external output signal, an LED output update period LED update timer that measures the time, a stop invalidation timer that measures the time from when the stop operation is detected until the stop operation is validated again, and a payout wait that measures the time until the payout of medals starts after the reel stops. A timer, an insertion detection timer that measures a period after ON of the insertion medal sensor 31 is detected, an insertion port detection timer that measures a period since ON of the insertion sensor 26 is detected, and ON of the payout sensor 34c is detected. There is a payout detection timer that measures a period from the start of the operation, and a start timer that measures the period from the start of reel rotation until the stop operation becomes effective. Of these, the stop invalidation timer, the payout waiting timer, and the start time timer do not extend over the timing at which one game ends, but the external output signal timer, the LED update timer, the insertion detection timer, the insertion port The detection timer and the payout detection timer may have times measured by these timers straddling the timing at which one game ends.

  The 2-byte timer is a timer for measuring a relatively long period that cannot be measured with a timer value within 1 byte. For example, a 1-game time timer for measuring a prescribed time (about 4.1 seconds) required for 1 game A security signal timer for measuring the minimum output period of the security signal among the external output signals, a standby time timer for measuring a period from the end of the game, a hopper empty timer for measuring a period during which the payout sensor 34c is not detected after the hopper motor 34b is driven. There is a timer. Of these, the standby time timer and the hopper empty timer do not straddle the timing of the end of one game with the measurement period of these timers, but the one game time timer and the security signal timer have the time measured by these timers of one game. May end the timing of the end.

  As described above, the timer counter indicates the timing at which one game ends, that is, the timing at which a part of the RAM 41c is initialized in accordance with the progress of the game (at the end of one game or at the end of a specific game state, Are initialized, and a timer counter that measures a measurement period that extends over a period of time, and a timer counter that does not extend over the timing at which a part of the RAM 41c is initialized in accordance with the progress of the game. The counter is also assigned to a special work that is not initialized at a timing according to the progress of the game.

  Of these timer counters, the one-byte timers A to C are assigned one byte at a time to a continuous three-byte area (7E2Ch to 7E2Eh) of the RAM 41c, and the two-byte timers A to D correspond to eight consecutive bytes of the RAM 41c. Two bytes are allocated to the areas (7E2Fh to 7E35h). Further, 1-byte timers A to C and 2-byte timers A to D are also allocated to continuous areas of the RAM 41c. Hereinafter, the area to which the 1-byte timers A to C are assigned is called a 1-byte timer group, and the area to which the 2-byte timers A to D are assigned is called a 2-byte timer group. That is, both the 1-byte timer group and the 2-byte timer group are set in areas to which consecutive addresses are assigned according to a predetermined rule. The area to which consecutive addresses are assigned according to a predetermined rule is, for example, an area to which a start address and an address added by N (N is a natural number) from the start address are assigned.

  FIG. 18 is a flowchart showing the control contents of the time counter updating process.

  In the time counter update process, first, the number of 1-byte timer counters to be updated (3 in this embodiment) is set as the number of 1-byte processes (Sj1), and the start address (7E2Ch) of the 1-byte timer group is set. The pointer is set (Sj2).

  Next, if the 1-byte value stored at the designated address (the address indicated by the pointer) is not 0, the 1-byte value of the designated address is decremented by 1 (Sj3), and the number of processes set in the step of Sj1 is subtracted by 1. (Sj4), it is determined whether or not the number of processes after the subtraction is 0 (Sj5).

  If the number of times of processing after the subtraction is not 0 in step Sj5, that is, if all the one-byte timers have not been updated, the pointer is incremented by 1 (Sj6), and the process returns to step Sj3. As a result, the pointer moves to the address of the unprocessed 1-byte timer, and if the value of the 1-byte at the specified address is not 0, the pointer is decremented.

  If the number of times of processing after the subtraction is 0 in step Sj5, that is, if all the 1-byte timers have been updated, the number of 2-byte timer counters to be updated is set as the number of 2-byte processings (this embodiment Then, 4) is set (Sj7), and the pointer is incremented by 1 (Sj8). As a result, the pointer moves to the start address (7E2Fh) of the 2-byte counter group.

  Next, if the 2-byte value stored in the area consisting of the designated address (the address indicated by the pointer) and the next address is not 0, the 2-byte value of the designated address and the next address is decremented by 1 (Sj9), and Sj7 The number of times of processing set in the step is subtracted by 1 (Sj10), and it is determined whether or not the number of times of processing after the subtraction is 0 (Sj11).

  If the number of times of processing after the subtraction is not 0 in step Sj11, that is, if all the 2-byte timers have not been updated, the pointer is incremented by 2 (Sj12), and the process returns to step Sj9. As a result, the pointer moves to the address of the unprocessed 2-byte timer, and the value of the designated address and the next address are decremented unless the 2-byte value is 0.

  When the number of times of processing after the subtraction is 0 in step Sj11, that is, when the update of all the 2-byte timers is completed, the processing is ended.

  As described above, in the present embodiment, the value of the timer counter assigned to the RAM 41c is periodically updated, and the passage of time is specified by reaching a specific value (0). Conventionally, when measuring a plurality of types of time intervals, a timer value is set and updated in a plurality of types of processing requiring time measurement, and a program for updating a plurality of types of timer values is provided in each processing. In such a case, the program capacity is increased. In addition, since a plurality of types of timer counters are allocated as a data group for each process in which each is used, it is necessary to read the value of an unrelated address in order to update them collectively in one process. there were.

  On the other hand, in the present embodiment, the area in which a plurality of types of timer counter values are stored is set in the area of the RAM 41c to which consecutive addresses are assigned according to a predetermined rule, and the timer value stored in the designated address is set. Since the updating process is repeated by adding a constant to the current designated address and changing the designated address for the area where the plural types of timer counter values are stored, the plural types of timer values are updated. In addition, the program capacity can be reduced as compared with the case where the processing of designating a plurality of types of addresses and updating the values of the addresses is performed by individual processing.

  It should be noted that the process of updating the timer value stored at the designated address is repeatedly performed while changing the designated address for the area in which the plurality of types of timer counter values are stored by performing a predetermined operation. Any configuration may be used as long as the value is updated. For example, by adding a constant to the current designated address and repeatedly executing while changing the designated address for an area in which a plurality of types of timer counter values are stored, a plurality of types are provided. Or a value corresponding to the number of processes for the reference address (for example, a 1-byte counter, +1 for 1 process, 2 for 2 processes, and 2 In the case of 3, +3...) Is added or subtracted to change the designated address for the area in which a plurality of types of timer counter values are stored. Ri may be configured to update a plurality of types of the timer value by return run.

  Further, in the present embodiment, the configuration is such that the values of the seven types of timer counters of 1-byte timers A to C and the two-byte timers A to D are provided. The process of updating the timer value stored at the specified address in the area where the consecutive addresses are assigned by the specified operation is performed by changing the specified address for the area storing the multiple types of timer values by performing a predetermined operation. If the configuration is such that two or more timer values are updated by repeatedly executing the program, the program capacity can be reduced as described above.

  In addition, only one of the one-byte timer and the two-byte timer sets the value of the timer counter in an area of the RAM 41c to which continuous addresses are assigned according to a predetermined rule, and updates the timer value stored at the specified address. A configuration in which a plurality of types of timer values are updated by performing a predetermined operation while repeatedly changing a designated address for an area in which a plurality of types of timer values are stored and changing the designated address may be used.

  In addition, only a part of the timer counters provided in the main control unit 41 sets the timer value in an area of the RAM 41c to which continuous addresses are assigned according to a predetermined rule, and updates the timer value stored at the designated address. A configuration in which a plurality of timer values are updated by performing a predetermined operation repeatedly while changing a designated address for an area in which a plurality of types of timer values are stored and changing the designated address may be used.

  In the present embodiment, a separate timer counter is provided for each type of period to be measured. For example, one timer counter may be shared for a plurality of types of periods in which the measured periods do not overlap.

  Further, in the present embodiment, as the processing executed by the main control unit 41, a timer interruption processing (main) for periodically performing a predetermined processing regardless of the progress of the game, and a processing in accordance with the progress of the game The main control unit 41 sets an initial value in a timer counter when a time measurement condition is satisfied in the main processing, and performs a plurality of types of processing in a timer interrupt processing (main). Since the timer value is updated, there is no need to provide a process for updating a plurality of types of timer values in each process constituting the main process. Therefore, the program capacity for updating the plurality of types of timer values is reduced. be able to.

  In this embodiment, the timer interrupt process (main) is executed by periodically interrupting the main process. However, in the timer interrupt process performed periodically, a predetermined timer interrupt process is performed regardless of the progress of the game. The main control unit 41 may be configured to perform both a periodic process for performing the performed process and a main process for performing a process that varies stepwise according to the progress of the game. By setting an initial value to the timer counter when the timing condition is satisfied in the processing and updating a plurality of types of timer values in the periodic processing, a plurality of types of timer values can be stored in each processing constituting the main processing. Since there is no need to provide a process for updating, it is possible to reduce the program capacity for updating a plurality of types of timer values.

  Further, in the present embodiment, in the time counter update processing, the value of the designated address is updated on condition that the value of the address is not 0, so that the timer value is updated to an abnormal value. Can be prevented.

  Further, in the present embodiment, in the time counter updating process, the same number of processes as the number of timer counters to be updated are set, and the process of updating the timer value is repeatedly executed by the set number of processes. In addition to simplifying the management of the number of timer counters to be performed, for example, when a plurality of types of timer counters having different update intervals are provided, it is possible to arbitrarily set the type of the timer value to be updated according to the number of processes to be set. it can.

  The number of processes, that is, the number of timer counters to be updated may be set in a program, or may be set by reading a value set in a table.

  In addition, the timer counter to be updated last is set in advance without setting the number of processes first, and the timer value is updated repeatedly until the address of the timer counter is reached. A specific end value (for example, FFh) is stored in the next address of the timer counter to be updated, and the process of repeatedly updating the timer value until the value read from the specified address becomes the specific end value may be repeatedly executed. good.

  Further, in this embodiment, a 1-byte timer counter and a 2-byte timer counter are provided, and a process of updating a 1-byte timer value and a process of updating a 2-byte timer value are separately provided. Therefore, the capacity of the program and the capacity occupied by the timer value in the RAM 41c can be reduced as compared with the case where the process of updating the 1-byte timer value and the process of updating the 2-byte timer value are shared.

  In this embodiment, a 2-byte timer counter is provided to measure a relatively long time corresponding to an initial value exceeding 1 byte. For example, a timer counter having a different update interval, for example, a timer By providing a first timer counter that updates once every four times of interrupt processing (main) and a second timer counter that updates once every fourteen times, a relative value can be obtained without providing a 2-byte counter. In such a configuration, it is not necessary to provide a process of updating the 1-byte timer value and a process of updating the 2-byte timer value. Can reduce the program capacity required for updating the program.

  Further, in the present embodiment, a plurality of types of timer counters are allocated in the RAM 41c to special works that are not initialized according to the progress of the game, and are not initialized according to the progress of the game. Regardless of the progress of the game, it is possible to measure the time of the period spanning the timing at which a part of the RAM 41c is initialized according to the progress of the game.

  In particular, in the present embodiment, the measurement period is not limited to the timer counter that may straddle the timing at which one game ends, that is, the timing at which a part of the RAM 41c is initialized in accordance with the progress of the game. Timer counters that do not straddle the timing at which a part of the RAM 41c is initialized in accordance with the progress are stored together with other timer counters in the area allocated to the special work, so that the timer counters can be easily managed. At the same time, a timer counter that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game, and the timing at which a part of the RAM 41c is initialized according to the progress of the game. The application of the timer counter can be easily changed by a later design change, such as changing to a timer counter that may straddle. It can be. In addition, if the configuration is such that one timer counter is shared for a plurality of types of periods in which the measurement periods do not overlap as described above, the timing at which a part of the RAM 41c is initialized may cross over as the game progresses. It is possible to measure the measurement period and the measurement period that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game with one timer counter.

  As described above, the embodiments of the present invention have been described with reference to the drawings. However, the present invention is not limited to the embodiments, and includes changes and additions within a scope not departing from the gist of the present invention. Needless to say.

  In the embodiment, an example is described in which the present invention is applied to a slot machine in which a bet is set using medals and credits as a game value, but a slot machine in which a bet is set using a game ball as a game value Alternatively, the present invention may be applied to a completely credit-type slot machine that sets a bet amount using only credits as a game value. When a game ball is used as a game value, for example, one medal can correspond to five game balls, and when 3 is set as the bet number in the first embodiment, 15 game balls are used. Is used to set the number of bets.

  Furthermore, the present invention is not limited to the use of only one of a plurality of types of game values such as medals and game balls. For example, a plurality of types of game values such as medals and game balls can be used together. It may be. That is, it is possible to set a bet amount and play a game by using any of a plurality of types of gaming values such as medals and game balls, and to generate a plurality of types of games such as medals and game balls by generating a prize. A slot machine that can pay out any of the utility values may be applied.

  In the embodiment, the slot machine has been described as an example of the gaming machine. However, the main control unit 41 disclosed in the above embodiment and the initial setting process, the timer interruption process, the command storage process, and the normal The sub-control unit 91 and the processing related to the sub-control unit 91, such as a command transmission process, a power-off command transmission process, a timer counter update process, and the like, are performed by launching a game ball to another gaming machine, for example, a gaming area. The present invention may be applied to a pachinko gaming machine or the like in which a game ball is played and a launched game ball enters a prize hole provided in the game area and a prize is generated, whereby the game ball is paid out as a prize ball.

1 Slot machine 2L, 2C, 2R Reel 6 MAXBET switch 7 Start switch 8L, 8C, 8R Stop switch 41 Main controller 91 Sub controller

Claims (1)

In gaming machines that play games,
First control means for performing the first control and capable of holding the control state even when the power supply to the gaming machine is stopped;
A second control unit that performs the second control based on the control information transmitted from the first control unit, and that can maintain the control state even when the power supply to the gaming machine is stopped;
With
The first control means includes:
A power-off process performing means for performing a power-off process for enabling a return to a control state before power supply to the gaming machine is stopped when the power-off condition is satisfied;
Control information storage means for creating control information to be transmitted to the second control means in accordance with the progress of control and storing the control information in a storage area;
First control information transmitting means for transmitting control information stored in the storage area to the second control means at every predetermined opportunity;
A second control information transmitting unit that transmits all control information stored in the storage area to the second control unit before executing the power interruption process when the power interruption condition is satisfied;
When control information according to the progress of control is not stored in the storage area at the predetermined opportunity, specific control information transmitting means capable of transmitting specific control information indicating a state of the first control means,
When the power supply to the gaming machine starts, when returning to the control state before the power supply to the gaming machine is stopped, a predetermined control information transmitting unit that transmits predetermined control information,
Including
When the power supply to the gaming machine is started, the specific control information is transmitted until the predetermined control information is transmitted, even if the control information according to the progress of the control is not stored in the storage area. Not
The period from when the power interruption condition is satisfied to when the first control means becomes inoperable transmits the maximum number of control information that can be stored in the storage area to the second control means, and A gaming machine that is longer than a period required to complete the power interruption process.

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