JP6806435B2 - Game machine - Google Patents

Description

The present invention relates to gaming machines such as pachinko gaming machines and slot machines.

In this type of gaming machine, the program used by the gaming machine for control includes a plurality of types of main modules and common submodules, and is stored in ROM. Each common submodule is stored starting with one of a plurality of specific addresses specified by a parameter having a data size smaller than the program address in the ROM, and is specified by, for example, an RST instruction in another module. When the address is specified, it is called and executed. (See, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2004-229938

In the gaming machine described in Patent Document 1, in order to store the common submodule in the ROM with one of a plurality of specific addresses at the beginning so that the common submodule can be called by the RST command, the next specific address is specified from one specific address in the ROM. If the amount of data in the common submodule is smaller than the capacity of the area up to the address, the ROM area from the end of the stored common submodule to the next specific address may become an empty area, and the ROM Area was not used effectively.

The present invention has been made by paying attention to such a problem, and an object of the present invention is to provide a game machine capable of effectively using a storage area of a program or data.

In order to solve the above problems, the gaming machine of means 1 of the present invention is
In a game machine (slot machine 1) that plays a game
A storage means (ROM41b) that can store a program and is assigned an address that can identify a storage area,
A control means (main control unit 41) that controls according to a program stored in the storage means, and
The first program calling means (CALL instruction, CALLV instruction) that calls the program stored in the specified address by specifying the address, and
By specifying a parameter (3-bit parameter) with a data amount smaller than that of the address, a plurality of specific addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H) assigned at predetermined intervals (8 bytes) are specified. A second program calling means (RST instruction) that calls a program stored at a specific address corresponding to the specified parameter (for example, a subroutine for waiting for an external signal off time).
With
The storage means
A first specific program (for example, a subroutine for waiting for an external signal off time) is stored in an area starting from one specific address, and a second specific program (for example, a second specific program (for example) starts from the next specific address of one specific address. For example, a subroutine of output port 2 output processing) is stored, and a predetermined program (for example, a subroutine of processing a maximum number of inserted medals) is stored in an area after the area in which the first specific program is stored and before the next specific address. stores the,
Including an address storage means for storing the address of the interrupt program,
The control means includes an interrupt processing execution means that executes a program from the address of the interrupt program stored in the address storage means as an interrupt process based on the interrupt.
The game machine is
A determination means for determining at startup whether or not the address stored in the address storage means (vector table) is within a predetermined range (the area of the program area in which the program or the like is actually stored).
Address storage means start inhibiting means addresses stored in the (vector table) for prohibiting the activation of the control means when it is determined that not in the predetermined range (the main controller 41, among address of the vector table in the program area If the program etc. is not the area actually stored, it will not be started),
It is characterized by having.
According to this feature, by specifying a parameter with a data amount smaller than the address, a program stored in a specific address corresponding to the specified parameter among a plurality of specific addresses assigned at predetermined intervals can be called. Therefore, the program capacity related to the program call can be reduced. In addition, the area from after the first specific program stored in the area starting from one specific address to before the next specific address, that is, the space between the first specific program and the second specific program. By storing a predetermined program in the area, the area of the storage means can be effectively used.

The gaming machine of the means 2 of the present invention is the gaming machine according to the means 1.
The control means is characterized in that the second specific program (for example, a subroutine for addition processing) is executed following the predetermined program (for example, a subroutine for setting value display data acquisition processing).
According to this feature, the predetermined program is stored in the area after the area where the first specific program is stored and before the next specific address, and the second specific program is executed following the predetermined program. Only by calling the predetermined program by the first program calling means, it is not necessary to call the second specific program by the second program calling means after the completion of the predetermined program, and the program capacity related thereto can be reduced.

The gaming machine of the means 3 of the present invention is the gaming machine according to the means 1 or the means 2.
The predetermined program is other than an area (specific address area) in which the predetermined program (for example, a part of a program having a data amount larger than the free area between the first specific program and the second specific program) is stored. It is characterized by including a jump instruction to a program stored in the area (for example, the rest of the program stored in the free area).
According to this feature, since the predetermined program includes a jump instruction to the program stored in an area other than the area in which the predetermined program is stored, there is a space between the first specific program and the second specific program. By storing a part of a program having a larger amount of data than the area as a predetermined program in the free area, the area of the storage means can be effectively used.

The gaming machine of the means 4 of the present invention is the gaming machine according to any one of the means 1 to the means 3.
A program starting from a specific address is transferred to a program (for example, the rest of the port output process) stored in an area other than the area (specific address area) in which the program (for example, a part of the port output process) is stored. It is characterized by including a jump command.
According to this feature, a program starting from a specific address includes a jump instruction to a program stored in an area other than the area where the program is stored, so that data is more data than the area from the specific address to the next specific address. Since a program having a large amount can be called by the second program calling means, the program capacity related to the calling can be reduced even for a program having a large amount of data.

The gaming machine of means 5 of the present invention is the gaming machine according to any one of means 1 to 4.
The storage means
The first storage area (game program area) in which the game program (game program) related to the progress of the game is stored, and
A second storage area (non-game program area) in which a non-game program (non-game program) that is a program called by the game program and is not related to the progress of the game is stored,
An unused area (unused area) allocated to the area in front of the rear storage area (non-game program area) allocated to the rear of the first storage area (game program area) and the second storage area (non-game program area). Unused area 1) and
It is characterized by having.
According to this feature, a first storage area in which a game program related to the progress of a game is stored and a second storage area in which a non-game program that is called by the game program and is not related to the progress of the game is stored. , Are allocated separately, and an unused area is allocated to the area in front of the rear storage area allocated to the rear of the first storage area and the second storage area, so that the game program and the non-game program The game program and the game program can be easily specified according to the difference in the storage area.
The front and back of the storage area are the magnitude relations of the address values assigned to the storage area, and the smaller address is the front and the larger address is the rear. Therefore, in the means 5, the rearward storage area allocated to the rear of the first storage area and the second storage area has a larger address value assigned to the first storage area and the second storage area. The storage area of the one is applicable.
Further, the unused area may be allocated in front of the rear storage area, the front storage area, the unused area, and the rear storage area may be allocated adjacent to each other, or the front storage area and the unused area may be allocated adjacent to each other. Another storage area may be allocated between and.

The gaming machine of means 6 of the present invention is the gaming machine according to any one of means 1 to 5.
The control means includes an interrupt processing execution means that executes a process (timer interrupt process (main)) according to an interrupt program based on the interrupt.
The game machine
Address storage means (vector table) that can store the address of the interrupt program (timer interrupt process (main)),
A determination means for determining at startup whether or not the address stored in the address storage means (vector table) is within a predetermined range (the area of the program area in which the program or the like is actually stored).
When it is determined that the address stored in the address storage means (vector table) is not within the predetermined range, the start limiting means (in the main control unit 41, the address of the vector table is in the program area of the program or the like. If it is not the area actually stored, it will not be started),
It is characterized by having.
According to this feature, it is possible to prevent an unintended interrupt process from being executed in advance.

The gaming machine of means 7 of the present invention is the gaming machine according to any one of means 1 to 6.
Setting means for setting the control means (setting of various functions performed with reference to HW parameters) and
An interrupt generation means (timer circuit 509) that generates an interrupt when the interrupt condition is satisfied, and
An interrupt limiting means that limits the occurrence of interrupts by the interrupt generating means,
With
The control means
A processing means for executing processing based on a program (game program or non-game program) after the setting by the setting means is performed, and
An interrupt process execution means that executes an interrupt process (timer interrupt process (main)) based on an interrupt, and
Including
The interrupt limiting means includes a first interrupt limiting means (setting of interrupt prohibition by startup setting) that limits the occurrence of interrupt before the processing based on the program (initial setting process) is started, and a program. It is characterized by including a second interrupt limiting means (setting of interrupt prohibition by initial setting processing) that limits the occurrence of interrupts at the start of processing based on.
According to this feature, it is possible to prevent an unintended interruption from occurring.

The gaming machine of means 8 of the present invention is the gaming machine according to any one of means 1 to 7.
A plurality of timer value storage areas (for example, 1-byte timers A to C) and
When any of a plurality of types of time timing conditions (for example, 1-byte timers A to C) is satisfied, a timer value storage area (for example, 1-byte timer A) corresponding to the time timing conditions is satisfied. To C), a timer value storage means (main process) for storing the timer value according to the timing condition, and
A timer value updating means (time counter updating process) capable of updating the timer values stored in a plurality of timer value storage areas (for example, 1-byte timers A to C) every predetermined cycle (about 2.24 ms).
With
Consecutive addresses (804CH to 804EH) are assigned to a plurality of timer value storage areas (for example, 1-byte timers A to C) according to a predetermined rule (+1).
The timer value update means performs a predetermined operation (designated address + 1) for an update process (process of subtracting 1 from the value indicated by the pointer) for updating the timer value stored in the timer value storage area corresponding to the specified address. The feature is that multiple types of timer values can be updated by repeatedly executing while changing the specified address for the timer value storage area.
According to this feature, consecutive addresses are assigned to a plurality of timer value storage areas according to a predetermined rule, and an update process for updating the timer values stored in the timer value storage area corresponding to the specified address is predetermined. Since multiple types of timer values are updated by repeatedly executing while changing the specified address for the timer value storage area by performing the operation of, when performing the process of updating multiple types of timer values for each type of timer value. The program capacity can be reduced.
It should be noted that the assignment of consecutive addresses according to a predetermined rule means that, for example, an address to which N (N is a natural number) is added from the start address and the start address is assigned.
In addition, changing the designated address for the timer value storage area by performing a predetermined operation means, for example, changing the designated address by adding or subtracting a value according to the number of processes to the current designated address. It corresponds to changing the designated address by adding or subtracting a constant from the reference address. At this time, the value or constant according to the number of processes may differ depending on the storage capacity of the timer value. For example, in the configuration where the timer value is stored byte by byte, the value according to the number of processes is the number of processes. Depending on the number of processes, the values will be 1, 2, 3 ..., and the constant will be 1, but if the timer value is stored by 2 bytes, the value according to the number of processes will be 2, 4, 6 ... Depending on the number of processes. , The constant is 2.

In addition, the present invention may have only the invention-specific matters described in the claims of the present invention, and has a configuration other than the invention-specific matters together with the invention-specific matters described in the claims of the present invention. It may be a thing.

It is a front view of the slot machine of the Example to which this invention was applied. It is a perspective view which shows the internal structure of a slot machine. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of the main control part. It is a figure which shows the memory map of ROM and RAM mounted on the main control part. It is a figure which shows the detail of the memory map of ROM and RAM mounted on the main control unit. It is a figure which shows the detail of the memory map of the program area in the ROM mounted on the main control unit. It is a figure which shows the structure of a game program and a non-game program. It is a figure which shows the relationship between a game area and a non-game area. It is a flowchart which shows the flow of processing when calling a non-game program. It is a flowchart which shows the control content of the initial setting process executed by the main control part. It is a flowchart which shows the control content of the setting change processing executed by the main control part. It is a flowchart which shows the control content of the main process executed by the main control unit. It is a flowchart which shows the control content of the timer interrupt process (main) executed by the main control unit. It is a flowchart which shows the control content of the timer interrupt process (main) executed by the main control unit. It is a flowchart which shows the control content of the command storage process executed by the main control part. It is a flowchart which shows the control content of the normal time command transmission processing which the main control part executes. It is a flowchart which shows the control content of the command transmission processing at the time of power failure executed by the main control unit. It is a flowchart which shows the control content of the power failure process which the main control part executes. It is a timing chart for demonstrating the flow of control at the time of activation and power-off of a main control part and a sub-control part. It is a flowchart which shows the control content when the main control part determines the value of a timer counter in a main process. It is a figure which shows the storage area of the timer counter in RAM. It is a flowchart which shows the control content of the time counter update process executed by the main control part.

A mode for carrying out the gaming machine according to the present invention will be described below based on examples.

An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. As shown in FIG. 1, the slot machine 1 of the present embodiment includes a housing 1a having an open front surface and a housing 1a thereof. It is composed of a front door 1b rotatably and pivotally supported at a side end of the body 1a.

As shown in FIG. 2, inside the housing 1a of the slot machine 1 of this embodiment, reels 2L, 2C, and 2R (hereinafter, left reel, middle reel, and right reel) in which a plurality of types of symbols are arranged on the outer circumference are arranged. ) Are arranged side by side in the horizontal direction, and as shown in FIG. 1, three consecutive symbols among the symbols arranged on the reels 2L, 2C, and 2R can be seen from the see-through window 3 provided on the front door 1b. It is arranged like this.

On the outer peripheral portions of the reels 2L, 2C, and 2R, a predetermined number of symbols (identification information) that can be distinguished from each other are drawn in a predetermined order. The symbols drawn on the outer peripheral portions of the reels 2L, 2C, and 2R are displayed in the upper, middle, and lower three stages in the see-through window 3 provided at substantially the center of the front door 1b.

Each reel 2L, 2C, 2R is rotated by reel motors 32L, 32C, 32R (see FIG. 3) provided corresponding to each, so that the symbols of each reel 2L, 2C, 2R are continuous with the perspective window 3. While the reels 2L, 2C, and 2R are stopped rotating, three consecutive symbols are derived and displayed on the perspective window 3 as a display result.

Inside the reels 2L, 2C and 2R, there are reel sensors 33L, 33C and 33R that detect the reference position for each of the reels 2L, 2C and 2R, and a reel LED 55 that irradiates the reels 2L, 2C and 2R from the back. , Are provided. Further, the reel LED 55 is composed of 12 LEDs corresponding to three consecutive symbols of reels 2L, 2C and 2R, and each symbol can be independently irradiated.

A display area 51a of the liquid crystal display 51 (see FIG. 1) is arranged at a position on the front side (player side) of the reels 2L, 2C, and 2R of the front door 1b. The liquid crystal display 51 has a liquid crystal panel that has transparency in a state where no voltage is applied to the liquid crystal element, and passes through the transmission region 51b and the perspective window 3 corresponding to the perspective window 3 of the display region 51a. The reels 2L, 2C, and 2R can be visually recognized from the player side.

As shown in FIG. 1, the front door 1b has a medal insertion unit 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player-owned game value). MAXBET switch 6, which is operated when setting the maximum number of bets among the specified number of bets determined according to the gaming state within that range, and the setting of medals and bets stored as credits. Settlement switch 10 operated when settling the medals used for (returning the medals used for setting credits and bets), start switch 7 operated when starting the game, reels 2L, 2C Stop switches 8L, 8C, and 8R, which are operated when the rotation of the 2Rs is stopped, are provided so as to be operable by the player.

Further, as shown in FIG. 1, the front door 1b shows a credit display 11 that displays the number of medals stored as credits, the number of medals paid out due to the occurrence of a prize, and the contents when an error occurs. Game auxiliary display 12 that displays an error code, etc., 1BETLED14 that notifies by lighting that the number of bets is set to 1, 2BETLED15 that notifies by lighting that the number of bets is set to 2, and 3 settings to the number of bets. 3BETLED16 that notifies by lighting that the game is being inserted, insertion request LED17 that notifies by lighting that a medal can be inserted, and start effective LED18 that notifies by lighting that the game start operation by operating the start switch 7 is effective. , Waiting LED19 to notify by lighting that the weight (a state of waiting for the start of rotation of the reel because a certain period has not passed since the previous game start) is in progress, and lighting that the replay game is in progress, which will be described later. A game display unit 13 is provided with an LED 20 during replay to be notified by.

Inside the MAXBET switch 6, a BET switch effective LED21 (see FIG. 3) is provided to notify by lighting that the betting number setting operation by operating the MAXBET switch 6 is effective, and the stop switches 8L, 8C, Inside the 8R, left, middle, and right stop effective LEDs 22L, 22C, and 22R (see FIG. 3) are provided to notify by lighting that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is effective. Has been done.

Inside the front door 1b, as shown in FIG. 2, a reset switch 23 for detecting an error state described later and a reset operation for canceling a stop state described later by a predetermined key operation, and a change of a setting value described later. A set value display 24 that displays the set value at that time while checking the inside or the set value, and a hit that controls the stop state (a state in which the progress of the game is restricted until the reset operation is performed) at a predetermined trigger. Stop switch 36a for selecting enable / disable of the stop function, automatic control to automatic settlement processing (processing to settle (return) medals stored as credits regardless of the player's operation) at a predetermined trigger The automatic settlement switch 36b for selecting the enable / disable of the settlement function and the flow path of the medals inserted from the medal insertion unit 4 are provided on the side of the hopper tank 34a (see FIG. 2) described later provided inside the housing 1a. Alternatively, a flow path switching solenoid 30 for selectively switching to either one of the medal payout outlet 9 sides, a medal insertion unit 31 for detecting medals inserted from the medal insertion unit 4 and flowing down to the hopper tank 34a side, and an insertion medal sensor. A medal selector 29 having a slot sensor 26 for detecting the insertion of foreign matter on the upstream side of 31 and a door open detection switch 25 (see FIG. 3) for detecting the open state of the front door 1b are provided.

Inside the housing 1a, as shown in FIG. 2, the above-mentioned reels 2L, 2C, 2R, reel motors 32L, 32C, 32R (see FIG. 3), and reel reference positions of the reels 2L, 2C, and 2R, respectively, are located. Reel unit 2 composed of detectable reel sensors 33L, 33C, 33R (see FIG. 3), external output board 1000 for outputting an external output signal (see FIG. 3), and medals inserted from the medal insertion unit 4 are stored. The hopper tank 34a, the hopper motor 34b for paying out the medals stored in the hopper tank 34a from the medal payout outlet 9 (see FIG. 3), and the payout sensor 34c for detecting the medal paid out by driving the hopper motor 34b (see FIG. 3). A hopper unit 34 and a power supply box 100 (see FIG. 3) are provided.

An overflow tank 35 for storing medals overflowing from the hopper tank 34a is provided on the side of the hopper unit 34. Inside the overflow tank 35, a full tank sensor 35a (see FIG. 3) for detecting that the stored medals are full is provided.

As shown in FIG. 2, the front surface of the power supply box 100 functions as a setting key switch 37 for switching to a setting change state or a setting confirmation state, and a reset switch for canceling an error state or a stop state in normal times. However, in the setting change state, the reset / setting switch 38 that functions as a setting switch for changing the setting value of the winning probability (ball output rate) of the internal lottery described later, and the power supply that is operated when the power is turned on / off. A switch 39 is provided.

Since the power supply box 100 is provided inside the housing 1a and the front door 1b can be opened by a predetermined key operation possessed by a clerk or the like, the power supply box 100 is provided on the front surface of the power supply box 100. The setting key switch 37, the reset / setting switch 38, and the power switch 39 can be operated only by a clerk or the like who has the key, and cannot be operated by the player. The same applies to the reset switch 23 detected by a predetermined key operation. In particular, since the setting key switch 37 requires further key operation after opening the front door 1b by key operation, only the clerk who has the key to operate the setting key switch 37 among the clerk of the amusement park. It is possible to operate.

When playing a game on the slot machine 1 of this embodiment, first, medals are inserted from the medal insertion unit 4, or the number of bets is set using credits. To use the credit, operate the MAXBET switch 6. When the specified number of bets determined according to the game state is set, the winning line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the game can be started. Become. If more than the maximum number of medals are inserted out of the specified number corresponding to the gaming state, that amount will be added to the credit.

The winning line is a line set to determine whether the combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a combination of winning symbols. In this embodiment, as shown in FIG. 1, only the winning line LN set across the symbols arranged horizontally in the middle stage of the reel 2L, the middle stage of the reel 2C, and the middle stage of the reel 2R, that is, the middle stage is used as the winning line. It is set. In this embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

Further, in the present embodiment, in order to make it easy to recognize that the winning line LN has a combination of symbols constituting the winning, the invalid lines LM1 to 4 are set separately from the winning line LN. The invalid lines LM1 to LM1 to 4 are not determined to win by the combination of the symbols aligned with the invalid lines LM1 to 4, but are invalid lines when the winning line LN has a combination of symbols constituting a specific winning. By configuring the combination of symbols (for example, bell-bell-bell) that will be awarded when the winning line LN is aligned with any of LM1 to LM4, the symbols constituting the winning line LN are the symbols that constitute a specific winning. This makes it easier to recognize that the combinations are complete.

When the start switch 7 is operated while the game can be started, the reels 2L, 2C, and 2R are rotated, and the symbols of the reels 2L, 2C, and 2R are continuously changed. When any of the stop switches 8L, 8C, and 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, and 2R is stopped, and the display result is derived and displayed on the perspective window 3.

When all reels 2L, 2C, and 2R are stopped, one game is completed, and a predetermined combination of symbols (hereinafter, also referred to as a combination) on the winning line LN is displayed on each reel 2L, 2C, and 2R. If the game is stopped as a result, a prize will be generated, and a number of medals determined according to the prize will be given to the player and added to the credit. Further, when the maximum number of credits (50 in this embodiment) is reached, medals are directly paid out from the medal payout outlet 9 (see FIG. 1). Further, when the combination of symbols accompanying the transition of the gaming state stops on the winning line LN as the display result of each reel 2L, 2C, 2R, the combination of symbols is shifted to the gaming state according to the combination of symbols. ..

In this embodiment, the game starts when the operation of the start switch 7 is detected while the operation of the start switch 7 is valid, and the game ends when all the reels are stopped. In addition, one unit of control (game control) for executing the game starts when all the controls associated with the end of the previous game are completed, and when all the controls associated with the end of the game are completed. finish.

Further, in this embodiment, a configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, and a configuration using four or more reels may be used. In the configuration using two or more reels, the winning may be determined based on the combination of the display results derived to all the two or more reels. Further, in this embodiment, the variable display device is configured by a physical reel, but the variable display device may be configured by an image display device such as a liquid crystal display.

Further, in the slot machine 1 in the present embodiment, after the game is started and the reels 2L, 2C, and 2R are rotated to start the fluctuation of the symbol, one of the stop switches 8L, 8C, and 8R is operated. When this is done, the rotation of the reels corresponding to the stop switches 8L, 8C, 8R is stopped and the symbol is stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

The reels 2L, 2C, and 2R rotate 80 times per minute and change the symbol of 80 x 21 (the number of symbol frames per reel) = 1680 frames, so that a maximum of 4 frames can be drawn in 190 ms. You will be able to do it. That is, the symbols that can be selected as the stop symbols are the symbols displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols up to 4 frames ahead of the stops, for a total of 5 frames.

Therefore, for example, when any of the stop switches 8L, 8C, and 8R is operated, when the symbol displayed at the bottom of the reel corresponding to the stop switch is used as a reference, the symbol is up to 4 frames ahead. Since the symbol can be displayed in the lower row, the symbol displayed in the middle row of the reel corresponding to the stop switch when any of the stop switches 8L and 8R is operated in each of the reels 2L, 2C and 2R. Designs arranged within 5 frames including the above can be displayed on the winning line.

In the following, reels 2L, 2C, and 2R may be simply referred to as reels when it is not necessary to distinguish them. Further, the reel 2L may be referred to as a left reel, the reel 2C may be referred to as a middle reel, and the reel 2R may be referred to as a right reel. Further, the operation of stopping the reels 2L, 2C and 2R by operating the stop switches 8L, 8C and 8R may be referred to as a stop operation.

FIG. 3 is a block diagram showing the configuration of the slot machine 1. As shown in FIG. 3, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game control board 40 controls the game state, and the effect control board 90 controls the game state. The effect is controlled according to the above, and the drive power supply for the electric components constituting the slot machine 1 is generated by the power supply board 101 and supplied to each part.

An AC100V power supply is supplied to the power supply board 101 from the outside, and a DC voltage required for driving the electric components constituting the slot machine 1 is generated from the AC100V power supply, so that the game control board 40 and the effect control board 90 are generated. It is supposed to be supplied to. Further, the above-mentioned hopper motor 34b, payout sensor 34c, full tank sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

The game control board 40 includes the MAXBET switch 6, the start switch 7, the stop switch 8L, 8C, 8R, the settlement switch 10, the reset switch 23, the stop switch 36a, the automatic settlement switch 36b, the input medal sensor 31, and the door opening. The detection switch 25, the reel sensors 33L, 33C, and 33R are connected, and the payout sensor 34c, the full tank sensor 35a, the setting key switch 37, and the reset / setting switch 38 described above are connected via the power supply board 101. The detection signals of these connected switches are input. Further, on the game control board 40, the above-mentioned credit display 11, game auxiliary display 12, 1-3 BETLED 14 to 16, input request LED 17, start effective LED 18, wait LED 19, replay LED 20, BET switch effective LED 21, left. , Middle, right stop effective LEDs 22L, 22C, 22R, set value display 24, flow path switching solenoid 30, reel motors 32L, 32C, 32R are connected, and the hopper motor 34b described above is connected via the power supply board 101. These electric components are connected and are driven based on the control of the main control unit 41 described later mounted on the game control board 40.

The game control board 40 is composed of a main control unit 41 that performs processing related to the progress of the game, a control clock generation circuit 42 that generates a control clock CCLK, a random clock generation circuit 43 that generates a random clock RCLK, and switches. The switch detection circuit 44 that takes in the input detection signal and transmits it to the main control unit 41, the motor drive circuit 45 that transmits the motor drive signal (phase signal of the stepping motor) to the reel motors 32L, 32C, 32R, and the solenoid drive signal. The solenoid drive circuit 46 that transmits to the flow path switching solenoid 30, the LED drive circuit 47 that transmits LED drive signals to various indicators and LEDs, and the main control unit 41 sends a voltage drop signal to that effect when a voltage drop is detected. A power failure detection circuit 48 that outputs to the main control unit 41 and a reset circuit 49 that gives a system reset signal to the main control unit 41 when the power supply is unstable such as when the power is turned on or when the power is cut off are mounted.

FIG. 4 shows a configuration example of the main control unit 41 mounted on the game control board 40. The main controller 41 shown in FIG. 4 is a one-chip microcomputer, which includes an external bus interface 501, a clock circuit 502, a collation block 503, a unique information storage circuit 504, an arithmetic circuit 505, and a reset / interrupt. Controller 506, CPU (Central Processing Unit) 41a, ROM (Read Only Memory) 41b, RAM (Random)
Access Memory) 41c, free run counter circuit 507, random number circuits 508a, 508b, timer circuit 509, interrupt controller 510, parallel input port 511, serial communication circuit 512, parallel output port 513, and address. It is configured to include a decoding circuit 514.

The reset / interrupt controller 506 is for controlling various resets and interrupt requests that occur inside or outside the main control unit 41. The reset / interrupt controller 506 includes an out-of-designated area travel prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit that monitors whether or not the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when it detects that the user program is executed outside the designated area. Further, the watchdog timer 506b has a function of generating a timeout signal for each set period.

The external bus interface 501 is a bus interface having an interface function between the external bus and the internal bus of the chip constituting the main control unit 41, an address bus, a data bus, and a direction control function for each control signal. The clock circuit 502 is a circuit that generates the internal system clock SCLK by dividing the control clock CCLK by two or the like. The collation block 503 has a function of connecting to an external collation machine and collating chips. The unique information storage circuit 504 is a circuit that stores a plurality of types of unique information that is internal information of the main control unit 41. The arithmetic circuit 505 is a circuit that performs multiplication and division.

The CPU 41a is a control CPU that executes game control in the slot machine 1 by executing a user program (game control processing program for game control) based on the control code read from the ROM 41b. When such game control is executed, a fixed data read operation in which the CPU 41a reads fixed data from the ROM 41b, a variable data writing operation in which the CPU 41a writes various variable data to the RAM 41c and temporarily stores them, and a CPU 41a is temporarily stored in the RAM 41c. Variable data read operation to read various variable data, CPU 41a receives input of various signals from the outside of the main control unit 41 via the external bus interface 501, parallel input port 511, serial communication circuit 512, etc., CPU 41a Also performs transmission operations such as outputting various signals to the outside of the main control unit 41 via the external bus interface 501, the serial communication circuit 512, the parallel output port 513, and the like.

The ROM 41b stores a control code indicating a user program (game control processing program for game control), fixed data, and the like. The RAM 41c provides a work area or the like for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power supply. That is, even if the power supply to the slot machine 1 is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period.

An 8-bit free run counter is mounted as the free run counter circuit 507. The random number circuits 508a and 508b are circuits that generate numerical data such as 8-bit random numbers and 16-bit random numbers, which are random number values having a predetermined update range. In this embodiment, the hardware random number generated by the 16-bit random number circuit 508b out of the random number circuits 508a and 508b is used as a random number for internal lottery described later. The timer circuit 509 is a 16-bit programmable timer, which counts down the set timer value based on the input of the control clock CCLK, and outputs an interrupt request signal to the interrupt controller when it reaches 0000H. In this embodiment, the timer circuit 509 can be used to perform periodic interrupt requests and time measurement.

The interrupt controller 510 is a circuit that controls an external interrupt request from an interrupt terminal and an interrupt request from a built-in peripheral circuit (for example, serial communication circuit 512, random number circuits 508a, 508b, timer circuit 509). .. The parallel input port 511 has a built-in 8-bit wide input-only port. Further, the parallel output port 513 included in the main control unit 41 shown in FIG. 4 has a built-in 11-bit wide output dedicated port. The serial communication circuit 512 is a circuit that performs asynchronous serial communication in input / output to the outside.

The address decoding circuit 514 is a circuit for decoding each functional block inside the main control unit 41 and decoding a chip select signal which is a decoding signal for an external device. The chip select signal enables the internal circuit of the main control unit 41 or an external device as a peripheral device to be selectively and effectively operated to be accessed from the CPU 41a.

The main control unit 41 transmits various commands to the sub control unit 91 via the parallel output port 513. The command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and the command is not sent from the sub control unit 91 to the main control unit 41. Further, in this embodiment, the command is transmitted to the sub control unit 91 via the parallel output port 513, that is, the command is transmitted as a parallel signal, but the command is transmitted via the serial communication circuit 512. A configuration in which a command is transmitted to the sub control unit 91, that is, a configuration in which the command is transmitted as a serial signal may be used.

Further, the main control unit 41 inputs the detection states of various switches connected to the game control board 40 from the parallel input port 511. Then, the main control unit 41 executes a basic process of gradually shifting according to the detection states of various switches input from the parallel input ports 511. Further, the main control unit 41 can interrupt the basic process and execute the interrupt process when the interrupt occurs. In this embodiment, a time-out occurs in the timer circuit 509, that is, the timer interrupt process (main) described later is executed at regular time intervals (about 0.56 ms in this embodiment). Further, the main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, priority is given according to a predetermined order. The interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process ends, a new interrupt will occur at that point. It will be.

As a basic process, the main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes, and responds to the change in the detection state of the various switches. Execute the process of gradual migration. Further, the main control unit 41 executes the timer interrupt process (main) at regular time intervals (about 0.56 ms in this embodiment). The execution interval of the timer interrupt process (main) is set to be longer than the total time of the time in which the process repeated according to the control state in the basic process completes and the execution time of the timer interrupt process (main). This means that the process of repeating the timer interrupt process (main) between this time and the next time according to the control state always completes at least one cycle.

A liquid crystal display 51, an effect LED 52, speakers 53, 54, a reel LED 55, and other effect devices are connected to the effect control board 90, and these effect devices are sub-controls described later mounted on the effect control board 90. It is driven based on the control by the unit 91. In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, the effect LED 52, the speakers 53, 54, and the reel LED 55. However, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board separately from the sub control unit 91, and the sub control unit 91 is based on a command from the main control unit 41. The output pattern of the effect device may be determined, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be used. The output control of the production device is performed by both units. Further, in this embodiment, the liquid crystal display 51, the effect LED 52, the speakers 53, 54, and the reel LED 55 are exemplified as the effect device, but the effect device is not limited to these, and for example, a mechanically driven display is used. A device or a mechanically driven role object may be applied as a directing device.

The effect control board 90 is composed of a microcomputer provided with a sub CPU 91a, ROM 91b, RAM 91c, and I / O port 91d, and is a liquid crystal display connected to the effect control board 90 and the sub control unit 91 that controls the effect. From the display control circuit 92 that controls the display of 51, the effect LED 52, the LED drive circuit 93 that controls the drive of the reel LED 55, the audio output circuit 94 that controls the audio output from the speakers 53, 54, when the power is turned on, or from the sub CPU 91a. Reset circuit 95 that gives a reset signal to the sub CPU 91a when the initialization command of is not input for a certain period of time, switch detection circuit 96 that detects the detection signal input from the switches connected to the effect control board 90, date information and time. The power supply voltage supplied to the clock device 97 and the slot machine 1 that output time information including information is monitored, and when a voltage drop is detected, a voltage drop signal indicating that is output to the sub CPU 91a. A detection circuit 98, other circuits, etc. are mounted, and the sub CPU 91a receives a command transmitted from the game control board 40, performs various controls for performing the effect, and is mounted on the effect control board 90. Directly or indirectly control each part of the control circuit.

In the game control board 40, the reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that gives the system reset signal to the main control unit 41, and the sub control unit 91 controls the main control when the power is turned on. It is designed to start at an earlier stage than the unit 41. On the other hand, the power failure detection circuit 98 is set to have a lower voltage for outputting the voltage drop signal than the power failure detection circuit 48 for outputting the voltage drop signal to the main control unit 41 in the game control board 40, and is set to have a lower voltage when the power is cut. The sub control unit 91 detects a power failure at a stage later than that of the main control unit 41, and performs a power failure process (sub) described later.

Like the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. , Executes command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 generates an interrupt every time the number of input of the system clock reaches a certain number, that is, at a fixed time interval (about 2 ms), and executes a timer interrupt process (sub) described later. Further, unlike the main control unit 41, the sub control unit 91 interrupts the process when an interrupt occurs based on the reception of a command, even if the timer interrupt process (sub) is being executed. The command reception interrupt process is executed at the same time, and even if the interrupt that triggers the timer interrupt process (sub) occurs at the same time, the command reception interrupt process is executed with the highest priority. Further, the backup power supply is also supplied to the sub control unit 91 at the time of a power failure, and the data stored in the RAM 91c is held while the backup power supply is supplied.

In the slot machine 1 of this embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using the winning probability according to the set value in the lottery that affects the advantage to the player such as the internal lottery, the navigation stock lottery, and the additional lottery described later. The set value is composed of 6 stages from 1 to 6, with 6 having the highest payout rate, and the smaller the value in the order of 5, 4, 3, 2, 1 the lower the payout rate. That is, when 6 is set as the set value, the advantage is highest for the player, and the smaller the value in the order of 5, 4, 3, 2, 1 is, the lower the advantage is.

In order to change the set value, it is necessary to turn on the power of the slot machine 1 after turning on the setting key switch 37. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 41c is displayed as a display value on the setting value display 24, and the setting value can be changed by operating the reset / setting switch 38. Move to the changed state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated by 1 (when the setting value 6 is further operated, the setting value is changed to 1). Return). Then, when the start switch 7 is operated, the display value is fixed as the set value. Then, when the setting key switch 37 is turned off, the confirmed display value (set value) is stored in the RAM 41c of the main control unit 41, and the game shifts to a state in which the game can proceed.

It should be noted that when the power is turned on while the setting key switch 37 is ON, the setting shift state is also provided on the condition that the door open detection switch 25 detects the opening of the front door 1b. Well, with such a configuration, it is possible to prevent the setting from being changed illegally when the front door 1b is not opened. Further, in the configuration of shifting to the setting change state on condition that the detection corresponding to the opening of the front door 1b is performed, the door opening detection switch 25 corresponds to the opening of the front door 1b after shifting to the setting change state. It is preferable to maintain the setting change state even if the detection is not performed. Therefore, even if the front door 1b is temporarily closed during the setting change, the operation for shifting to the setting change state is performed again. It is not necessary and the setting change operation is not complicated. Further, when the setting key switch 37 is turned off after the start switch 7 is operated to confirm the set value after shifting to the setting change state, the door open detection switch 25 detects the front door 1b to be opened. On the condition that the setting is changed, the setting change state may be terminated and the game may proceed to a state in which the game can proceed. Even in such a configuration, the front door 1b is illegally opened. It is possible to prevent the setting from being changed.

Further, in order to confirm the set value, the setting key switch 37 may be turned on after the game is finished and the bet number is not set. When the setting key switch 37 is turned on in such a situation, the setting value display 24 displays the setting value read from the RAM 41c, so that the setting value can be confirmed. In the setting confirmation state, the progress of the game is impossible, and by turning off the setting key switch 37, the setting confirmation state ends and the game returns to the state in which the progress is possible.

After the game is over, when the setting key switch 37 is turned on while the number of bets is not set, it is a condition that the door opening detection switch 25 detects the opening of the front door 1b. In addition, a configuration that shifts to the setting confirmation state may be used, and such a configuration can prevent the setting value from being illegally confirmed when the front door 1b is not opened. Further, in the configuration of shifting to the setting confirmation state on the condition that the detection corresponding to the opening of the front door 1b is performed, the door opening detection switch 25 corresponds to the opening of the front door 1b after shifting to the setting confirmation state. It is preferable to maintain the setting confirmation state even if the detection is not performed. Therefore, even if the front door 1b is temporarily closed during the setting confirmation, the operation for shifting to the setting confirmation state again is performed. It is not necessary and the setting confirmation operation is not complicated. Further, when the setting key switch 37 is turned off after the start switch 7 is operated to confirm the set value after shifting to the setting confirmation state, the door open detection switch 25 detects the front door 1b to be opened. On the condition that the setting is confirmed, the setting confirmation state may be terminated and the game may be returned to the state in which the game can proceed. Even in such a configuration, the front door 1b is illegally not opened. It is possible to prevent the set value from being confirmed.

In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not a voltage drop signal from the power failure detection circuit 48 is detected each time the timer interrupt process (main) is executed. When the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process, the power failure process (main) for setting the data for determining whether the data in the RAM 41c is normal at the next return is performed. Execute.

Then, the main control unit 41 returns the processing state of the main control unit 41 to the state before the power failure based on the data stored in the RAM 41c, provided that the data in the RAM 41c is normal at the time of its activation. However, when the RAM 41c data is not normal, it is determined that the RAM is abnormal, the RAM error error code is set in the register to control the RAM error error state, and the progress of the game is disabled.

The error state shifts to the normal error state that is canceled by the reset operation (operation of the reset / setting switch 38 or the reset switch 23) and the setting change state described above, and is canceled until a new setting value is set. The RAM error state is a special error state, including the special error state without, and once controlled to the RAM error error state, it shifts to the setting change state and is released until a new setting value is set. Will not be done.

Further, the sub control unit 91 also determines whether or not the voltage drop signal from the power interruption detection circuit 98 is detected in the timer interrupt processing (sub), and when it is determined that the voltage drop signal is detected, At the next return, the power interruption process (sub) for setting the data for determining whether the data in the RAM 91c is normal is executed.

Then, the sub-control unit 91 returns the processing state of the sub-control unit 91 to the state before the power failure based on the data stored in the RAM 91c, provided that the data in the RAM 91c is normal at the time of its activation. However, when the data in the RAM 91c is not normal, it is determined that the RAM is abnormal, and the RAM 91c is initialized. In this case, unlike the main control unit 41, only the RAM 91c is initialized, and the execution of the effect is not disabled.

Further, even if it is determined that the data in the RAM 91c is normal at the time of its activation, the sub control unit 91 is activated when it receives a setting command described later indicating that the setting has been changed from the main control unit 41. The RAM 91c is initialized even when neither the return command nor the setting command, which will be described later, indicating that the control state of the main control unit 41 has been restored is received even after a certain period of time has elapsed. In this case as well, only the RAM 91c is initialized, and the execution of the effect is not disabled.

Next, the initialization of the RAM 41c of the main control unit 41 will be described. The usable area of the storage area of the RAM 41c of the main control unit 41 is divided into an important work, a special work, a general work, an unused area, and a stack area, and the important work, the special work, the general work, and the unused area. , The stack area is arranged in this order.

In this embodiment, the main control unit 41 displays the data of the RAM 41c when the setting key switch 37 is started when the setting key switch 37 is ON and the data of the RAM 41c is destroyed when the setting key switch 37 is started. When it is not destroyed, when the data of RAM 41c is destroyed at the time of starting with the setting key switch 37 ON, at the end of setting change, at the end of a specific game state, at the end of one game When the initialization condition is satisfied, four types of initialization with different regions to be initialized are performed according to each initialization condition.

Initialization 0 is when the data in the RAM 41c is destroyed when the setting key switch 37 is started up in the OFF state, or when the data in the RAM 41c is destroyed when the setting key switch 37 is started up in the ON state. In the initialization 0, all the usable areas are initialized. Initialization 1 is initialization performed when the data in the RAM 41c is not destroyed at the time of starting with the setting key switch 37 ON, and in initialization 1, other than the important work and the special work in the usable area. Area is initialized. The initialization 2 is an initialization performed at the end of a specific gaming state, and in the initialization 2, the general work, the unused area, and the unused stack area among the usable areas are initialized. The initialization 3 is an initialization performed at the end of one game, and in the initialization 3, the unused area and the unused stack area among the usable areas are initialized. The storage area of the data indicating the set value and the game state is allocated to the special work, and the data of the RAM 41c is not destroyed at the time of starting with the setting key switch 37 ON, that is, the data of the RAM 41c. If is normal and the setting is changed, the set value and the data indicating the game state will be retained. Further, the storage area of the timer counter, which will be described later, is allocated to the special work, and is retained without being initialized at the end of the game or the end of a specific game state.

In the slot machine 1 of the present embodiment, a specified number of bets that can be set according to the gaming state is determined, and the game is provided on the condition that the specified number of bets determined according to the gaming state is set. Can be started. In this embodiment, the winning line LN is activated when a predetermined number of bets are set according to the gaming state.

Then, in this embodiment, when all reels 2L, 2C, and 2R are stopped, the activated winning line (in the case of this embodiment, all winning lines are always activated, so that the following is valid. A winning line is obtained when a combination of symbols called a role is aligned on the winning line (the winning line is simply called the winning line). The combination may be a combination of the same symbols or a combination including different symbols.

The types of winning roles are determined according to the game status, but they can be broadly divided into small roles that involve paying out medals and re-starting the next game without the need to set the number of bets. There is a game role and a special role with a transition to a game state that is advantageous to the player. In the following, the small role and the replay role are collectively referred to as the general role. In order for each winning combination determined according to the game state to be won, it is necessary to win the internal lottery described later and set the winning flag of the winning combination in the RAM 41c. Of the winning flags for each of these combinations, the winning flags for the small combination and the replay combination are valid only in the game in which the flags are set, and are invalid in the next game, but the winning flag for the special combination is , It is valid until the combinations of the allowed combinations are complete by the flag, and is invalid in the game in which the combinations of the allowed combinations are complete. That is, once the winning flag of the special role is won, even if the combination of the winning combination permitted by the flag cannot be aligned, the winning flag is not invalidated and is carried over to the next game. It becomes.

Hereinafter, the internal lottery of this embodiment will be described. The internal lottery is performed before the display results of all reels 2L, 2C, and 2R are derived (specifically, the start switch 7) whether or not the main control unit 41 allows the winning of each of the above-mentioned combinations. Is determined at the time of detection). In the internal lottery, first, a random number value (an integer of 0 to 65535) for the internal lottery is acquired when the start switch 7 is detected. Specifically, the value generated by the random number circuit 508b and stored in the random number value register of the random number circuit 508b is set in the lottery work assigned to the RAM 41c. Then, for each winning combination determined according to the gaming state, according to the numerical data stored in the lottery work and the number of determination values of each winning combination determined according to the current gaming state, the number of bets, and the set value. It is determined whether or not to allow the prize.

In the internal lottery, the number of judgment values determined according to the winning combination, the current game state, and the set value to be the target of the internal lottery is sequentially added to the random number value for the internal lottery (numerical data stored in the lottery work). When the numbers are added and the result of the addition overflows, it is determined that the winning combination has been won. Therefore, the winning combination is won with a probability (number of determination values / 65536) according to the magnitude of the number of determination values.

Then, when the winning of any of the winning combinations is determined, the winning flag corresponding to the winning combination is set in the internal winning flag storage work assigned to the RAM 41c. The internal winning flag storage work is composed of a 2-byte storage area, in which the upper byte is assigned as the special role storage work in which the winning flag of the special combination is set, and the lower byte is the winning of the general combination. It is assigned as a general role storage work for which a flag is set. Specifically, when the special role is won, the winning flag of the special role indicating that the special role has been won is set in the special role storage work, and the winning flag set in the general role storage work is cleared. In addition, when the general role is won, the winning flag of the general role indicating that the general role has been won is set in the general role storage work. If neither combination nor combination of combinations is won, only the general combination storage work is cleared.

Next, the stop control of the reels 2L, 2C and 2R will be described. The main control unit 41 refers to the table index and the table creation data stored in the ROM 41b when the reel starts to rotate and when the reel stops and the reel that is still rotating remains. , Create a stop control table for each spinning reel. The stop control table is data that can specify the number of slip frames for each timing when the stop operation is performed. Then, when any operation corresponding to the rotating reel is effectively detected among the stop switches 8L, 8C, and 8R, the stop control table of the corresponding reel is referred to, and the referenced stop control table is slipped. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, and 2R corresponding to the operated stop switches 8L, 8C, and 8R.

In this embodiment, a value of 0 to 4 is set as the number of sliding frames, and it is possible to pull in a maximum of 4 symbols to stop the reel after detecting the stop operation. That is, the stop position of the symbol can be specified from a range of up to 5 frames including the stop operation position where the stop operation is detected. Further, since it is necessary to move one frame to move the reel for one symbol, it is possible to pull in a maximum of four symbols after detecting the stop operation to stop the reel, and stop when the stop operation is detected. It is possible to specify the stop position of a symbol from a range of up to 5 symbols including the operation position.

In this embodiment, when any of the winning combinations is won, when the stop operation is performed, the winning winning combinations can be stopped together on the winning line within a pull-in range of up to 4 frames. If possible, control is performed to align and stop the winning combination, and control is performed to stop the winning combination without aligning it within a pull-in range of a maximum of 4 frames. If the special role and the small role are won at the same time, such as when the special role is carried over from before the previous game and the small role is won, the maximum on the winning line is when the stop operation is performed. If the winning small wins can be aligned and stopped within the pull-in range of 4 frames, the control is performed to align and stop the small wins that have been won within the pull-in range of up to 4 frames on the winning line. If it is not possible to draw in, if it is possible to align and stop the winning special roles in the drawing range of up to 4 frames on the winning line, control is performed to align and stop them, and the winning combination is Control is performed so that the four frames are stopped without being aligned within the pull-in range. That is, in such a case, the control of aligning the small winning combination on the winning line is prioritized over the special winning combination, and the special winning combination can be won only when the small winning combination cannot be drawn in. If the special role and the small role can be drawn in at the same time, only the small role will be drawn in, and the small role will not be aligned on the winning line at the same time as the special role. In addition, when a special role and a small role are won at the same time, the control to align the special role on the winning line is prioritized over the small role, and only when the special role cannot be drawn in, the small role is placed on the winning line. Alignment control may be performed.

Further, in this embodiment, when the special role and the re-game combination are won at the same time, such as when the special role is carried over from before the previous game and the re-game combination is won, the stop operation is performed. At that time, control is performed so that the symbols of the re-game combination are aligned and stopped within a pull-in range of up to 4 frames on the winning line. In this case, the symbols constituting the re-game combination or the symbols constituting the re-game combination to be elected at the same time are arranged within 5 symbols, that is, within 4 frames for each of the reels 2L, 2C, and 2R. Since it can always be stopped at any position within the pull-in range of 4 frames, if the special role and the re-game combination are won at the same time, regardless of the operation timing of the stop switches 8L, 8C, 8R by the player. Instead, all the re-game roles will be awarded. That is, in such a case, the control of aligning the re-game combination on the winning line is prioritized over the special combination, and the re-game combination is sure to win the prize. If the special role and the re-game role can be drawn in at the same time, only the re-game role will be drawn in, and the special role will not be aligned on the winning line at the same time as the re-game role.

In this embodiment, the reel stop control is performed using a stop control table that can specify the number of slip frames for each timing when the stop operation is performed. However, the stop position that can specify the stop position can be specified. A configuration that specifies the stop position from the table and stops the reel at the specified stop position, and searches for a stop position that can be stopped at the timing when the stop operation is performed without using the stop control table or stop position table. A configuration that performs stop control to specify and stop the reel at the specified stop position, stop control using the stop control table, stop control using the stop position table, and stop without using the stop control table or stop position table. A configuration in which stop control by searching and specifying a stop position may be used together, or a configuration in which a stop control table or a stop position table is partially changed to perform stop control may be used.

In the present embodiment, the main control unit 41 measures the game time, which is the time elapsed from the time when the rotation of the reel is started after the start of the game, that is, the time when the rotation of the reel is started. After the end of one game, a specified number of bets are set by inserting medals, etc., and when the game start operation is performed with the game start operation enabled, the reel rotation of the previous game starts. If the game time at which the counting is started from the time point is equal to or longer than the specified time (4.1 seconds in this embodiment), that is, if the specified time has elapsed from the start time of reel rotation of the previous game, no wait is generated. At that point, the rotation of the reel for the game in the game is started. On the other hand, after the end of one game, a specified number of bets are set by inserting medals, etc., and when the game start operation is performed with the game start operation enabled, the reel rotation of the previous game starts. If the game time at which timing is started from that point is less than the specified time, that is, if the specified time has not elapsed since the start of reel rotation in the previous game, a wait is generated and the reel rotation is started at that point. Instead, the game waits until the game time at which timing is started from the start of reel rotation of the previous game reaches the specified time, and when the specified time is reached, the rotation of the reel is started.

In this embodiment, the main control unit 41 controls to output an external output signal indicating a gaming state, an error occurrence status, and the like. These external output signals are output to hall equipment such as a hall computer via an information providing terminal board of a game store (hall) in which the external output board 1000 and the slot machine 1 are installed.

The main control unit 41 has a medal IN signal indicating the number of medals used for setting the number of bets, a medal OUT signal indicating the number of medals given to the player due to the occurrence of a prize, and a game state of RB (regular bonus). An RB signal indicating that the game is in progress, a BB signal indicating that the game state is in BB (big bonus), an RT signal indicating that RT2 is in progress, and a door opening signal indicating that the front door 1b is open, which will be described later. A setting change signal indicating that the mode has been changed to the setting change mode, an insertion error signal indicating an abnormality of the medal selector, and a payout error signal indicating an abnormality of the hopper unit 34 are output.

The external output board 1000 is provided with a relay circuit, a parallel / serial conversion circuit, terminals for each output signal, and a connector to be connected for electrically connecting to the circuit of the information providing terminal board. Among the signals output from the game control board 40, the medal IN signal, the medal OUT signal, the RB signal, and the BB signal are directly output as pulse signals to the information providing terminal board via the relay circuit. On the other hand, the door open signal, the setting change signal, the input error signal, and the payout error signal are converted into a security signal which is a serial signal that can be individually identified by the parallel serial conversion circuit to provide information. It is output to the terminal board.

Next, a command transmitted by the main control unit 41 to the sub control unit 91 will be described.

In this embodiment, the main control unit 41 gives the sub control unit 91 a number of input commands, a credit command, a game state command, an internal winning command, a reel acceleration information command, a stop operation command, a slip frame number command, and a stop. Sends multiple types of commands, including commands, game end commands, winning number commands, payout start commands, payout end commands, standby commands, stop commands, error commands, return commands, setting commands, setting confirmation commands, and door commands.

The number of inserted medals command is a command that can specify the number of inserted medals, that is, the number of medals used to set the number of medals, and is a state from the end of the game (after changing the setting) to the start of the game, when the power is restored. , Or when a medal is inserted in a state where the specified number of bets is not set, or when the MAXBET switch 6 is operated to set the bet number, the medal is transmitted. Further, since the input number command is transmitted when the bet number setting operation is performed, it is possible to identify that the bet number setting operation has been performed by receiving the input number command. The credit command is a command that can specify the number of medals stored as credits, is a state from the end of the game (after changing the setting) to the start of the game, and in a state where a specified number of bets are set. Sent when a medal is inserted and credits are added.

The game state command is a command that can specify the game state of the game, and is transmitted when the start switch 7 is operated to start the game. The internal winning command is a command that can specify the internal lottery result, and is transmitted when the start switch 7 is operated to start the game and after the game state command is transmitted. Since the game status command and the internal winning command are transmitted when the start switch 7 is operated and the game starts, it is possible to identify that the start switch 7 is operated and the game has started by receiving these commands. Is.

The reel acceleration information command is a command that can specify that the reel rotation starts as the game progresses, and is transmitted when the reel rotation starts as the game progresses. The stop operation command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, or the area number of the stop operation position of the corresponding reel, and is used for the stop operation of each reel. It is transmitted every time the accompanying stop control is performed. The slide frame number command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and the number of slide frames that move from the stop operation of the corresponding reel to the stop. Therefore, each time the stop control associated with the stop operation of each reel is performed, the corresponding stop operation command is transmitted and then transmitted. The stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, or the area number of the stop position of the corresponding reel, and is a stop control associated with the stop operation of each reel. Is sent after the corresponding slip frame count command is sent each time. The stop operation command, the number of sliding frames command, and the stop command can all specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and are accompanied by the stop operation of each reel. Since it is transmitted every time the stop control is performed, it is possible to specify that the stop operation of any of the reels has been performed and the reel to be stopped by receiving these commands.

The game end command is a command that can specify that the game has ended, and is transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch. The winning number command is a command that can specify the combination of symbols aligned on the winning line LN, the presence or absence of winning, the type of winning, and the number of medals to be paid out at the time of winning, so that the player stops the third stop reel. It is when the stop switch is pressed and the stop switch is released, and is transmitted after the game end command is transmitted. Both the game end command and the winning number command are transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch. Therefore, by receiving these commands, It is possible to identify that all the operations necessary for advancing one game have been completed.

The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals by winning a prize or settlement of credits (including the medal used for setting the number of bets) is started. In addition, the payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning a prize and settlement of credits is completed.

The standby command is a command indicating that the game shifts to the standby state, and when the game shifts to the standby state after the estimated end time (60 seconds in this embodiment) elapses without setting the number of bets after one game ends, credits It is sent after the payout of medals by settlement (including the medal used to set the number of bets) is completed and the payout end command is sent.

The stop command is a command indicating the occurrence or release of the stop state, and when the ending effect waiting time elapses after the end of the BB, the stop command indicating the occurrence of the stop state is transmitted and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted. An error command is a command that indicates the occurrence or cancellation of an error state and the type of error state. When an error is determined and controlled to an error state, an error command indicating the occurrence of an error state and its type is sent and reset. When the operation is performed and the error state is cleared, an error command indicating the error state is cleared is sent.

The return command is a command indicating that the main control unit 41 has returned to the control state before the power failure, and is transmitted when the main control unit 41 returns to the control state before the power failure. The setting command is a command that indicates the start or end of the setting change state and the setting value after the setting change. When the setting change state is entered, the setting command indicating the start of the setting change state is sent, and when the setting change state ends. A setting command indicating the end of the setting change state and the setting value after the setting change is sent. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it is possible to specify that the control state of the main control unit 41 has been initialized by the setting command indicating the start of the setting. .. The setting confirmation command is a command that indicates the start or end of the setting confirmation state. When the setting confirmation state is entered, the setting confirmation command that indicates the start of the setting confirmation is sent, and the setting that indicates the end of the setting confirmation is sent when the setting confirmation state ends. A confirmation command is sent.

The door command is a command indicating the detection state of the door open detection switch 25, that is, ON (open state) / OFF (closed state), and the command queue is empty when a predetermined condition is satisfied (normal time command transmission processing is executed). At some point) it will be sent.

Of these commands, commands other than the door command are generated in the main process, temporarily stored in the command queue provided in the RAM 41c, and then the timer interrupt process (main) normal command transmission process and power failure command transmission. Sent in the process. On the other hand, the door command is generated when no command is stored in the command queue in the normal command transmission process, is temporarily stored in the command queue provided in the RAM 41c, and is transmitted in the normal command transmission process. To.

Next, the control of the effect executed by the sub control unit 91 based on the command transmitted by the main control unit 41 to the sub control unit 91 will be described. When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

In the timer interrupt processing (sub), the sub control unit 91 determines whether or not an unprocessed command is stored in the reception buffer, and if an unprocessed command is stored, the earliest of them. The control pattern table stored in the ROM 91b is referred to based on the command received in the step, and the liquid crystal display 51, the effect LED 52, the speaker 53, 54, the reel LED 55, etc. are referred to based on the control contents registered in the control pattern table. Controls the output of various production devices. In the control pattern table, for each of a plurality of types of effect patterns, a display pattern of the liquid crystal display 51 corresponding to the type of command, a lighting mode of the effect LED 52, an output mode of the speakers 53 and 54, a lighting mode of the reel LED 55, etc. The control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 of the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among them, the control pattern corresponding to the type of the received command is referred to, and the output control of the effect device is performed based on the control pattern. As a result, the effect according to the effect pattern and the progress of the game is executed.

If the sub-control unit 91 receives a new command during the execution of the effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed and uses the newly received command. An effect based on the corresponding control pattern is executed. That is, even if the production is not completed to the end, when a new command is received, the production that was being executed is canceled and a new production is performed unless the new command received is not the command that triggers the new production. The effect based on the command will be executed.

When the internal winning command is received, the effect pattern is selected at a selection rate according to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub-control unit 91 receives the internal winning command, it is stored in the effect table according to the result of the internal lottery indicated by the internal winning command. The registered selection rate is referred to, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Therefore, even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received, and as a result, different effects may be performed depending on the effect pattern.

Further, whether the sub-control unit 91 has changed the detection state of the door open detection switch 25 from OFF (closed state) to ON (open state) based on the detection state of the door open detection switch 25 specified from the door command. When it is determined whether or not the door is open and the state changes from OFF (closed state) to ON (open state), a door opening notification is executed to notify that the front door 1b is being opened.

FIG. 5 is an address map of the memory area used by the main control unit 41. As shown in FIG. 5, the memory area used by the main control unit 41 includes a memory area (0000H to 7FFFH) allocated to the ROM 41b and a memory area (8000H to FFFFH) allocated to the RAM 41c.

The memory area of the ROM 41b includes a program / data area (0000H to 26FFH) in which a program and fixed data are stored, a ROM comment area (2700H to 277FH) in which arbitrary data such as a program title and version can be set, and a later description. Vector table area (2780H to 27A7H) where the upper address of the subroutine of the CALLV instruction and the start address of the timer interrupt processing (main) are set, and parameters for setting the internal functions of the main control unit 41 in terms of hardware. Includes an HW parameter area (27A8H to 27FFH) in which is set and an unused area (2800H to 7FFFH) where access is prohibited.

The memory area of the RAM 41c is an internal function register area (9000H to 81FFH) in which a usable area (8000H to 81FFH) that can be used as a work and a register group for controlling each function mounted on the main control unit 41 are stored. 9080H) and unused areas (8200H to 8FFFH, 9081H to FFFFH) whose access is prohibited.

The parameters set in the HW parameter area in the ROM 41b include the final address (HPRGEND) of the ROM area used in the program / data area, the start address (HRAMSTAT) and the final address (HRAMEND) of the RAM area for which access is prohibited.

FIG. 6 is an address map of the program / data area in the ROM 41b of the main control unit 41 and the usable area in the RAM 41c.

As shown in FIG. 6A, the program / data area in the ROM 41b includes a game program area in which a game program related to the progress of the game is stored, a game data area in which game data used by the game program is stored, and a game data area in which the game data used by the game program is stored. It includes a used area 1, a non-game program area in which a non-game program not related to the progress of a game is stored, a non-game data area in which non-game data used by the non-game program is stored, and an unused area 2. ..

The progress of the game is to proceed with a series of processes constituting the game, and if it is a slot machine, the stage where the number of bets is set and the game can be started, the game is started and the reels are rotated. The stage of causing the reel to be stopped, the stage of deriving the display result, and the stage of giving the value of a medal or the like according to the display result are advanced.

The game program area is allocated to 0000H to 097EH, the game data area is allocated to 097FH to 12FFH, the non-game program area is allocated to 1380H to 1D02H, and the non-game data area is allocated to 1D03H to 267DH. Further, the area (1357H to 137FH) between the game data area and the non-game program area is regarded as the unused area 1, and the area (267EH to 26FFH) after the non-game data area in the program / data area in the ROM 41b is defined as the unused area 1. It is regarded as an unused area 2, and 0 is stored in all areas in the unused areas 1 and 2.

In this way, the game program area related to the progress of the game and the non-game program not related to the progress of the game are separately assigned, and the game program area and the non-program area are rearward in the storage area of ROM 41b. Since the unused area 1 of at least 16 bytes or more is allocated to the area in front of the allocated non-program area, the game program area related to the progress of the game, the non-game program not related to the progress of the game, and the non-game program. Can be easily specified according to the difference in the storage area.

Further, the game program area and the game data area, and the non-game program area and the non-game data area are allotted to continuous areas, while the game program area and the game data area related to the progress of the game and the non-game area not related to the progress of the game. Since the game program and the non-game data area are allocated to areas that are not continuous with an unused area 1 of at least 16 bytes or more in between, the game program area and the game data area related to the progress of the game and the progress of the game The non-game program and the non-game data area, which are not involved, can be easily specified according to the difference in the storage area.

In the above, the front and back of the storage area are the magnitude relations of the address values assigned to the storage area, and the smaller address is the front and the larger address is the rear. Therefore, the storage area allocated after the one storage area corresponds to the storage area having an address value larger than that of the one storage area, and the storage area allocated before the one storage area. , A storage area whose address value is smaller than that of one storage area is applicable.

Further, the game program may be allocated behind the non-game program area, and the unused area may be allocated in front of the game program allocated behind the non-game program area. A game program area related to the progress of the game and a non-game program not related to the progress of the game can be easily specified according to the difference in the storage area.

Further, the game program area and the non-game program area may be allocated to adjacent areas with the unused area 1 in between. Even with such a configuration, the game program area related to the progress of the game and the game program area may be allocated. Non-game programs that are not related to the progress of the game can be easily identified according to the difference in the storage area.

Further, since 0 values are stored in all the unused areas 1 and 2 of the program / data area of the ROM 41b, the game program area and the game data area, the non-game program area and the non-game data, The unused areas 1 and 2 can be easily distinguished, and even when invalid data is stored in the unused areas 1 and 2, it can be easily found.

It should be noted that 1 may be stored in all the unused areas 1 and 2 of the program / data area of the ROM 41b, and even in such a configuration, the game program area, the game data area, and the non-game The program area and non-game data can be easily distinguished from the unused areas 1 and 2, and even when invalid data is stored in the unused areas 1 and 2, it can be easily found. ..

Further, both the game program area and the non-game program area start from an address (0H) in which the lower four digits have the same value when the address is expressed in binary, and the program / data area of ROM 41b. Of these, the game program area related to the progress of the game and the non-game program area not related to the progress of the game can be easily distinguished from other areas.

In addition, both the game program area and the non-game program area not only start from an address having the same 0 in the lower 4 digits when the address is expressed in binary, but also the value in the lower 1 digit when the address is expressed in hexadecimal. Starts from the same 0 address (0H), so the game program area and the non-game program area can be easily distinguished from other areas not only when the address is expressed in binary not only but also when it is expressed in hexadecimal. can do.

In both the game program area and the non-game program area, regardless of whether the address is expressed in binary or hexadecimal, the lower N (N is a natural number of 1 or more) starts from the address having the same value. The game program area and the non-game program area can be easily distinguished from other areas. For example, the value of the lower N (N is a natural number of 1 or more) digits is the same 1. The same effect can be obtained with a configuration starting from the address of.

As shown in FIG. 6B, the usable area of the RAM 41c includes a game RAM area used as a work by the game program, an unused area 3, a non-game RAM area used by the non-game program as a work, and an unused area. 4 and a stack area are included. In this embodiment, the game program and the non-game program share one stack area, but the game stack area in which the game program saves data and the non-game stack area in which the non-game program saves data. And may be individually provided.

The game RAM area is allocated to 8000H to 805BH, the non-game RAM area is allocated to 8070H to 814CH, and the stack area is allocated to 8170H to 81FFH. The area between the game RAM area and the non-game RAM area (805CH to 806FH) and the area between the non-game RAM area and the stack area (814DH to 816FH) are unused areas 3 and 4, respectively, and are unused. In areas 3 and 4, 0 is stored in all areas. Further, of the stack areas, the stack pointers (SP) to 81FFH are used stack areas, and the other stack areas 816FH to SP are unused stack areas. As described above, the game RAM area used by the game program as a work and the non-game RAM area used by the non-game program as a work are allocated to areas that are not continuous with an unused area 3 of at least 16 bytes or more in between.

In this way, the game RAM area and the non-game RAM area are allocated to areas that are not continuous with an unused area 3 of at least 16 bytes or more in between, so that the game RAM area used by the game program related to the progress of the game , The non-game RAM area used by the non-game program not related to the progress of the game can be easily specified according to the difference in the storage area.

In the following, the game program area, the game data area, and the game RAM area may be collectively referred to as a game area, and the non-game program area, the non-game data area, and the non-game RAM area may be collectively referred to as a non-game area. .. Further, the unused area 1, the unused area 2, the unused area 3 and the unused area 4 may be collectively referred to as an unused area.

The main control unit 41 is an area (game program area, game) from the start address (0000H) to the address (267DH) set in HPRGEND in the program / data area of ROM 41b based on the parameters set in the HW parameter area. Access to the data area, unused area 1, non-game program area, non-game data area) is collectively set to allow, and the area between the address (267EH) and 26FFH after the address (267DH) set in HPRGEND. Prohibit access to (unused area 2). Further, based on the parameters set in the HW parameter area, the area from the start address (8000H) of the usable area of the RAM 41c to the area before the address (814DH) set in the HRAM STAT (game RAM area, unused area 3). , Non-gaming RAM area), the address (814DH) set in HRAMSTAT by setting access to the area (stack area) from the address (8170H) after the address (816FH) set in HRAMEND to 81FFH to allow. Access to the area (unused area 4) between the addresses (816FH) set in HRAMEND is set to be prohibited. Access to an area other than the program / data area of ROM 41b and access to an area other than the usable area of RAM 41c are uniformly prohibited.

Then, when the main control unit 41 accesses the unused area 2 between the address (267FH) after the address (267EH) set in HPRGEND and 26FFH in the program / data area of the ROM 41b, the ROM 41b When an area other than the program / data area is accessed, the unused area 4 between the address set in the HRAM STAT (814 DH) and the address set in the HRAM END (816 FH) in the usable area of the RAM 41c. When there is an access to an area other than the usable area of the RAM 41c, it is determined that the access is unauthorized and an illegal access reset is generated. When an illegal access reset occurs, it is controlled to a special error state described later, the progress of the game is disabled, the state shifts to the setting change state, and the setting value is not released until a new setting value is set.

In this way, the main control unit 41 is out of the usable area of the RAM 41c when the access is prohibited from the program / data area of the ROM 41b based on the parameters set in the HW parameter area. When there was access to an area for which access was not set for permission, when there was access to an area other than the program / data area in ROM 41b, there was access to an area other than the usable area in RAM 41c. Occasionally, that is, when there is an access to a memory area that is not accessed in normal operation, an illegal access reset is generated to disable the progress of the game. Therefore, what is an unused area or operation of ROM 41b? Even when an illegal program is stored in an unrelated area, an unused area of the RAM 41c, or the like, it is possible to prevent the illegal program from being executed.

In particular, in this embodiment, the game program area and the non-game program area are allocated to the program / data area of the ROM 41b that is permitted to be accessed by the program, and the game program area is assigned to the front of the non-game program area behind the game program area. An unused area 1 is allocated to the area, and a group of programs / data areas including an area from the start address of the game program area to the final address of the non-game program based on the parameters set in the HW parameter area. While the access to the area (the area from the game program area to the non-game data area) is collectively set to allow, the other areas, that is, the game program, the game data, and the non-game program among the program / data areas, Since access to the area after the non-game data in which the non-game data is not stored is prohibited, it is possible to prevent unintended control by a malicious program or illegal data.

Further, in the program / data area of the ROM 41b that is permitted to be accessed by the program, the game area is allocated behind the non-game program area, and the unused area is in front of the game program area behind the non-game program area. Is assigned, and access to a group of areas including the area from the start address of the non-game program area to the final address of the game program in the program / data area is collectively based on the parameters set in the HW parameter area. Even if access to other areas is prohibited while setting the permission, it is possible to prevent unintended control by malicious programs and malicious data.

In this embodiment, a group of areas (game program) including an area from the start address of the game program area to the final address of the non-game program in the program / data area based on the parameters set in the HW parameter area. Access to the area from the area to the non-game data area) is collectively set to allow, but the game program area and the non-game program area are assigned to the program / data area, and the game program area is used. Unused area 1 is allocated to the area in front of the non-game program area behind, and a group of program / data areas including the game program area (area from the game program area to the game data area) and non-game area. Access to a group of areas including the game program (area from the non-game program area to the non-game data area) may be set to allow, and access to other areas may be prohibited. Such a configuration. Even in this case, access to the program / data area where the game program or non-game program is not stored is prohibited, so that it is possible to prevent unintended control by the malicious program or the illegal data. .. Further, in the program / data area of the ROM 41b that is permitted to be accessed by the program, the game area is allocated behind the non-game program area, and the unused area is in front of the game program area behind the non-game program area. Is assigned, and a group of areas including the game program area (the area from the game program area to the game data area) and a group of areas including the non-game program (from the non-game program area to the non-game area) in the program / data area. Access to each of the areas up to the data area) may be set to allow and access to other areas may be prohibited. Even with such a configuration, game programs and non-games in the program / data area may be set. Since access to the area where the program is not stored is prohibited, it is possible to prevent unintended control by malicious programs and malicious data.

Further, in the above, the configuration is such that the area itself that allows access in the program / data area is set, but by setting the area that prohibits access in the program / data area, the area that indirectly permits access is set. It may be configured to be performed.

The main control unit 41 is based on the parameters set in the HW parameter area, and is an area (game) from the address (0000H) set in IATSTAT1 to the address (097EH) set in IATEND1 in the program / data area of ROM 41b. The program area), the area (non-gaming program area) from the address (1380H) set in IATSTART2 to the address (1D02H) set in IATEND2 is set as a designated area in which the IAT circuit 506a permits program running.

Then, the IAT circuit 506a is set in the area (game program area) from the address (0000H) set in IATSTAT1 to the address (097EH) set in IATEND1, and from the address (1380H) set in IATSTAT2 to IATEND2. Area up to the address (1D02H) (non-game program area), that is, an area other than the designated area where program running is permitted (game data area, non-game data area, unused area 1 and 2 in the program / data area of ROM 41b). , An area other than the program / data area of ROM 41b), the IAT generation signal is output when the user program is executed. Then, when the IAT generation signal is output, the CPU 41a is controlled to a special error state described later, the progress of the game is disabled, the setting shifts to the setting change state, and until a new setting value is set. It is designed not to be released.

In this way, the main control unit 41 executes the user program when the user program is executed in an area other than the designated area where the program running is permitted based on the parameters set in the HW parameter area, that is, in normal operation. When the user program is executed in a non-existent area, the IAT circuit 506a outputs an IAT generation signal to disable the progress of the game. Therefore, an unused area of the ROM 41b or an area unrelated to the operation. Even when an illegal program is stored in an unused area or the like of the RAM 41c, it is possible to prevent the illegal program from being executed.

In particular, in this embodiment, the game program area and the non-game program area are allocated to the program / data area of the ROM 41b that is permitted to be accessed by the program, and the game program area is assigned to the front of the non-game program area behind the game program area. The unused area 1 is assigned to the area, and the IAT circuit 506a permits the program running for each of the game program area and the non-game program area in the program / data area based on the parameters set in the HW parameter area. While it is set as a designated area, program running is prohibited in other areas, that is, in the program / data area where game programs and non-game programs are not stored, so it is not intended due to malicious programs or illegal data. It is possible to prevent control from being performed.

Further, in the program / data area of the ROM 41b that is permitted to be accessed by the program, the game area is allocated behind the non-game program area, and the unused area is in front of the game program area behind the non-game program area. Is assigned, and based on the parameters set in the HW parameter area, the IAT circuit 506a sets each of the game program area and the non-game program area of the program / data area as designated areas for permitting program running. Therefore, even if the program running in other areas is prohibited, it is possible to prevent unintended control due to an illegal program or illegal data.

In this embodiment, each of the game program area and the non-game program area of the program / data area is set as a designated area where the IAT circuit 506a permits program running based on the parameters set in the HW parameter area. However, the program / data area is allocated to the game program area and the non-game program area, and the unused area 1 is allocated to the area behind the game program area and before the non-game program area. , A group of areas (from the game program area to the non-game data area) including the area from the start address of the game program area to the final address of the non-game program in the program / data area based on the parameters set in the HW parameter area. The area up to) may be collectively set as a designated area where the IAT circuit 506a permits program running, and program running in other areas may be prohibited. Even in such a configuration, the program may be used. / Since program running is prohibited in the area of the data area where the game program and the non-game program are not stored, it is possible to prevent unintended control by the malicious program or the illegal data. Further, in the program / data area of the ROM 41b that is permitted to be accessed by the program, the game area is allocated behind the non-game program area, and the unused area is in front of the game program area behind the non-game program area. Is assigned, and based on the parameters set in the HW parameter area, a group of areas (from the game program area) including the area from the start address of the non-game program area to the final address of the game program in the program / data area. Even if the IAT circuit 506a collectively sets the area up to the non-game data area as a designated area that allows program running and program running in other areas is prohibited, it is due to an illegal program or illegal data. It is possible to prevent unintended control from being performed.

Further, in the above, the area itself that allows the program running is set in the program / data area, but the program running is indirectly permitted by setting the area that prohibits the program running in the program / data area. The configuration may be such that an area is set.

The program executed by the main control unit 41 includes a main routine that manages the progress of the entire program and a subroutine that is called during the execution of another program.

Further, as an instruction for causing the main control unit 41 to execute the program stored in the program / data area, a CALL instruction, an RST instruction, and a jump instruction are included.

The CALL instruction is an instruction that calls and executes a subroutine stored at an address specified in the main routine or the subroutine. When the subroutine is called by the CALL instruction, the main control unit 41 stores the address of the caller in the stack area, and calls and executes the subroutine stored in the designated address. Then, after the subroutine is completed, the address of the caller stored in the stack area, that is, the main routine or subroutine of the caller who executed the CALL instruction is returned.

Further, the CALL instruction includes a normal CALL instruction and a CALLV instruction which is a special CALL instruction. The normal CALL instruction is an instruction that calls a subroutine by specifying both the upper address and the lower address and specifying the address by the specified upper address and lower address, whereas the CALLV instruction specifies only the lower address. By doing so, it is an instruction to specify an address by a preset upper address and a specified lower address in the vector table area of ROM 41b and call the subroutine, and call the subroutine with a smaller amount of data than a normal CALL instruction. It becomes possible.

The RST instruction is an instruction to call and execute a subroutine stored in a specific address corresponding to a specified value by designating a value corresponding to a plurality of predetermined specific addresses, and is an instruction to execute the above-mentioned ordinary CALL. It is possible to call a subroutine with a smaller amount of data than an instruction or a CALLV instruction. When the subroutine is called by the RST instruction, the main control unit 41 stores the address of the caller in the stack area, and calls and executes the subroutine stored in the specific address corresponding to the specified value. Then, after the subroutine is completed, the address of the caller stored in the stack area, that is, the main routine or subroutine of the caller who executed the RST instruction is returned.

A jump instruction is an instruction to move to a program stored at an address specified in a main routine or a subroutine. The main control unit 41 moves to the program stored at the address specified by the jump instruction, and executes the destination program. In this case, unlike the CALL instruction and the RST instruction, the program does not return to the source program even if the program after the transfer ends.

Further, the main control unit 41 includes an LD instruction as an instruction for reading the data stored in the program / data area. The LD instruction is an instruction to read the data stored at the address specified in the main routine or the subroutine into the specified register. The main control unit 41 reads the data stored at the address specified by the LD instruction, and stores the read data in the register specified by the LD instruction.

Of the game programs stored in the ROM 41b, the frequently used subroutines are stored in the game program area of the ROM 41b where the start address is a specific value (for example, 00H). On the other hand, in the vector table area of the ROM 41b, a specific value is set as the upper address of the subroutine called by the CALLV instruction. Then, when the main control unit 41 calls a subroutine in which the upper address of the start address is a specific value, the main control unit 41 uses the CALLV instruction to specify only the lower address, thereby setting the specific value set in the vector table area as the upper address. Specify, specify the lower address specified as the lower address, and call and execute the subroutine stored in the address that combines the upper and lower levels. For this reason, the upper addresses that form part of the addresses used when calling the subroutines that are used particularly frequently in the game program are set in advance as specific values in the vector table, and are based on the specific values set in the vector table. Because the address is specified, it is possible to call a subroutine with a smaller amount of data than a normal CALL instruction that calls a program by specifying both the upper address and the lower address, and when calling these subroutines. It is possible to reduce the waste of the program for specifying the address.

The subroutines that are particularly frequently used among the non-game programs stored in the ROM 41b are stored in the non-game program area of the ROM 41b where the start address is a specific value, and the CALLV instruction is given in the vector table area of the ROM 41b. By setting a specific value as the upper address of the subroutine to be called in, and when the main control unit 41 calls the subroutine in which the upper address of the start address is the specific value, these subroutines are specified by using the CALLV instruction to specify only the lower address. Even if the configuration is such that the program is called and executed, it is possible to call the subroutine with a smaller amount of data than the normal CALL instruction that calls the program by specifying both the upper address and the lower address, and these subroutines can be called. It is possible to reduce the waste of the program for specifying the address when calling.

Further, the upper address used when calling by the CALLV instruction may be set to a specific register of the main control unit 41 instead of the vector table area.

Further, not limited to the CALLV instruction, a part of the address is specified by using the value stored in the vector table area, the value set in the specific register, etc., and the subroutine is specified by specifying the remaining part of the address. If the configuration uses a special CALL instruction that enables the storage address of the subroutine to be specified, it is possible to reduce the waste of the program for specifying the address when calling the subroutine. In addition, identification values with a smaller amount of data than the addresses are assigned to each of the multiple areas that make up the vector table area, and the storage addresses of the subroutines are set in each of these multiple areas, and the identification values are specified to identify them. Even with a configuration that uses a special CALL instruction that makes it possible to specify the storage address of the subroutine stored in the area corresponding to the value, it is possible to reduce the waste of the program for specifying the address when calling the subroutine. ..

Further, the game data that is particularly frequently used among the game data stored in the ROM 41b is stored in the area where the start address is a specific value in the game data area of the ROM 41b, and a special LD is stored in the vector table area of the ROM 41b. By setting a specific value as the upper address of the data to be read by the command, and when the main control unit 41 calls the game data in which the upper address of the start address is the specific value, only the lower address is specified by using a special LD command. , Even if the configuration is such that these game data are read, it is possible to call the game data with a smaller amount of data as compared with the normal LD instruction that reads data by specifying both the upper address and the lower address. It is possible to reduce the waste of the program for specifying the address when reading the game data of.

In addition, the non-game data that is particularly frequently used among the non-game data stored in the ROM 41b is stored in the non-game data area of the ROM 41b where the start address is a specific value, and is stored in the vector table area of the ROM 41b. When a specific value is set as the upper address of the data to be read by the special LD instruction and the main control unit 41 calls the non-game data in which the upper address of the start address is the specific value, only the lower address is used by the special LD instruction. By specifying, even if the configuration is such that these non-game data are read, the non-game data is called with a smaller amount of data than the normal LD instruction that reads data by specifying both the upper address and the lower address. This makes it possible to reduce the waste of the program for specifying an address when reading these non-game data.

Further, even in these cases, the upper address used when calling with a special LD instruction may be set to a specific register of the main control unit 41 instead of the vector table area.

In addition, a part of the address is specified using the value stored in the vector table area, the value set in a specific register, etc., and the data storage address can be specified by specifying the remaining part of the address. If the configuration uses the special LD instruction, it is possible to reduce the waste of the program for specifying the address when reading the data. In addition, identification values that are smaller than the address are assigned to each of the multiple areas that make up the vector table area, data storage addresses are set in each of these multiple areas, and identification values are specified. Even in a configuration using a special LD instruction that makes it possible to specify the storage address of the data stored in the area corresponding to the value, it is possible to reduce the waste of the program for specifying the address when reading the data. ..

Further, the main control unit 41 is activated when a system reset by inputting a system reset signal, a WDT reset by WDT506b, and the above-mentioned illegal access reset occur. At this time, the value set in the vector table area is set. Is a value indicating the area of the address set in 0000H to HPRGEND, that is, the area of the program area in which the program or the like is actually stored, or FFFFH (value set in the unused vector table area). It is determined whether or not there is, and if the value set in the vector table area is neither a value indicating the area of the address set in 0000H to HPRGEND nor FFFFH, it is not started.

In this way, the main control unit 41 indicates that the value set in the vector table area, that is, the upper address of the subroutine of the CALLV instruction described later and the start address of the timer interrupt process (main) is outside the area in which the program is set. By not starting when it is a value, it is possible to prevent in advance that an unintended process is executed due to an interruption or the like.

FIG. 7 is an address map of the game program area in the program / data area of the ROM 41b of the main control unit 41.

As shown in FIG. 7, the game program area of the ROM 41b is an area having an address of 0000H to 097EH, and the area from 0000H to 003FH (hereinafter, may be referred to as a specific address area) in this area is an address. Addresses every 8 bytes (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H) in which the lower one digit of is a specific value (8H or 0H) are assigned as specific addresses.

In the game program area, as game programs related to the progress of the game, for example, initial setting processing, external signal off time waiting processing, maximum number of inserted medals set processing, output port 2 output processing, set value display data acquisition processing, addition processing , All reel stop LED off processing, interrupt 1 time waiting processing, interrupt BC times waiting processing, hopper stop processing, port output processing, game state determination processing, game counter transmission processing, command storage processing, etc. are stored. There is.

The initial setting process is a process of returning the control state of the main control unit 41 to a state in which the game can proceed when returning from the power interruption, and the external signal off time waiting process is a process of returning from the ON state when the external output signal is output. It is a process of waiting until the time until switching to the OFF state elapses, and the maximum number of inserted medals set process is a process of setting the maximum number of inserted medals used in the game (three in this embodiment) and outputs. The port 2 output process is a process of outputting a signal indicating the excitation state of the flow path switching solenoid 30 from the output port according to the progress of the game, and the set value display data acquisition process is a set value display 24. Is a process of acquiring display data for displaying, and the addition process is a process of adding a predetermined value to a specified parameter and acquiring address data based on the added value, and is an all-reel stop LED off process. Is a process of setting the port output so that the left middle right stop effective LEDs 22L, 22C, and 22R are turned off, and the interrupt one-time wait process is a process of waiting until the interrupt process is performed once. The interrupt BC times wait process is a process of waiting until a specified number of interrupt processes are performed, and the hopper stop process is a process of setting a port output so as to turn off the hopper motor 34b. The port output process is a process of outputting a signal based on the port output setting performed in each process, and the game state determination process acquires the game state and sets a flag indicating the game state in the RAM 41c. The game counter transmission process is a process for setting the value of the game counter to be transmitted as a command, and the command storage process is a process for storing a command in the command queue.

Among the game programs stored in the ROM 41b, some of the above-mentioned frequently used subroutines are stored in the above-mentioned specific address in the game program area of the ROM 41b. In this embodiment, among the game programs, a plurality of external signal off-time wait processes, output port 2 output processes, addition processes, interrupt 1 wait process, interrupt BC wait process, port output process, and game state determination process are performed. The specific address of one of the specific addresses is stored in the ROM 41b at the beginning.

Specifically, the external signal off-time wait processing starts with the specific address 0008H, the output port 2 output process starts with the specific address 0010H, and the addition process starts with the specific address 0018H and waits once for interruption. The process starts with the specific address 0020H, the interrupt BC wait process starts with the specific address 0028H, the port output process starts with the specific address 0030H, and the game state determination process starts with the specific address 0038H. It is stored in a specific address area.

In the specific address area, the area from one specific address to the front of the next specific address is 8 bytes, and when a subroutine exceeding 8 bytes is stored with the specific address at the beginning, the subroutine is a plurality of areas. It is divided and stored in. In this embodiment, the port output process of the subroutine stored at the specific address is composed of a data amount exceeding 8 bytes, and the first 8 bytes of the subroutine starts with the specific address (0030H) and is next. While it is stored in the area (0030H to 0037H) before the specific address (0038H), the portion exceeding 8 bytes is stored in the area other than the specific address area (area starting with 0289H) in the game program area. To. In addition, the first 8-byte part of the port output process includes a jump instruction that moves to the specified address and executes the program stored at that address, and the first 8-byte part starting from the specific address. By executing, the part exceeding 8 bytes stored outside the specific address area is also executed integrally. The jump instruction is an instruction to call and execute a program stored in the specified address by designating a 2-byte address.

In this way, the subroutine with the amount of data exceeding 8 bytes is divided into the first 8-byte part and the subsequent part, and the first 8-byte part is stored in the area starting from the specific address, and the latter part is stored. By storing it outside the specific address area and providing a jump instruction to move to the subsequent part in the first 8-byte part, even a subroutine with a data amount exceeding 8 bytes can be specified without being passed to multiple specific addresses. It can be stored in the area starting with the address.

In this embodiment, when a subroutine of less than 8 bytes is stored starting from a specific address in a specific address area, the area after the subroutine stored in the specific address to before the next specific address is used. Subroutine is stored.

Specifically, a 3-byte area from after the external signal off-time waiting process (000 DH) to before the next specific address (000 FH), that is, between the external signal off-time wait process and the output port 2 output process. In the area, the maximum number of inserted medals set processing composed of 3 bytes of data is stored, and the subroutine is applied to all the areas from the specific address where the external signal off time waiting process is stored to before the next specific address. Data is stored.

Further, in the area of 3 bytes from after the output port 2 output process (0015H) to before the next specific address (0017H), that is, in the area between the output port 2 output process and the addition process, 3 bytes of data The setting value display data acquisition process composed of the amount is stored, and the subroutine data is stored in the entire area from the specific address where the output port 2 output process is stored to before the next specific address. ing.

Further, in the area of 5 bytes from after the addition process (001BH) to before the next specific address (001FH), that is, in the area between the addition process and the interrupt one-time wait process, the amount of data is 5 bytes. The configured all-reel stop LED off process is stored, and the subroutine data is stored in the entire area from the specific address where the addition process is stored to before the next specific address.

Further, the area of 3 bytes from after the interrupt BC wait process (002DH) to before the next specific address (002FH), that is, the area between the interrupt BC wait process and the port output process is 3 The hopper stop process consisting of the amount of byte data is stored, and the subroutine data is stored in the entire area from the specific address where the interrupt BC wait process is stored to before the next specific address. It has become.

Further, the 2-byte area from after the game state determination process (003EH) to the end address (003FH) of the specific address area, that is, the area between the game state determination process and the command storage process, has a 2-byte amount of data. The game counter transmission process composed of is stored, and the data of the subroutine is stored in the entire area from the specific address where the game state determination process is stored to the end of the specific address area.

In this way, by storing the subroutine or a part of the data amount corresponding to the area in the subroutine stored in the area starting from the specific address and the remaining area before the next specific address, Subroutine data is stored in the entire area from the specific address to the area before the next specific address.

In this embodiment, of the subroutines stored in the area starting from the specific address and the subroutines stored in the remaining area before the next specific address, the setting value display data acquisition process is executed. In this case, the addition process is continuously executed, and the addition process subroutine is stored after the set value display data acquisition process subroutine in the game program area. Further, the hopper stop process is a process in which the port process is continuously executed when the subroutine is executed, and the port process subroutine is stored after the hopper stop process subroutine in the game program area. Further, the game counter transmission process is a process in which the command storage process is continuously executed when the subroutine is executed, and the command storage process subroutine is stored after the game counter transmission process subroutine in the game program area. Has been done.

Further, among the subroutines stored in the area starting from the specific address and the subroutines stored in the remaining area before the next specific address, the all reel stop LED off processing is performed when the processing is executed. , A process in which port processing is continuously executed, and includes a jump instruction for designating an address in which port processing is stored and moving to that address.

In this embodiment, the subroutine stored in the area starting from the specific address and the remaining area before the next specific address are the data of the subroutine composed of the amount of data corresponding to the remaining area. By storing, the subroutine data is stored in the entire area from one specific address to the next specific address, but before the subroutine stored in the area starting from the specific address and the next specific address. In the remaining area up to, the data of the predetermined subroutine composed of a larger amount of data than the remaining area may be stored. In such a configuration, the predetermined subroutine is stored in the remaining area. The first part is divided into a second part stored at a predetermined address of the game program area outside the specific address area, and the first part is divided into the remaining area including a jump command to move to the predetermined address. By storing the corresponding amount of data in the free area and storing the second part at a predetermined address outside the specific address area, the data is larger than the area sandwiched between the subroutines stored in the area starting from the specific address. By using a part of the subroutine of quantity, the data of the subroutine can be stored in the entire area from the specific address to the front of the next specific address.

The main control unit 41 of this embodiment includes a 1-byte RST instruction capable of calling a subroutine by designating a specific address. The operation code of the RST instruction is composed of 8 bits (1 byte), and the values of the 1st bit to the 3rd bit and the 5th bit to the 8th bit are always set to "1", while the 3rd bit. By designating each value of the 5th bit to a predetermined value, a specific address corresponding to the combination of the predetermined 3-bit "0" and "1" is specified, and the specified specific address is designated. It is possible to call the subroutine stored as the beginning. Specifically, eight addresses of 0000H, 0008H, 0010H, 0018H, 0020H, 0028H, 0030H, and 0038H are assigned as specific addresses that can be specified by the RST instruction, and the third bit to the operation code of the RST instruction is assigned. By specifying the 5th bit as "000", the specific address 0000H is specified, by specifying "001", the specific address 0008H is specified, and by specifying "010", the specific address 0010H is specified. By specifying "011", the specific address 0018H is specified, by specifying "100", the specific address 0020H is specified, and by specifying "101", the specific address 0028H is specified, and "110" is specified. By doing so, the specific address 0030H is specified, and by specifying "111", the specific address 0038H is specified. Then, the subroutine starting with the specified specific address is called.

The address in the ROM 41b has a 2-byte structure, whereas the parameter (operand) for specifying the specific address by the RST instruction is 3 bits of the 3rd bit to the 5th bit. That is, the RST instruction specifies a specific address corresponding to the specified parameter among a plurality of specific addresses assigned at predetermined intervals by specifying a parameter having a data amount smaller than the program address in the ROM 41b. Since the subroutine stored in the specified specific address can be called, the program capacity related to the program call can be reduced. Further, the operation code of the RST instruction as a whole is composed of 1 byte and is composed of a smaller amount of data than the program address of the 2-byte configuration, so that the operation code of the program is called by specifying the program address. Since it is possible to call a program stored at a specific address with a small amount of data, the program capacity for calling the program can be reduced.

As described above, the ROM 41b of the main control unit 41 of the present embodiment is assigned a 2-byte address capable of specifying the storage area in which the program is stored, and the storage area having an address of 0000H to 003FH is assigned. Addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H) in which the lower one digit of the address is a specific value (8H or 0H) are assigned as specific addresses. In addition, the main control unit 41 specifies a 2-byte address, moves to a program at the specified address and executes the program, and specifies and specifies a specific address with 3-bit data shorter than the address. It is equipped with a 1-byte RST instruction that can call a program at a specific address and execute the program. In such a configuration, when a program having a data amount smaller than the area between specific addresses, that is, less than 8 bytes, is stored in the specific address, the subroutine stored in the area starting from the specific address and the next A free area may be generated in the area before the specific address, and the storage area of the ROM 41b has not been effectively used.

On the other hand, in this embodiment, the first specific program, for example, the subroutine of waiting for the external signal off time is stored in the area starting from one specific address, and the second is stored in the area starting from the next specific address. Specific program, for example, the output port 2 output processing subroutine is stored, and the area from after the first specific program to before the next specific address, that is, of the first specific program and the second specific program. By storing a predetermined program or a part of the predetermined program, for example, a subroutine of the maximum number of inserted medals set processing that matches the data amount of the free area, in the free area between them. The data of the subroutine is stored in the area from the specific address of the above to the area before the next specific address, and the area of the ROM 41b can be effectively used.

The predetermined program stored in the free area between the first specific program and the second specific program may be a program having a data amount smaller than the free area of the area, or may be stored in the free area. A program having the same amount of data may be used, and in any configuration, the predetermined program is stored in the free area between the first specific program and the second specific program, so that the area of ROM 41b can be occupied. It can be used effectively.

Further, in the present embodiment, one type of subroutine is stored in the free area between the first specific program and the second specific program, but the first specific program and the second specific program are used. Multiple types of subroutines, that is, multiple programs may be stored in the free area between them. Even in such a configuration, the subroutines may be stored in the area from one specific address to the area before the next specific address. The data will be stored, and the area of the ROM 41b can be effectively used.

In this embodiment, in the free area between the first specific program and the second specific program, as a predetermined program, a program in which the second specific program is continuously executed after the predetermined program (for example, after the end). By storing the set value display data acquisition process subroutine) that continuously executes the addition process, the main control unit 41 performs the first program (set value display data acquisition process subroutine) stored in the free area. The second specific program (subscription of addition processing) is executed, and the second specific program is executed after the predetermined program is completed only by calling the predetermined program stored in the free area by the CALLV instruction. Therefore, it is not necessary to call the second specific program by the RST instruction in the program stored in the free area, and the program capacity for calling the second specific program can be reduced.

Further, in the present embodiment, the free area between the first specific program and the second specific program is configured to store a predetermined program having a data amount equal to or less than the free area. In the free area between the specific program and the second specific program, a program including a part of a program having a data amount larger than the free area as a predetermined program and a jump instruction to move to an area other than the free area is provided. In addition to being stored, the remaining part of the program may be stored in a predetermined area specified by a jump instruction. With such a configuration, between the first specific program and the second specific program. Since a part of the program having a data amount larger than the free area can be stored in the free area, the storage area of the ROM 41b can be effectively used without being emptied. The area in which the remaining part of the predetermined program is stored may be a specific address area or an area outside the specific address area.

Further, in this embodiment, as a specific program to be stored in the area starting from the specific address, one of the programs (for example, a subroutine of port output processing) having a larger amount of data than the area from the specific address to the area before the next specific address. An area that starts from a specific address by an RST command by storing a program that includes a part and a jump command that moves to an area other than the area, and storing the remaining part of the program in an area other than the area. Since a part of the specific program stored in is executed and the rest is executed by the jump instruction, the program has a larger amount of data than the area from the specific address to the front of the next specific address. However, since the program can be specified and executed by the RST instruction, the program capacity for calling such a program having a large amount of data can be reduced. The remaining part of the specific program is stored in an area outside the specific address area, but may be stored in an area inside the specific address area.

As described above, the game program is a program related to the progress of the game, and is a program for executing a process that hinders the progress of the game unless the process based on the program is executed.

On the other hand, the non-game program is a program that is not related to the progress of the game as described above, and even if it is called from the game program and returns to the game program without executing the process based on the program, the game is progressed. It is a program for executing possible processing.

As shown in FIG. 8, the game program includes a game-dedicated program included only in the game program, and a common determination program and a common general-purpose program included in both the game program and the non-game program.

The game-dedicated program includes, for example, a BET process, an internal lottery process, a reel rotation process, a payout process, and an external output 1 process. The BET process is a process for starting the game by operating the start switch 7 after setting the number of bets by inserting medals or the like after the control of one game is completed and setting the specified number of bets. The internal lottery process is a process of performing an internal lottery and setting a winning flag, and the reel rotation process is a process of starting the rotation of the reel and operating the stop switches 8L, 8C, and 8R to operate the reel. This is a process for stopping the game, and the payout process is for determining whether or not a prize has been generated according to the stop position of the stopped reel, and for paying out medals, setting a re-game, shifting the game state, and the like. The external output 1 process is a process for controlling the output of the medal IN signal, the medal OUT signal, the RB signal, the BB signal, and the RT signal among the external output signals. Further, although not particularly shown, the game program also includes the above-mentioned processing related to AT (control related to lottery related to AT, control related to navigation notification, etc.), and the above-mentioned processing for transmitting the internal winning command.

The common determination program in the game program includes, for example, input determination processing and payout determination processing. The insertion determination process is a process of determining whether or not the medal has passed normally by the insertion medal sensor 31, and is a process executed in a state where medals can be inserted for setting the number of bets and the like. The payout determination process is a process of determining whether or not the medal has passed normally by the payout sensor 34c, and is a process executed in a state where the medal payout is permitted at the time of winning a small winning combination or at the time of credit settlement. Is.

The common general-purpose program in the game program is a process called and executed from a plurality of types of processes constituting the game program. For example, counter update process, port input process, data conversion process, LED display process, data setting process, etc. Includes command setting processing. The counter update process is a process for updating the specified counter value, the port input process is a process for acquiring the input state of the specified port, and the data conversion process is input using game data. It is a process of converting and outputting the data, the LED display process is a process of setting to display the specified value on the LED, and the data setting process is a process of setting the specified data. The command setting process is a process of setting a specified command in the command queue. In addition, the above-mentioned initial setting processing, external signal off time waiting processing, maximum number of inserted medals set processing, output port 2 output processing, set value display data acquisition processing, addition processing, all reel stop LED off processing, interrupt once waiting The common general-purpose program also includes processing, interrupt BC waiting processing, hopper stop processing, port output processing, game state determination processing, game counter transmission processing, and command storage processing.

As shown in FIG. 8, the non-game program includes a non-game dedicated program included only in the non-game program, and the same common determination program and common general-purpose program as the game program.

The non-game dedicated program is, for example, test signal output processing, foreign matter detection processing, door monitoring processing, external output 2 processing, input medal error judgment processing, payout medal error judgment processing, random number abnormality confirmation processing, RAM abnormality confirmation processing, backup abnormality. Includes confirmation processing, register initialization processing, setting value abnormality confirmation processing, and error processing. The test signal output process is a process for outputting a test signal generated in connection with the result of the game, and the foreign object detection process is a process for detecting a foreign object in the medal passage by the slot sensor 26. The door monitoring process is a process for detecting the opening of the front door 1b, and the external output 2 process is a security signal (door opening signal, setting change signal, closing error signal, payout error signal) among the external output signals. It is a process for performing output control, and the inserted medal error determination process detects backflow of inserted medals, detection of medal clogging in the medal selector 29, and detection of foreign matter in the medal selector 29 based on the detection status of the inserted medal sensor 31. The payout medal error determination process is a process for detecting backflow of payout medals, medal clogging detection near the payout exit, and foreign matter detection near the payout exit based on the detection status of the payout sensor 34c. The random number abnormality confirmation process is a process for confirming whether the random number circuit is operating normally, and the RAM abnormality confirmation process and the backup abnormality confirmation process are processes for confirming whether the data stored in the RAM 41c is abnormal. The register initialization process is a process for initializing various registers of the main control unit 41, and the set value abnormality confirmation process is a process for determining whether or not the set value is within a normal range. The error processing includes various abnormalities (medal insertion abnormality, foreign matter detection in the medal selector 29, reel rotation abnormality, medal payout abnormality, foreign matter detection near the payout outlet, RAM abnormality, set value abnormality, hopper tank 34a. This is a process for disabling the game when an empty, full tank detection of the overflow tank 35, etc. is detected.

The common general-purpose program in the non-game program is a process called and executed from a plurality of types of processes constituting the non-game program, and like the common general-purpose program in the game program, for example, counter update process, port input process, and so on. Includes data conversion processing, LED display processing, data setting processing, and command setting processing.

In particular, in the non-game program, when an abnormality is detected as described above, the release condition according to the type of abnormality (random number abnormality, RAM abnormality, backup abnormality, setting value abnormality, resetting the setting value, In the case of other abnormalities, it includes error processing that disables the progress of the game until the reset operation) is established.

In addition, the non-game program includes a process of determining whether or not the detection status is a predetermined status based on the detection status of the detection means (input port sensor 26, full tank sensor 35a, door open detection switch 25) not related to the progress of the game. ..

In addition, the non-game program functions as a detection means related to the progress of the game in a specific control state among a plurality of control states (BET process, internal lottery process, reel rotation process, payout process), and other control states. In the above, is the detection means (for example, the insertion medal sensor 31 and the payout sensor 34c) that functions as the detection means that is not related to the progress of the game a predetermined detection status based on the detection status in the control state that is not related to the progress of the game? It includes a process of determining whether or not a medal is inserted (for example, a process of detecting a inserted medal or a process of detecting a payout medal for detecting an abnormality caused by detecting the insertion of a medal during reel rotation or the withdrawal of a medal). It should be noted that such a determination process corresponds to a common determination program because it is the same process as the process of determining whether or not the detection status is a predetermined detection status based on the detection status in the control state related to the progress of the game in the game program. ..

Among the processes included in the game program, the external output 1 process, the process of counting the number of medals inserted in the BET process, the process of switching the flow path switching solenoid 30, the process of counting the number of medals paid out in the payout process, and the hopper. If the process is not directly related to the progress of the game, such as the process of detecting that the tank 34a is empty, the process of updating the software random number, the process related to AT, the process of sending the internal winning command, etc. The configuration may include all or part of the processing in the non-game program. On the other hand, among the processes included in the non-game program, if the processes are indirectly related to the progress of the game, such as the activation process and the setting value abnormality confirmation process, all or part of these processes are included in the game program. It may be.

In this embodiment, as shown in FIG. 9, the CPU 41a of the main control unit 41 calls the non-game program in the process based on the game program to execute the process based on the non-game program, and after the process based on the non-game program is completed. , Return to the process based on the game program.

As shown in FIG. 10, when the non-game program is called from the processing based on the game program, the CPU 41a first of the non-game program, the arithmetic registers (A, F, BC, DE,) used by the CPU 41a for the calculation. All the values of the HL register, hereinafter, the register for calculation is simply referred to as a register) are saved in the stack area, and the data used by the game program is protected. Then, after all the processing based on the non-game program is completed, the value saved in the stack area is returned to the register, and then the processing based on the game program is returned.

In this embodiment, the register values used by the game program are protected by saving them in the stack area, but the game program uses them by changing the values of the front register and the back register. It may be configured to protect the value of the register.

Further, in this embodiment, when the non-game program is called from the process based on the game program, the value of the register used by the game program is protected at the beginning of the non-game program, and at the end of the non-game program, The configuration is to restore the protected register value, but the register value used by the game program immediately before calling the non-game program from the process based on the game program is protected, and all the processes based on the non-game program are performed. After the end, when the non-game program is called from the processing based on the game program, the configuration that restores the value of the protected register at the first stage of returning to the game program, the game program is at the beginning of the non-game program. From the configuration based on the game program, the configuration that protects the value of the register used and restores the value of the protected register at the first stage of returning to the game program after all the processing based on the non-game program is completed. The value of the register used by the game program immediately before calling the non-game program may be protected, and the value of the protected register may be restored at the end of the non-game program.

As shown in FIG. 9, in principle, when executing the process based on the game program, the CPU 41a executes the process based on the game program with reference to the game data in the game data area, and uses the game RAM area as a work. , It is possible to refer to and update the contents of the game RAM area. Further, in principle, when executing the process based on the non-game program, the CPU 41a executes the process based on the non-game program with reference to the game data in the non-game data area, and uses the non-game RAM area as a work. It is possible to refer to and update the contents of the non-gaming RAM area.

Further, the CPU 41a does not refer to the non-game data area and does not update the non-game RAM area when executing the process based on the game program, but it is possible to refer to the non-game RAM area. , In executing the process based on the non-game program, the game data area is not referred to and the game RAM area is not updated, but the game RAM area can be referred to.

Further, the processing based on the game program can refer only to a specific area (for example, an error flag setting area indicating abnormality detection) required for the game program in the non-game RAM area, and can be referred to the non-game program. The processing based on the game RAM area can be referred to only a specific area required for the non-game program (for example, an internal winning flag setting area, a game state setting area, an RT setting area, etc.). In addition, a specific area in the non-game RAM area where processing based on the game program can be referred to, and a specific area in the game RAM area where processing based on the non-game program can be referred to may be allocated to continuous address areas. Although it is preferable, the configuration may be such that a part or all of the address area is not contiguous.

However, RAM abnormality confirmation, backup abnormality confirmation, RAM 41c initialization, and power interruption processing described later in the startup processing are included in the non-game program, except for these processing, that the entire area of the RAM 41c can be accessed. Has been done.

As described above, in this embodiment, the game program area in which the game program related to the progress of the game is stored, the game data area in which the game data referred to by the game program is readable, and the work data referred to by the game program are stored. A game RAM area that is readable and writable, a non-game program area that is a program called by the game program and stores non-game programs that are not related to the progress of the game, and a non-game that the non-game program refers to. Since the non-game data area in which the data is readable and stored and the non-game RAM area in which the work data referred to by the non-game program is readable and writable are allocated separately, the game program, The game data and the work data of the game program and the non-game program, the non-game data, and the work data of the non-game program can be easily specified according to the difference in the storage area.

Further, by separating the game program area and the game data area and the non-game program area and the non-game data area, the area occupied by the ROM 41b can be compactly managed according to each function. It will be easier to identify the relevant data.

Further, in the present embodiment, the non-game RAM area can be referred to when the game program is executed, and the game RAM area can be referred to when the non-game program is executed. The data used by the non-game program can be easily used when executing the game program, and the data used by the game program can be easily used when executing the non-game program. On the other hand, it is impossible to update the non-game RAM area when executing the game program, and it is impossible to update the game RAM area when executing the non-game program. Does not affect the processing of the non-game program, and the non-game program does not affect the processing of the game program.

Further, in the present embodiment, the processing based on the game program can refer only to a specific area (for example, an error flag setting area indicating abnormality detection) required for the game program in the non-game RAM area. , The processing based on the non-game program can refer only to a specific area (for example, an internal winning flag setting area, a game state setting area, an RT setting area, etc.) necessary for the non-game program in the game RAM area. Therefore, since the data that the game program can refer to in the non-game RAM area and the data that the non-game program can refer to are limited to a specific area, the reference destination of the game program or the non-game program can be easily specified. be able to.

Further, in the present embodiment, when an abnormality is detected, the non-game program includes an error process that disables the progress of the game until the cancellation condition is satisfied according to the type of the abnormality. Therefore, the process in the non-game program. It is possible to prevent the game from proceeding as it is when an abnormality or the like is detected.

Further, in the present embodiment, since the non-game program includes a common judgment program having the same contents as the common judgment program (for example, input judgment processing, payout judgment processing) included in the game program, the game program and the non-game program are mutually exclusive. The same judgment can be made without affecting the result of.

Further, in the present embodiment, the non-game program is a process called and executed from a plurality of types of processes constituting the non-game program, and includes a common general-purpose program similar to the common general-purpose program included in the game program. , Even if the common general-purpose program has the same processing content, the game program and the non-game program are provided with each other. Therefore, even if the processing content is the same common general-purpose program, is it included in the game program or the non-game program? Can be easily identified.

Further, in the present embodiment, whether or not the non-game program has a predetermined detection status based on the detection status of the detection means (input port sensor 26, full tank sensor 35a, door open detection switch 25) not related to the progress of the game. Since the determination process is included, the game program is not complicated because the determination as to whether or not the predetermined detection is performed by the detection means not related to the progress of the game is performed by the non-game program.

Further, in the present embodiment, the non-game program functions as a detection means related to the progress of the game in a specific control state among a plurality of control states (BET process, internal lottery process, reel rotation process, payout process). In other control states, the detection means (for example, the insertion medal sensor 31 and the payout sensor 34c) that functions as the detection means that is not related to the progress of the game is based on the detection status in the control state that is not related to the progress of the game. Processing for determining whether or not the detection status is predetermined (for example, detection processing for inserted medals and detection processing for paid medals for detecting an abnormality caused by detection of insertion of medals during reel rotation or withdrawal of medals) Therefore, in a situation where the detection result of the detection means as described above is not used for the progress of the game, the detection means is determined by the non-game program whether or not the predetermined detection is performed by the detection means. The detection result of the detection means can be used even in a situation where the detection result of is not used for the progress of the game, and the game program is not complicated more than necessary.

Further, in this embodiment, when the game program calls the non-game program and executes the non-game program, the entire area of the register is protected regardless of whether or not the register is actually used by the game program. Therefore, when returning to the game program, it is possible to reliably return from the state at the time when the non-game program was called.

Further, in the present embodiment, when the non-game program is called from the process based on the game program, the value of the register used by the game program is protected at the beginning of the non-game program, and at the end of the non-game program, Since the value of the protected register is restored, the capacity of the game program can be reduced.

It should be noted that the value of the register used by the game program immediately before calling the non-game program from the process based on the game program is protected, and after all the processes based on the non-game program are completed, at the first stage of returning to the game program. The protected register value may be restored. With such a configuration, the register protection process is performed before calling the non-game program, and the register recovery process is performed after the return from the non-game program. The data stored in the register by the non-game program does not affect the game program.

Next, various control contents executed by the main control unit 41 in this embodiment will be described below with reference to FIGS. 11 to 23.

When the main control unit 41 is activated due to the occurrence of a reset, the main control unit 41 sets at startup. In the startup setting, the status flag provided in the main control unit 41 is initialized. The status flag is data that holds the state of the operation result and the execution result of the instruction, and particularly includes the interrupt master permission flag that sets the prohibition / permission of interrupt. Since the initial value of the interrupt master permission flag is a value indicating the prohibition of interrupts, the main control unit 41 is started in a state where interrupts are prohibited.

After that, the main control unit 41 sets various functions with reference to the HW parameters, and then performs the initial setting process shown in the flowchart of FIG. 11 according to the program stored in the program / data area. In the initial setting process, first, interrupting is prohibited by setting the value of the interrupt master permission flag to a value indicating interrupt prohibition (Sa1). As described above, the main control unit 41 is activated in the interrupt-prohibited state, but in Sa1, interrupts are prohibited again. Next, initialization data is set (Sa2), and each output port including the parallel output port 513 is initialized (Sa3). Next, the built-in register is set (Sa4).

Next, it is determined whether or not the power supply voltage is normal (Sa5). If the power supply voltage is not normal, the determination is repeated until it becomes normal. If the power supply voltage is normal, the upper address of the interrupt vector is set (Sa6). Then, the access to the RAM 41c is permitted (Sa7), and the stack pointer is initialized (Sa8).

Next, the RAM parity (hereinafter referred to as RAM parity 1) of all areas (including unused area 3) of the game RAM area of the RAM 41c and the RAM of all areas (including unused area 4) of the non-game RAM area. The parity (hereinafter referred to as RAM parity 2) and the RAM parity (hereinafter referred to as RAM parity 3) of the stack area (unused stack area and used stack area) are calculated (Sa9). Then, it is determined whether or not the calculated RAM parity 1 to 3 is 0 (Sa10). As will be described later, if the power interruption process (main) is normally performed when the power is cut off last time, the RAM parity 1 to 3 should be 0, so that the RAM parity 1 to 3 is set in the step of Sd10. If any one of them is not 0, the data stored in the RAM 41c is not normal. In this case, the process proceeds to the step of Sa14 and the destruction diagnosis data is cleared (Sa14). On the other hand, when the RAM parity 1 to 3 are all 0, the destruction diagnosis data 1 stored in the game RAM area, the destruction diagnosis data 2 stored in the non-game RAM area, and the stack area The stored destruction diagnosis data 3 is acquired (Sa11), it is determined whether or not the acquired destruction diagnosis data 1 to 3 are correct (Sa12), and the destruction diagnosis data 1 to 3 are cleared (Sa13). ..

Next, it is determined whether or not the setting key switch 37 is in the ON state (Sa14). When the setting key switch 37 is in the ON state, the timer interrupt is set (Sa19). Specifically, the register of the timer circuit 509 built in the main control unit 41 is set so that the timer interrupt is executed periodically at predetermined time intervals. In this embodiment, the value corresponding to about 0.56 ms is set in a predetermined register (time constant register), so that the timer interrupt is periodically generated every about 0.56 ms. Further, in the timer circuit 509, the timer is initialized by setting the register, and the time counting is started from the initial value. When the timer interrupt setting in the step of Sa19 is completed, the process shifts to the setting change process.

On the other hand, when the setting key switch 37 is in the OFF state, it is determined whether or not the stored contents of the RAM 41c are destroyed (Sa15). In the step of Sa15, it is determined whether or not the RAM abnormality flag described later is set, and whether or not the stored contents of the RAM 41c are destroyed based on the determinations of Sa10 and Sa12. If the stored contents of the RAM 41c are not destroyed, a return command is transmitted to the sub-control unit 91 (Sa16). When the stored contents of the RAM 41c are not destroyed, it is determined that the RAM abnormality flag is not set and the RAM parity 1 to 3 are all 0 in the step of Sa10, and further in the step of Sa12. This is a case where all of the destruction diagnosis data 1 to 3 are determined to be correct.

After the step of Sa16, all the registers are restored (Sa17), and the timer interrupt is set in the same manner as in the step of Sa19 (Sa18). Then, the process shifts to the Sd24 process of the timer interrupt process (main) described later. As a result, the process that was executed before the power failure is restored.

If the stored contents of the RAM 41c are destroyed in the step of Sa15, the start address (0000H) of the RAM is set in the register (Sa20), and the specified address is reached to the final address of the usable area (0FFFH). Initialize the region, that is, all regions of the usable region (Sa21).

Next, the RAM error flag indicating that the stored contents of the RAM 41c are not normal is set in the RAM 41c (Sa22), and the process proceeds to error processing. In error handling, the progress of the game is disabled. Further, in the error state in which the RAM abnormality flag is set and the transition is made, the setting key switch 37 is turned on and the power switch 39 is turned on, so that the error state can be canceled by shifting to the setting change processing. On the other hand, when the power switch 39 is turned on without turning on the setting key switch 37, the RAM error flag is still set and an error state occurs again.

Next, the setting change process executed by the main control unit 41 will be described.

As shown in FIG. 12, the main control unit 41 first sets the start address (0000H) of the RAM in the register (Sb1). Next, it is determined whether or not the stored contents of the RAM 41c are destroyed in the same manner as in the step of Sa15 shown in FIG. 11 (Sb2). If the contents of the RAM are not destroyed, that is, if the contents of the RAM are not abnormal, the start address of the RAM to be initialized at the start of setting change is set in the register (Sb3). That is, the address set in Sb1 is changed. If the contents of the RAM are destroyed, that is, if the contents of the RAM are abnormal, the process proceeds to step Sb4.

Next, the area from the address specified in the step of Sb1 or Sb3 to the final address of the usable area is initialized (Sb4). Since the start address of the RAM is set in the step of Sb1, in this case, all the usable areas are initialized in the step of Sb4. On the other hand, in the step of Sb3, the start address of the RAM to be initialized at the start of setting change is set. Therefore, in this case, in the step of Sb4, the areas other than the important work and the special work are initialized. Will be done.

Next, a setting command indicating the start of the setting change state is transmitted to the sub control unit 91 (Sb5) to allow interruption (Sb6).

Next, it is determined whether or not the reset / setting switch 38 has changed from OFF to ON (Sb7). When the reset / setting switch 38 changes from OFF to ON, the set value of the register is updated (1 is added in the case of 1 to 5 and updated to 1 in the case of 6) (Sb8). If the reset / setting switch 38 does not change, it is determined whether or not the start switch 7 has changed from OFF to ON (Sb9). If the start switch 7 does not change, the process returns to the step of Sb7. On the other hand, when the start switch 7 changes from OFF to ON, it is determined whether or not the setting key switch 37 is in the OFF state (Sb10). If the setting key switch 37 is not in the OFF state, the determination is repeated until the setting key switch 37 is in the OFF state. When the setting key switch 37 is OFF, the data of the set value set in the register is stored in the RAM 41c (Sb11).

Next, a setting command indicating the end of the setting change state is transmitted to the sub control unit 91 (Sb12). Then, the start address of the initialization target RAM at the end of the setting change is set in the register (Sb13), and the process proceeds to the main process.

Next, the main process executed by the main control unit 41 will be described. The main process is repeatedly executed for each unit of game. Then, one cycle of the main process corresponds to one unit of the game.

As shown in FIG. 13, the main control unit 41 first prohibits interruption (Sc1). Next, the final address of the RAM to be initialized is set (Sc2).

Next, the RAM area indicated by the specified address is cleared (Sc3). At this time, if the main process is started after the setting change process, the start address of the initialization target RAM at the end of the setting change is set, and in the Sc2 step, the final address of the initialization target RAM at the end of the setting change is set. Since it is set, the areas other than the important work and the special work among the usable areas will be initialized. Further, at the end of the game, which is not the end of the specific game state, the start address of the initialization target RAM at the end of the game is set in the Sc10 step described later, and in the Sc2 step, the initialization target RAM at the end of the game is set. Since the final address of is set, the unused area and the unused stack area of the usable area are initialized. Further, at the end of the specific game state and at the end of the game, the start address of the initialization target RAM at the end of the specific game state is set in the step of Sc11 described later, and in the step of Sc2, the start address of the initialization target RAM is set. Since the final address of the initialization target RAM at the end of the game state is set, the general area, the unused area, and the unused stack area among the usable areas are initialized.

After the RAM is initialized in the step of Sc3, the interrupt is permitted (Sc4), and the game start waiting process is executed (Sc5). In the game start waiting process, a process of waiting in a state in which the bet number can be set, setting a predetermined number of bets according to the game state, and starting the game when the start switch 7 is operated is executed.

Next, the internal lottery process is executed (Sc6). In the internal lottery process, whether to allow the above-mentioned winning of each winning combination based on the random number value for the internal lottery latched at the same time as the game starts by the detection of the start switch 7 in the step of Sc5 (that is, the derivation of the display result is derived. Performs the process of deciding whether or not to allow it.

Next, the reel control process is executed (Sc7). In the reel control process, the process of rotating each reel 2L, 2C, 2R in response to the operation of the start switch 7, the result of the internal lottery in the step of Sd2, and the operation of the stop switches 8L, 8C, 8R by the player are detected. A process of stopping the rotation of the corresponding reels 2L, 2C, and 2R is executed according to the fact.

Next, the game end setting process is executed (Sc8). In the game end setting process, when it is determined that the rotation of all reels 2L, 2C, and 2R has stopped in the Sc7 process, a prize is generated according to the display result derived for each reel 2L, 2C, and 2R. Execute the process of determining whether or not. Then, when it is determined that a prize has been generated, credits are added and medals are paid out based on the number of payouts according to the prize. When a prize is won, a process of setting the game state is executed in preparation for the next game after the payout of medals is completed. Further, if no winning is generated, after the reels are stopped, a process of setting the game state is executed in preparation for the next game.

When the game end time setting process is completed, it is determined whether or not it is the end of a specific game state (Sc9), and if it is not the end of the specific game state, the start address of the initialization target RAM at the end of the game is set. Set (Sc10) and return to the step of Sc1. If it is the end of the specific gaming state, the start address of the initialization target RAM at the end of the specific gaming state is set (Sc11), and the process returns to the Sc1 step.

In the main process, a command storage process that generates a command and sets it in the command queue is executed according to the progress of the game, and the set command is executed in the subsequent timer interrupt process (main) during normal operation. It is transmitted to the sub-control unit 91 by the command transmission process.

14 and 15 are flowcharts showing the control contents of the timer interrupt process (main) executed by the main control unit 41 interrupting the basic process (mainly the main process) at regular intervals (intervals of about 0.56 ms). is there. The timer interrupt process (main) is a process executed by an interrupt generated according to the count of the timer circuit 509, and the address in which the timer interrupt process (main) program is stored is a vector table. It is set as a value corresponding to the timer interrupt of. Then, when the timer interrupt occurs, the process from the address is executed. In addition, other interrupts are automatically prohibited during the execution period of the timer interrupt process (main).

As shown in FIG. 14, in the timer interrupt process (main), first, the register in use is saved in the stack area (Sd1).

Next, a power failure determination process is performed (Sd2). In the power failure determination process, it is determined whether or not a voltage decrease signal has been input from the power failure detection circuit 48, and if the voltage decrease signal has been input, whether or not the voltage decrease signal has been input even in the previous power failure determination process. If a voltage drop signal is input even in the previous power failure determination process, it is determined that there is a power failure, and a power failure flag indicating that is set.

After the power failure determination process in the step of Sd2, it is determined whether or not the power failure flag is set (Sd3), and if the power failure flag is not set, the process proceeds to Sd4 and the detection data of various switches from the input port. Performs port input processing to input. On the other hand, when the power failure flag is set, after executing the power failure command transmission process (Sd19) for transmitting various commands set in the command queue to the sub control unit 91, the power failure process (main). Move to.

Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sd5). In the step of Sd5, 1 is added when the branch counter value is 0 to 2, and the value is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0 ... Each time the timer interrupt process (main) is executed.

Next, it is determined whether it is 2 or 3, that is, timer interrupt 3 or timer interrupt 4 by referring to the branch counter value (Sd6), and if it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt. In the case of 1 or timer interrupt 2, the motor phase signal output process for outputting the phase signal data of the reel motors 32C, 32C, 32R is executed (Sd7).

Next, it is determined whether or not it is 1 by referring to the branch counter value, that is, whether or not it is timer interrupt 2 (Sd8), and if it is not timer interrupt 2, that is, if it is timer interrupt 1, the reel motor Reel start processing (Sd9) that controls the step time interval at the start of 32L, 32C, 32R, motor step processing (Sd10) that changes the phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C , 32R is stopped, and after a certain period of time has elapsed, the motor phase signal standby process (Sd11) for changing the phase signal to one-phase excitation is sequentially executed, and then the process proceeds to the step of Sd24.

Further, when it is determined in the step of Sd8 that the timer interrupt is 2, the LED dynamic display process (Sd12) for dynamically lighting various indicators, and the control for outputting data such as lighting signals of various LEDs to the output port. Signal output processing (Sd13), time counter update processing for updating various time counters (Sd14), door monitoring processing for monitoring the detection status of the door open detection switch 25, door monitoring processing for requesting transmission of door commands (Sd15), command queue After sequentially executing the normal command transmission process (Sd16) for transmitting various commands set to to the sub-control unit 91 and the external output signal update process (Sd17) for updating the external output signal, the process proceeds to the step of Sd24.

Further, when it is determined in the step of Sd6 that the timer interrupt is 3 or the timer interrupt 4, it is further determined whether or not the branching counter value is 3, that is, whether or not the timer interrupt is 4 (Sd18). If it is not the timer interrupt 4, that is, if it is the timer interrupt 3, the origin passage process (Sd19) for checking the origin passage (passage of the reel reference position) of the rotating reels 2L, 2C, and 2R, and the switches After sequentially executing the switch input determination process (Sd20) for determining whether or not the detection state has changed, the process proceeds to the step of Sd24.

Further, when it is determined in the step of Sd18 that the timer interrupt is 4, the stop switch process (Sd21) for determining the stop position according to the detection of the stop switches 8L, 8C, 8R, and the two-phase when it is time to stop. After sequentially executing the stop process (Sd22) for starting the brake by excitation and the final stop process (Sd23) for three-phase excitation after a certain time from the start of the brake in the stop process, the process proceeds to the step of Sd24.

In the step of Sd24, the register saved in the stack area in Sd1 is restored, and the process returns to the process before the interrupt.

As described above, in this embodiment, the main control unit 41 is started in the interrupt-prohibited state when a reset occurs, and is interrupted by the program at the start of the initial setting process to be executed for the first time thereafter. The prohibition is performed, and even if the main control unit 41 is activated in a state where the interrupt is not prohibited for some reason, it is possible to prevent an unintended interrupt from occurring.

Further, after the main control unit 41 is activated, after setting the timer interrupt in the timer circuit 509, the interrupt is permitted, and the interrupt occurs in a state where the timer interrupt does not operate normally. It can be prevented from being interrupted. Further, in the timer circuit 509, the timer is initialized by setting the timer interrupt, and the time counting is started from the initial value, and the time from the start until the first interrupt occurs. The timer interrupt can be generated at regular time intervals without any deviation from the time until the second and subsequent interrupts occur. Further, the main control unit 41 updates the setting of the timer circuit 509 to the initial value by the program in the initial setting process, and the setting of the timer circuit 509 is rewritten for some reason at the time of startup. Even if there is, it is possible to prevent an unintended interruption from occurring.

Further, if the setting key switch 37 is in the ON state at the time of activation, the main control unit 41 shifts to the setting change processing, and initializes the RAM 41c at the start of the setting change processing. At this time, if the data in the RAM 41c is normal, by holding the important work and the special work and initializing the other areas, the control state (set value, game state, etc.) before the change is maintained even after the setting is changed. While a part can be retained, if the data in RAM 41c is not normal, the data in RAM 41c can be reliably abnormal by initializing all areas of the usable area including important work and special work. It can be resolved.

Further, since the RAM abnormality flag is set in the main control unit 41 when the RAM abnormality is determined, the RAM parity is 0 when the power is turned off again after the RAM abnormality error occurs and the power is turned on again. Therefore, even when the destruction diagnosis data is determined to be normal, it is possible to determine whether or not the data in the RAM 41c is destroyed based on the RAM abnormality flag.

Further, after the setting change processing is completed, the main control unit 41 executes a main process for stepwise processing according to the progress of the game for each game unit. Further, in the main process, the RAM 41c is initialized for each game unit, and the RAM 41c is also initialized at the end of the setting change process. Then, after the setting change process is completed, the main process is started from the stage before the process of initializing the RAM 41c in the main process, and the initialization of the RAM 41c after the setting change process is completed and the game unit. It is possible to initialize the RAM 41c for each unit by a common process.

Further, when the RAM 41c is initialized, the main control unit 41 prohibits interrupts until the initialization is completed, and the timer interrupt process (main) is performed during the execution of the initialization of the RAM 41c. When it occurs, it is possible to prevent the initialized contents from being changed or the processing performed in the timer interrupt processing (main) from being performed normally.

Further, the main control unit 41 updates the output state of the external output signal in the main process, and changes the output state of the external output signal in the subsequent timer interrupt process (main) based on the updated output state. At the same time, when updating the output status of the external output signal, interrupting is prohibited until the update is completed, and the timer interrupt processing (main) occurs before the output status of the external output signal is completed. By doing so, it is possible to prevent an external output signal indicating unintended data from being output.

The main control unit 41 of this embodiment generates a command according to the progress of the game in the above-mentioned setting change process and main process, stores the generated command in the command queue, and performs a normal time in the timer interrupt process (main). Every time the command transmission process is executed, the untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

FIG. 16 is a flowchart showing the control contents of the command storage process executed when various commands generated by the main control unit 41 are stored in the command queue. The command transmitted by the main control unit 41 is composed of 2 bytes, the first byte represents MODE (command classification), and the second byte represents EXT (command content). Further, the command form shown in this embodiment is an example, and other data forms may be used. Further, in this embodiment, the command is composed of a 2-byte signal, but these commands may be composed of a 1-byte signal or a 3-byte or more signal.

In the command storage process, first, MODE and EXT constituting the command to be transmitted are generated (Se1). Then, after storing the MODE and EXT of the generated command in the area of the area number indicated by the storage pointer, that is, in the free area of the command queue (Se2), 1 is added to the area number indicated by the storage pointer (Se3). Since the area number is a numerical value in the range of 0 to 31, when the serial number indicated by the storage pointer is 31, 1 is added and updated to 0 when it becomes 32.

Next, it is confirmed whether or not the untransmitted flag is set (Se4), and if the untransmitted flag is not set, the untransmitted flag is set (Se5). Then, it is confirmed whether or not the area number indicated by the storage pointer and the area number indicated by the transmission pointer match, that is, whether or not all the areas of the command queue are filled with untransmitted commands. If this is the case, wait until the unsent command stored in the command queue is sent and the area number indicated by the storage pointer and the area number indicated by the transmission pointer do not match, and the area number indicated by the storage pointer. The command storage process ends when the area number indicated by the transmission pointer does not match, that is, when the command queue becomes empty (Se6).

FIG. 17 shows the control of the normal command transmission process executed in the timer interrupt 2 of the timer interrupt process (main) described above in order for the main control unit 41 to transmit the command stored in the command queue by the command storage process. It is a flowchart which shows the content.

In the normal command transmission process, first, it is confirmed whether or not the untransmitted flag is set, that is, whether or not the untransmitted command is stored in the command queue (Sf1), and the untransmitted flag is not set. In this case, the detection state of the door open detection switch 25 is acquired, MODE and EXT constituting the door command are generated, and the generated MODE and EXT are stored in the area of the area number indicated by the storage pointer, that is, in the free area of the command queue. Store (Sf2, Sf3).

When it is determined that the untransmitted flag is set in the step of Sf1, and after the MODE and EXT constituting the door command are stored in the command queue in the steps of Sf2 and Sf3, the area indicated by the transmission pointer value of the command queue. The command stored in is transmitted to the sub-control unit 91 (Sf4 to Sf7). Specifically, first, the MODE constituting the command stored in the area indicated by the transmission pointer value of the command queue is output (Sf4), and a strobe signal for notifying the sub-control unit 91 that the command has been output is sent for a predetermined time. (In this embodiment, 10 μs) is output (Sf5). Then, the EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sf6), and the strobe signal is output again for a predetermined time (Sf7).

Next, 1 is added to the area number indicated by the transmission pointer (Sf8). Since the area number is a numerical value in the range of 0 to 31, when the area number indicated by the transmission pointer is 31, 1 is added and the area number is updated to 0 when it becomes 32. After that, it is confirmed whether the area number indicated by the transmission pointer and the serial number indicated by the storage pointer match, that is, whether the command to be transmitted is stored in the command queue (Sf9), and if they match. That is, when the command to be transmitted is not stored in the command queue, the untransmitted flag is cleared and the normal command transmission process is terminated (Sf10). On the other hand, if the area number indicated by the send pointer and the serial number indicated by the storage pointer do not match, that is, when the command to be sent is stored in the command queue, the unsent flag is maintained and the command is sent during normal operation. End the process. By maintaining the untransmitted flag, the untransmitted command left in the command queue will be transmitted in the timer interrupt process (main) from the next time onward.

The main control unit 41 of this embodiment executes a command transmission process at the time of power failure before executing the power failure process (main) when the power failure flag is set in the above-mentioned timer interrupt process. In addition to the normal command transmission process, the untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

FIG. 18 is a flowchart showing the control contents of the command transmission process at the time of power interruption, which is executed before the power interruption process (main) is performed by the main control unit 41 in the timer interrupt process (main).

In the command transmission process at the time of power failure, first, it is confirmed whether or not the untransmitted flag is set, that is, whether or not the untransmitted command is stored in the command queue (Sg1), and the untransmitted flag is set. If so, all the commands stored in the command queue are transmitted to the sub-control unit 91 (Sg1 to Sg7).

Specifically, first, the MODE constituting the command stored in the area indicated by the transmission pointer value of the command queue is output (Sg2), and a strobe signal for notifying the sub-control unit 91 that the command has been output is sent for a predetermined time. (In this embodiment, 10 μs) is output (Sg3). Then, the EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sg4), and the strobe signal is output again for a predetermined time (Sg5). After that, 1 is added to the area number indicated by the transmission pointer (Sg6). Since the area number is a numerical value in the range of 0 to 31 as in the case of adding the transmission pointer in the normal command transmission process, when the area number indicated by the transmission pointer is 31, 1 is added to obtain 32. Update to 0.

Next, it is determined whether or not the area number indicated by the transmission pointer and the serial number indicated by the storage pointer match, that is, whether or not the command to be transmitted is stored in the command queue (Sg7), and the area indicated by the transmission pointer. If the number and the serial number indicated by the storage pointer do not match, that is, when the command to be transmitted is stored in the command queue, the area number indicated by the transmission pointer and the serial number indicated by the storage pointer in the step of Sg7 The steps Sg2 to Sg7 are repeatedly executed until it is determined that they match, and all the commands stored in the command queue are transmitted to the sub-control unit 91.

Then, in the step of Sg7, when it is determined that the area number indicated by the transmission pointer and the serial number indicated by the storage pointer match, that is, all the commands stored in the command queue are transmitted to the sub-control unit 91. When no command remains in the command queue, the main control unit 41 clears the untransmitted flag (Sg8), ends the command transmission process at the time of power interruption, and shifts to the power interruption process (main).

In this way, in the normal command transmission process, one command (a set of commands consisting of 2 bytes) is sent to the sub-control unit 91 each time the normal command transmission process is executed in the timer interrupt process (main). On the other hand, in the command transmission process at the time of power interruption, all the commands stored in the command queue are sent to the sub-control unit 91 before the power interruption process (main) is performed in the timer interrupt process. It is designed to be sent.

FIG. 19 shows the power interruption process (main) executed after the power interruption command transmission process when the main control unit 41 determines that the power interruption flag is set in the timer interrupt process (main) described above. It is a flowchart which shows the control content. In this embodiment, the power interruption process is included in the non-game program.

In the power failure processing (main), first, all the registers that may be used are saved in the stack area (Sg1).

Next, the destruction diagnosis data 1 is set in the game RAM area, the destruction diagnosis data 2 is set in the non-game RAM area, and the destruction diagnosis data 3 is set in the stack area (Sg2). The data for destructive diagnosis are all 5A (H). Then, all the output ports including the parallel output port 513 that outputs the command are initialized (Sg3). As a result, the output state of the output port corresponding to the last output command by the command transmission process at the time of power failure is initialized. Next, the RAM parity adjustment data 1 is calculated and set in the game RAM area so that the exclusive OR of all areas (including the unused area 3) of the game RAM area becomes 0, and the non-game RAM area is set. The RAM parity adjustment data 2 is calculated and set in the non-gaming RAM area so that the exclusive OR of all areas (including the unused area 4) becomes 0, and all areas of the stack area (unused stack). The RAM parity adjustment data 3 is calculated and set in the stack area (Sg4) so that the exclusive OR of the area and the used stack area becomes 0, and access to the RAM 41c is prohibited (Sg5). After that, the voltage drops, the CPU 41a of the main control unit 41 stops, and the state shifts to the standby state. Then, when the voltage drops in this standby state, the main control unit 41 is internally stopped in operation, and the operation is surely stopped in the event of a power failure.

When the power supply of AC100V is stopped by the above processing, the power interruption processing is executed, the destruction diagnosis data 1 to 3 and the RAM parity adjustment data 1 to 3 are stored in the backup RAM, and RAM access is performed. It is prohibited and the output port is cleared.

As described above, in this embodiment, in the power failure processing executed when the power failure is detected, the process of calculating the RAM parity adjustment data for determining whether the data in the RAM 41c is normal, and the data when the power is turned on The process of calculating the RAM parity for determining whether or not it is normal, and the process of determining whether or not the data of the RAM 41c is normal based on the RAM parity when the power is turned on are performed separately for the game RAM area and the non-game RAM area. Therefore, the data storage area required for designing these processes can be easily specified.

In this embodiment, the adjustment data is set in the target area so that the calculation result of the target area in the power interruption process becomes a specific value (0 in this embodiment), and the target area is set in the start-up process. Whether or not the data in the RAM 41c is normal is determined by whether or not the calculation result of the area is a specific value. However, the calculation result of the target area in the power failure process and the target area in the start-up process are determined. It may be configured to determine whether or not the data in the RAM 41c is normal depending on whether or not the calculation result of the above matches. Further, the calculation method is not limited to the exclusive OR, and other calculation methods (for example, total sum) may be used.

Further, in this embodiment, the RAM parity adjustment data 1 is calculated using the data stored in all the areas of the game RAM area including the unused area 3 in the power interruption process, and the non-game including the unused area 4 is calculated. RAM parity adjustment data is calculated using the data stored in all areas of the RAM area, and the RAM calculated using the data stored in all areas of the game RAM area including the unused area 3 in the startup process. It is determined whether the RAM 41c is normal or not based on the RAM parity 2 calculated using the data stored in all the areas of the non-gaming RAM area including the parity 1 and the unused area 4. When an invalid program is stored in the used areas 3 and 4, it is determined that the RAM is abnormal, so that it is possible to prevent the illegal program from being stored in the unused areas 3 and 4.

In this embodiment, the RAM parity adjustment data 1 is calculated using the data stored in all the areas of the game RAM area including the unused area 3 in the power interruption process, and the non-game including the unused area 4 is calculated. RAM parity adjustment data is calculated using the data stored in all areas of the RAM area, and the RAM calculated using the data stored in all areas of the game RAM area including the unused area 3 in the startup process. It is configured to determine whether the RAM 41c is normal or not based on the RAM parity 2 calculated using the data stored in all the areas of the non-gaming RAM area including the parity 1 and the unused area 4, but it is unused. RAM parity adjustment data 1 is calculated using the data stored in the game RAM area that does not include the area 3, and RAM parity adjustment data is used using the data stored in the non-game RAM area that does not include the unused area 4. Is calculated, and the data stored in the non-game RAM area that does not include the unused area 4 and the RAM parity 1 calculated using the data stored in the game RAM area that does not include the unused area 3 in the startup process are used. The configuration may be such that it is determined whether or not the RAM 41c is normal based on the RAM parity 2 calculated in the above.

Further, in the power interruption processing, the RAM parity adjustment data 1 is calculated using the data stored in all the areas of the game RAM area including the unused area 3, and stored in the non-game RAM area not including the unused area 4. The RAM parity adjustment data is calculated using the calculated data, and the RAM parity 1 and the unused area 4 are calculated using the data stored in all the areas of the game RAM area including the unused area 3 in the start-up process. It may be configured to determine whether or not the RAM 41c is normal based on the RAM parity 2 calculated using the data stored in the non-game RAM area that does not include the above, and even in such a configuration, the unused area may be used. When an invalid program is stored in 3, it is determined that the RAM is abnormal, so that it is possible to prevent the illegal program from being stored in the unused area 3.

Further, in the power interruption processing, the RAM parity adjustment data 1 is calculated using the data stored in the game RAM area that does not include the unused area 3, and is stored in all the non-game RAM areas including the unused area 4. RAM parity adjustment data is calculated using the data, and the non-game including the RAM parity 1 and the unused area 4 calculated using the data stored in the game RAM area that does not include the unused area 3 in the start-up process. It may be configured to determine whether or not the RAM 41c is normal based on the RAM parity 2 calculated using the data stored in all the areas of the RAM area. Even in such a configuration, the unused area 4 may be used. When an invalid program is stored in, it is determined that the RAM is abnormal, so that it is possible to prevent the illegal program from being stored in the unused area 4.

Further, in this embodiment, in the power interruption process executed when the power failure is detected, the process of calculating the RAM parity adjustment data for determining whether the data in the RAM 41c is normal, and the data is normal when the power is turned on. A configuration in which the process of calculating the RAM parity for determining whether or not the data is normal and the process of determining whether or not the data of the RAM 41c is normal based on the RAM parity when the power is turned on are divided into a game RAM area and a non-game RAM area. However, in the power interruption process, the game RAM area is calculated by calculating the adjustment data in which the calculation result using both the data stored in the game RAM area and the data stored in the non-game RAM area becomes a specific value. Alternatively, the RAM 41c is set in the non-game RAM area, and is based on whether or not the calculation result using both the data stored in the game RAM area and the data stored in the non-game RAM area in the startup process becomes a specific value. In the configuration for determining whether or not the data in the above is normal, that is, in the power interruption process, the process for calculating the adjustment data for determining whether or not the data in the RAM 41c is normal, and determining whether or not the data is normal when the power is turned on. The process of calculating the data to be performed and the process of determining whether or not the data of the RAM 41c is normal based on the data calculated when the power is turned on may be performed without distinguishing between the game RAM area and the non-game RAM area. With such a configuration, in the power failure process, a process of calculating adjustment data for determining whether the data in the RAM 41c is normal, and a process for determining whether the data is normal when the power is turned on. It is possible to reduce the program capacity required for the process of calculating the data and the process of determining whether or not the data in the RAM 41c is normal based on the data calculated when the power is turned on.

Further, even in such a configuration, in the power interruption processing, adjustment data is calculated using not only the game RAM area and the non-game RAM area but also the data of all the areas including the unused areas 3 and 4, and the activation process is performed. Whether or not the data in the RAM 41c is normal depends on whether or not the result calculated using the data of all the areas including the unused areas 3 and 4 as well as the game RAM area and the non-game RAM area becomes a specific value. It is preferable to have a configuration for determining whether or not, and even in such a configuration, if an invalid program is stored in the unused areas 1 and 2, it is determined that the RAM is abnormal. Therefore, the unused areas 1 and 2 It is possible to prevent malicious programs from being stored in the data.

In this embodiment, as shown in FIG. 20, the reset circuit 49 of the game control board 40 has a monitoring voltage (DC + 24V) higher than the drive voltage (DC + 5V) of the main control unit 41 among the power supply voltages supplied from the power supply board 101. ) Is monitored, and when the monitoring voltage exceeds the operable voltage (main) (+ 3.5V) that enables the main control unit 41 to operate when the power is turned on, the reset signal is turned on to the main control unit 41. After the output, when a sufficient time (sufficient time for the monitoring voltage to rise to + 24V) has elapsed for the drive voltage (DC + 5V) of the main control unit 41 to stabilize, the reset signal is turned off and the main control unit 41 is turned off. The control unit 41 is activated. On the other hand, the reset circuit 95 of the effect control board 90 has the sub control unit 91 when the reset signal is turned off by the reset circuit 49 when the power is turned on, that is, at a timing earlier than the timing when the main control unit 41 is activated. By turning off the reset signal output to the main control unit 41, the sub control unit 91 is activated at an earlier stage than the main control unit 41 when the power is turned on, and a return command or setting command (start) transmitted from the main control unit 41. ) Is put on standby in a state where the sub-control unit 91 can receive.

Then, the main control unit 41 executes the above-mentioned initial setting process when the reset signal output by the reset circuit 49 is turned off and starts up, and if it is possible to return to the state before the power failure, the initial setting After sending a reset command at the end of the process, the timer interrupt is permitted, and then the timer interrupt process is executed at regular intervals. Further, when the reset signal is turned off and the operation is started, the setting key switch 37 is in the ON state, the RAM 41c is initialized, and the setting change state is started without returning to the state before the power failure. , Before the timer interrupt is permitted at the end of the initial setting process, a setting command (start) is sent to the sub-control unit 91 instead of the reset command, and then the timer interrupt is permitted, and then the timer The interrupt process is executed at regular intervals. On the other hand, the sub control unit 91 starts before the main control unit 41 starts, executes and completes the initial setting process, and waits until a return command or a setting command (start) is received in a state where the command can be received. To do.

Next, the main control unit 41 executes the timer interrupt process (main) at regular intervals after transmitting the return command or the setting command, and executes the normal command transmission process in the timer interrupt process (main). At that time, if the command to be transmitted is not stored in the command queue, the door command is generated and transmitted based on the detection state of the door open detection switch 25. On the other hand, the sub control unit 91 starts the output control of the effect device by receiving the return command or the setting command (start).

In addition, the main control unit 41 transmits a door command or the like by a normal command transmission process executed in the timer interrupt process (main), and after the main control unit 41 is started, the timer is interrupted until the end of the initial setting process. The interrupt is not permitted, and after the main control unit 41 is started, after the return command or setting command (start) is transmitted, the transmission of commands such as the door command transmitted by the normal command transmission process is permitted. It will be.

Further, as shown in FIG. 20, the main control unit 41 executes a power failure determination process in the timer interrupt process (main) based on whether or not a voltage drop signal is input from the power failure detection circuit 48. Identify the occurrence of a power outage. The power failure detection circuit 48 monitors the above-mentioned monitoring voltage (DC + 24V) higher than the drive voltage (DC + 5V) of the main control unit 41, and detects a voltage drop in which the monitoring voltage is higher than the drive voltage (DC + 5V) of the main control unit 41. Since the voltage drop signal is output when the voltage (main) (+ 20V) or less, the main control unit 41 identifies the occurrence of the power failure when the monitoring voltage becomes the voltage drop detection voltage (main) or less. .. Then, when the occurrence of the power failure is specified in the power failure determination process, the main control unit 41 executes the command transmission process at the time of the power failure, and sends all the commands stored in the command queue to the sub control unit 91. After sending, the power failure process (main) is executed.

Further, the reset circuit 49 has an operating limit voltage (main) (+ 8V) or less in which the monitoring voltage is lower than the voltage drop detection voltage (main) (+ 20V) and higher than the operable voltage (main) (+ 3.5V). As a result, the reset signal is turned on to make the main control unit 41 inoperable. The operating limit voltage (main) is the voltage drop for the time until the voltage drop detection circuit 48 drops to the operating limit voltage (main) after it becomes equal to or lower than the voltage drop detection voltage (main) that detects the occurrence of a power failure. After the voltage drops below the detection voltage (main), the main control unit 41 identifies the occurrence of a power failure, executes the command transmission process at the time of the power failure, and secures the time required to execute the power failure process. Is set to.

The time required for the main control unit 41 to identify the occurrence of a power failure after the voltage drop detection voltage (main) or less, execute the command transmission process at the time of the power failure, and execute the power failure process is The maximum time until the main control unit 41 detects a power failure (0.56 ms because the occurrence of a power failure is specified for each timer interrupt process (main)) and the command queue in the command transmission process at the time of a power failure. The time required to transmit the maximum number of commands (32) that can be stored (40 μs for one command transmission (MODE transmission 10 μs, transmission interval 10 μs, EXT transmission 10 μs, transmission interval 10 μs), so 40 for the maximum number of transmissions) × 32 = 1280 μs) and the time required for the power interruption process (main), which is the total time.

On the other hand, the power failure detection circuit 98 monitors the above-mentioned monitoring voltage (DC + 24V) higher than the drive voltage (DC + 5V) of the sub control unit 91, and the monitoring voltage is lower than the operation limit voltage (main) (+ 8V). Since a voltage drop signal is output when the voltage drop detection voltage (sub) (+ 6V) is higher than the drive voltage (DC + 5V) of the sub control section 91, the monitoring voltage of the sub control section 91 is the voltage drop detection voltage (sub). The occurrence of power failure will be identified by the following. Then, when the occurrence of the power failure is specified in the power failure determination process, the sub control unit 91 executes the power failure process (sub).

Further, the reset circuit 95 has an operating limit voltage (sub) (+ 4V) or less in which the monitoring voltage is lower than the voltage drop detection voltage (sub) (+ 6V) and higher than the operable voltage (sub) (+ 3.5V). As a result, the reset signal is turned on to make the sub control unit 91 inoperable. The operating limit voltage (sub) is the voltage drop for the time from when the power failure detection circuit 98 drops below the voltage drop detection voltage (sub) that detects the occurrence of a power failure until it drops to the operation limit voltage (sub). The sub control unit 91 identifies the occurrence of a power failure after the voltage falls below the detection voltage (sub), and is set so that the time required to execute the power failure process is secured.

Further, in the sub control unit 91, the main control unit 41 becomes inoperable after the monitoring voltage is the operation limit voltage (main), that is, the command transmission process and the power cut process (main) at the time of power interruption by the main control unit 41 are completed. When the voltage drop detection voltage (sub) is lower than the voltage, the voltage drop signal output is used to identify the occurrence of the power failure and execute the power failure process (sub). At least the main control unit 41 Since the state in which commands can be received is maintained until the command transmission process at the time of power failure is completed, the power failure process should be executed in a state where the main control unit 41 has received all the commands transmitted by the command transmission process at the time of power failure. Can be done. Even if the timing at which the sub-control unit 91 identifies the occurrence of a power failure is the timing before the main control unit 41 becomes inoperable, the command transmitted by the main control unit 41 by the command transmission process at the time of power failure is transmitted. If the configuration is such that the command can be received until the timing sufficient to receive all the commands, the main control unit 41 executes the power interruption process in the state where all the commands transmitted by the command transmission process at the time of power failure are received. can do.

As described above, the main control unit 41 of the present embodiment generates a command according to the progress of the game in the main process or the like, stores the generated command in the command queue, and performs a normal command in the timer interrupt process (main). Each time a transmission process is executed, an untransmitted command stored in the command queue is transmitted to the sub-control unit 91.

In such a configuration, while a plurality of commands are stored in the command queue, the power supply to the slot machine 1 may be stopped and a power failure may occur, and the main control is performed when the power failure is detected by the main control unit 41. A plurality of commands have not been transmitted on the unit 41 side, the untransmitted commands are retained as they are even after the power failure, and the commands held before the power failure are transmitted to the sub control unit 91 after the power failure is restored. If transmitted, the control state on the main control unit 41 side at the time of power interruption and the time of recovery from power interruption will be different from the control state on the main control unit 41 side specified by the sub control unit 91 side.

On the other hand, in the present embodiment, the main control unit 41 is stored in the command queue before executing the power interruption process (main) for returning to the control state before the power failure when the power failure is detected. Since the command transmission process at the time of power failure is executed to transmit all the commands to the sub control unit 91, the control state on the main control unit 41 side at the time of power failure and the time of recovery from power failure and the sub control unit 91 The control state on the main control unit 41 side specified on the side can be matched as much as possible.

Further, the main control unit 41 has a maximum number of commands that can be stored in the command queue during the period from when the power supply is stopped until when the power supply becomes uncontrollable at the time of power failure detection (up to 32 commands in this embodiment). Is transmitted to the sub-control unit 91, and it is longer than the period required for the power failure process (main) to be completed. Therefore, after the power failure is detected, all the commands stored in the command queue are transmitted. It is possible to reliably execute the processing up to the power interruption processing (main).

In this embodiment, the main control unit 41, which is the first control means for controlling the game, transmits a command as control information to the sub control unit 91, which is the second control means for controlling the effect. However, the first control means may be a control means other than the control of the game, for example, the control of the effect. Further, the second control means may be any control means that performs some control based on the control information transmitted from the first control means. For example, the second control means is a control means that controls the effect. In some cases, the control means that controls the effect device based on the control information transmitted from the first control means may be used as the second control means.

Further, in this embodiment, as the power interruption process (main) executed by the main control unit 41 (first control means), the RAM parity is adjusted so that the RAM parity (exclusive logical sum) of the backup area becomes 0. By setting the data and performing the process of setting the destruction diagnosis data (data other than 0), the RAM parity is 0 at the time of recovery from the power failure, and the destruction diagnosis data match, so that the data in the backup area However, if the power supply to the slot machine 1 is stopped and a power failure occurs, the control state before the power failure can be restored. A good example is that the checksum of the backup area may be set and the checksum of the backup area may be determined to be normal by matching the checksum calculated at the time of recovery from the power failure.

Further, in the present embodiment, when the reset circuit 49 of the game control board 40 becomes an operable voltage (main) or less, the monitoring voltage drops and the main control unit 41 becomes inoperable when a power failure occurs. Is supplied to the main control unit 41, and when a reset signal is supplied, the main control unit 41 stops all operations, that is, is in an uncontrollable state, and the main control unit 41 is configured after the power failure is detected. , The period until the reset signal is supplied and the control becomes uncontrollable is required for the maximum number of commands that can be stored in the command queue to be transmitted to the sub-control unit 91 and for the power interruption process (main) to be completed. Although the configuration is longer than the period, in the configuration in which the reset signal is not supplied to the main control unit 41 at the time of power failure, the monitoring voltage falls below the operable voltage (main) of the main control unit 41 until it becomes uncontrollable. Even if the period is longer than the period required to send the maximum number of commands that can be stored in the command queue to the sub-control unit 91 and complete the power cut processing (main), the power is cut off. After detection, it is possible to reliably execute the processing from the transmission of all the commands stored in the command queue to the power cut processing (main).

Further, in this embodiment, the operation limit voltage (main) for stopping the operation of the main control unit 41 when a power failure occurs is equal to or less than the voltage drop detection voltage (main) at which the power failure detection circuit 48 detects the occurrence of a power failure. After the time until the operation limit voltage (main) drops to the operation limit voltage (main) or less, the main control unit 41 identifies the occurrence of a power failure and performs a command transmission process at the time of the power failure. By setting so that the time required for execution and execution of the power failure processing is secured, the period from the occurrence of the power failure until the main control unit 41 becomes inoperable is stored in the command queue. The configuration is such that the maximum number of possible commands is transmitted to the sub-control unit 91, and the period required for the power interruption processing (main) to be completed is longer than the period required. The sub-control unit 91 can store the maximum number of commands that can be stored in the command queue for the period from when a power failure occurs until the main control unit 41 becomes inoperable by delaying the decrease in drive voltage by a capacitor, battery, capacitor, etc. The maximum number that can be stored in the command queue is the period until the main control unit 41 becomes inoperable or the configuration is such that it is transmitted to the command and is longer than the period required for the power interruption processing (main) to be completed. The command may be transmitted to the sub-control unit 91, and the maximum number that can be stored in the command queue may be set so as to be longer than the period required for the power interruption processing (main) to be completed. Even with this configuration, it is possible to reliably execute the processing from the transmission of all the commands stored in the command queue to the power failure processing (main) after the power failure occurs.

Further, the main control unit 41 of the present embodiment executes the command transmission process at the time of power failure when the power failure is detected, and after transmitting all the commands stored in the command queue to the sub control unit 91, Since the power supply process (main) is executed and each output port of the parallel output port 513 including the output port that outputs the command in the power failure process (main) is initialized, the power supply is erroneously unstable. It is possible to prevent the command from being sent.

Further, the main control unit 41 of the present embodiment executes a normal command transmission process in the timer interrupt process (main), so that a predetermined number of commands stored in the storage area stored in the command queue can be executed. Since (in this embodiment, one) command is transmitted to the sub-control unit 91 every predetermined trigger (once every four timer interrupt processes (main)), a predetermined number (1 in this embodiment) is transmitted. Even if the above commands are stored in the command queue, the number of commands transmitted in one timer interrupt process (main) is limited to a predetermined number, so the commands in the normal command transmission process It is possible to prevent the other control by the main control unit 41 from being delayed due to the transmission of.

In addition, the main control unit 41 of this embodiment sets a command (internal winning command) in the command queue according to the progress of the game at a predetermined trigger (when performing a normal command transmission process executed in the timer interrupt process (main)). , Stop operation command, etc.) is not stored, and by transmitting a door command indicating the detection status of the door open detection switch 25 to the sub control unit 91, the open / closed state of the front door 1b can be changed to the sub control unit. Since 91 can be specified and the door command is transmitted when the command according to the progress of the game is not stored in the command queue at a predetermined trigger, the transmission of the command according to the progress of the game is the door command. It is possible to prevent the delay due to the transmission and the delay of other controls (for example, each control in the main process) by the main control unit 41 due to the transmission of the door command.

Further, the main control unit 41 is allowed to transmit a command such as a door command transmitted by a normal command transmission process after transmitting a return command or a setting command (start) after its activation. After turning on the power, the door command will not be sent until the state before the power failure is restored and the return command is sent, or the setting command (start) is sent without returning to the state before the power failure. Therefore, after it is determined whether or not to restore the main control unit 41, the state of the main control unit 41 can be specified on the sub control unit 91 side, and the main control unit 41 is in the control state before the power failure. When the sub-control unit 91 receives a command in a state where it is not determined whether or not to return, it is possible to prevent an unintended operation from being performed.

In this embodiment, when no command is stored in the command queue in the normal command transmission process, a door command indicating the detection state of the door open detection switch 25 is generated and transmitted. When no command is stored in the command queue in the normal command transmission process, the operation switches (MAXBET switch 6, start switch 7, stop switch 8L, 8C, 8R) are based on the output of the switch detection circuit 44. It is possible to specify the control state on the main control unit 41 side, such as a command indicating the detection state (on / off), a command indicating the presence / absence of error detection and the type of detected error, and a command capable of specifying the game state of the game. A command may be generated and transmitted to the sub control unit 91. Even with such a configuration, the sub control unit 91 can specify the control state on the main control unit 41 side, and the game can be played. The transmission of commands according to the progress is delayed by the transmission of commands that can specify the control state of the main control unit 41, or other control by the main control unit 41 by the transmission of commands that can specify the control state of the main control unit 41. Can be prevented from being delayed.

Next, a timer counter for measuring the time interval used by the main control unit 41 for controlling the progress of the game and the like will be described with reference to FIGS. 21 and 17.

When the timekeeping start condition is satisfied, the main control unit 41 sets an initial value according to the timekeeping time as the timer value of the timer counter assigned to the RAM 41c, and periodically timers in the timer interrupt process (main). The value is subtracted and the timer value becomes 0 to specify that the time has passed.

Specifically, when the timekeeping start condition is satisfied in the main process, the main control unit 41 sets the initial value of the timer value according to the timekeeping time in the area to which the timer counter corresponding to the condition is assigned. The set timer value is subtracted by 1 in the time counter update process of the timer interrupt process (main) until it becomes 0 about every 2.24 ms.

Then, in the main process, as shown in FIG. 21, the address of the corresponding timer counter is acquired (Si1), the acquired value is read (Si2), and it is determined whether or not the read value is not 0 (Si3). , When it is determined that the read value is 0, it is specified that the time counting time has elapsed.

As shown in FIG. 22, the timer counter used in this embodiment has an initial value of 1 byte or less, 1 byte timer A, 1 byte timer B, 1 byte timer C, and an initial value of more than 1 byte and 2 bytes or less. Includes 2-byte timer A, 2-byte timer B, 2-byte timer C, and 2-byte timer D.

The 1-byte timer is a timer for measuring a relatively short period that can be measured with a timer value of 1 byte or less. For example, an external output signal timer that measures the output period of an external output signal and an LED output update period. LED update timer to measure, stop invalid timer to measure the period from detection of stop operation until the stop operation is activated again, payout waiting to measure the period from reel stop to the start of medal payout The timer, the insertion detection timer that measures the period after the ON of the insertion medal sensor 31 is detected, the insertion port detection timer that measures the period after the ON of the insertion port sensor 26 is detected, and the ON of the payout sensor 34c are detected. There are a payout detection timer that measures the period after the start of rotation, a start timer that measures the period from the start of reel rotation until the stop operation becomes effective, and the like. Of these, the stop invalid timer, the payout wait timer, and the start timer do not span the timing at which one game ends in the measurement period by these timers, but the external output signal timer, LED update timer, input detection timer, and input port The detection timer and the payout detection timer may have a measurement time by these timers that spans the timing at which one game ends.

The 2-byte timer is a timer for measuring a relatively long period that cannot be measured with a timer value of 1 byte or less. For example, a 1-game time timer that measures a specified time (about 4.1 seconds) required for 1 game. , A security signal timer that measures the minimum output period of the security signal among the external output signals, a standby time timer that measures the period from the end of the game, and a hopper empty that measures the period during which the payout sensor 34c is not detected after the hopper motor 34b is driven. There is a timer and so on. Of these, the standby time timer and the hopper empty timer do not straddle the timing at which the measurement period by these timers ends for one game, but the one game time timer and the security signal timer have the measurement time by these timers for one game. May straddle the end timing of.

In this way, the timer counter is a timing at which one game ends, that is, a timing at which a part of the RAM 41c is initialized according to the progress of the game (a part of the RAM 41c at the end of one game or at the end of a specific game state). A timer counter that measures the measurement period that straddles the timing at which is initialized) and a timer counter that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game. The counter is also assigned to a special work that is not initialized at the timing according to the progress of the game.

Of these timer counters, the 1-byte timers A to C are allocated 1 byte each to the continuous 3-byte area (804CH to 804EH) of the RAM 41c, and the 2-byte timers A to D are the continuous 8-byte areas of the RAM 41c. Two bytes are allocated to each region (804FH to 8055H). Further, the 1-byte timers A to C and the 2-byte timers A to D are also assigned to the continuous area of the RAM 41c. Hereinafter, the area to which the 1-byte timers A to C are allocated is referred to as a 1-byte timer group, and the area to which the 2-byte timers A to D are allocated is referred to as a 2-byte timer group. That is, both the 1-byte timer group and the 2-byte timer group are set in the area to which consecutive addresses are assigned according to a predetermined rule. The area to which consecutive addresses are assigned according to a predetermined rule is, for example, an area to which an address to be added by N (N is a natural number) from the start address and the start address is assigned.

FIG. 23 is a flowchart showing the control contents of the time counter update process.

In the time counter update process, first, the number of 1-byte timer counters to be updated (3 in this embodiment) is set as the number of 1-byte processes (Sj1), and the start address (804CH) of the 1-byte timer group is set. Set the pointer (Sj2).

Next, if the 1-byte value stored in the specified address (address indicated by the pointer) is not 0, the 1-byte value of the specified address is subtracted by 1 (Sj3), and the number of processes set in the step of Sj1 is subtracted by 1. (Sj4), it is determined whether or not the number of processes after subtraction is 0 (Sj5).

If the number of processes after subtraction is not 0 in the step of Sj5, that is, if the update of all 1-byte timers is not completed, the pointer is added by 1 (Sj6), and the process returns to the step of Sj3. As a result, the pointer moves to the address of the unprocessed 1-byte timer, and if the 1-byte value of the specified address is not 0, it is subtracted.

When the number of processes after subtraction is 0 in the step of Sj5, that is, when the update of all 1-byte timers is completed, the number of 2-byte timer counters to be updated is set as the number of 2-byte processes (this embodiment). Then, 4) is set (Sj7), and the pointer is added by 1 (Sj8). As a result, the pointer moves to the start address (804FH) of the 2-byte counter group.

Next, if the 2-byte value stored in the area consisting of the specified address (address indicated by the pointer) and the next address is not 0, the 2-byte value of the specified address and the next address is subtracted by 1 (Sj9), and Sj7. The number of processes set in step 1 is subtracted by 1 (Sj10), and it is determined whether or not the number of processes after the subtraction is 0 (Sj11).

If the number of processes after subtraction is not 0 in the step of Sj11, that is, if the update of all 2-byte timers is not completed, the pointer is added by 2 (Sj12), and the process returns to the step of Sj9. As a result, the pointer moves to the address of the unprocessed 2-byte timer, and if the 2-byte value of the specified address and the next address is not 0, the pointer is subtracted.

When the number of processes after subtraction is 0 in the step of Sj11, that is, when all the 2-byte timers have been updated, the processes are terminated.

As described above, in this embodiment, the value of the timer counter assigned to the RAM 41c is periodically updated, and the passage of time is specified by becoming a specific value (0). Conventionally, when measuring multiple types of time intervals, timer values are set and updated within multiple types of processing that require timekeeping, and each process is a program for updating multiple types of timer values. Since it is necessary to provide it inside, it has been a factor of increasing the program capacity. In addition, since multiple types of timer counters are assigned as data groups for each process used, it is necessary to read the values of their unrelated addresses in order to update them collectively in one process. there were.

On the other hand, in this embodiment, the area in which a plurality of types of timer counter values are stored is set in the area to which consecutive addresses are assigned according to a predetermined rule of the RAM 41c, and the timer values stored in the specified addresses are set. Since the update process is repeatedly executed while changing the specified address for the area where multiple types of timer counter values are stored by adding a constant to the current specified address, multiple types of timer values are updated. , The program capacity can be reduced as compared with the case where a process of designating a plurality of types of addresses and updating the value of the address is performed in each process.

It should be noted that the process of updating the timer value stored in the specified address is repeatedly executed while changing the specified address for the area in which the timer counter values of multiple types are stored by performing a predetermined operation, thereby performing multiple types of timers. Any configuration may be used as long as the value is updated. For example, by adding a constant to the current specified address, multiple types of timer counter values can be repeatedly executed while changing the specified address for the area where the value is stored. The timer value may be updated, or a value corresponding to the number of processes with respect to the reference address (for example, in the case of a 1-byte counter, +1 for the number of processes 1 and +2 for the number of processes 2 and the number of processes). In the case of 3, +3 ...) may be added or subtracted to update the plurality of types of timer values by repeatedly executing while changing the designated address for the area in which the plurality of types of timer counter values are stored.

Further, in this embodiment, the configuration includes seven types of timer counter values of 1-byte timers A to C and 2-byte timers A to D, but at least two or more types of timer counter values are set according to a predetermined rule of the RAM 41c. The process of updating the timer value stored in the specified address by setting the area where consecutive addresses are assigned in is changed by performing a predetermined operation to change the specified address for the area where multiple types of timer values are stored. However, if the configuration is such that two or more types of timer values are updated by repeatedly executing the timer values, the program capacity can be reduced as described above.

Further, for only one of the 1-byte timer and the 2-byte timer, the timer counter value is set in the area to which continuous addresses are assigned according to a predetermined rule of the RAM 41c, and the timer value stored in the specified address is updated. It is also possible to update the plurality of types of timer values by repeatedly executing the area while changing the designated address for the area in which the plurality of types of timer values are stored by performing a predetermined operation.

Further, only a part of the timer counters provided in the main control unit 41 is set to the area to which continuous addresses are assigned according to a predetermined rule of the RAM 41c, and the timer value stored in the designated address is updated. A configuration may be used in which a plurality of types of timer values are updated by repeatedly executing the operation while changing the designated address for the area in which the plurality of types of timer values are stored by performing a predetermined operation.

Further, in the present embodiment, a separate timer counter is provided for each type of measurement period, but for example, one timer counter may be shared for a plurality of types of periods in which the measurement periods do not overlap.

Further, in this embodiment, as the processes executed by the main control unit 41, a timer interrupt process (main) that periodically performs a predetermined process regardless of the progress status of the game, and a timer interrupt process (main) that periodically performs the process according to the progress status of the game. The main control unit 41 sets an initial value in the timer counter when a timing condition is satisfied in the main process, including a main process that performs different processes in stages, and a plurality of types in the timer interrupt process (main). Since the timer value is updated and it is not necessary to provide a process for updating multiple types of timer values in each process constituting the main process, the program capacity for updating multiple types of timer values is reduced. be able to.

In this embodiment, the timer interrupt process (main) is executed by interrupting the main process periodically, but it is determined in advance in the timer interrupt process that is periodically performed regardless of the progress of the game. A configuration may be configured in which both the periodic processing for performing the processing and the main processing for performing different processing stepwise according to the progress of the game are performed. Even in such a configuration, the main control unit 41 is the main. By setting the initial value in the timer counter when the timing condition is satisfied in the process and updating multiple types of timer values in the periodic process, multiple types of timer values can be set in each process that constitutes the main process. Since it is not necessary to provide a process for updating, it is possible to reduce the program capacity for updating a plurality of types of timer values.

Further, in this embodiment, in the time counter update process, the value of the specified address is updated on the condition that the value of the specified address is not 0, and the timer value is updated to an abnormal value. Can be prevented.

Further, in the present embodiment, in the time counter update process, the same number of processes as the number of timer counters to be updated is set, and the process of updating the timer value is repeatedly executed for the set number of processes. In addition to facilitating the management of the number of timer counters to be updated, for example, when a plurality of types of timer counters having different update intervals are provided, the type of timer value to be updated can be arbitrarily set according to the number of processes to be set. it can.

The number of processes, that is, the number of timer counters to be updated may be set in the program, or the value set in the table may be read and set.

In addition, the timer counter to be updated last is set in advance without setting the number of processes first, and the process of updating the timer value is repeatedly executed until the address of the timer counter is reached, or the process is updated at the end. A specific end value (for example, FFH) is stored at the next address of the timer counter to be used, and the process of updating the timer value is repeatedly executed until the value read from the specified address reaches the specific end value. good.

Further, in this embodiment, a 1-byte timer counter and a 2-byte timer counter are provided, and a process of updating the 1-byte timer value and a process of updating the 2-byte timer value are separately provided. Therefore, the capacity of the program and the capacity occupied by the timer value in the RAM 41c can be reduced as compared with the case where the process of updating the 1-byte timer value and the process of updating the 2-byte timer value are shared.

In this embodiment, a 2-byte timer counter is provided to measure a relatively long time corresponding to an initial value exceeding 1 byte. For example, a timer counter having a different update interval, for example, a timer Interruption processing (main) By providing a first timer counter that updates once every four times and a second timer counter that updates once every 14 times, it is relative without providing a 2-byte counter. It may be configured to measure a long time interval, and by doing so, it is not necessary to provide a process of updating the 1-byte timer value and a process of updating the 2-byte timer value, so that the timer value does not need to be provided. It is possible to reduce the program capacity related to the update of.

Further, in the present embodiment, a plurality of types of timer counters are assigned to a special work that is not initialized according to the progress of the game in the RAM 41c, and are not initialized according to the progress of the game. Regardless of the progress of the game, it is possible to measure the time of the period straddling the timing at which a part of the RAM 41c is initialized according to the progress of the game.

In particular, in this embodiment, not only the timer counter whose measurement period may straddle the end timing of one game, that is, the timing when a part of the RAM 41c is initialized according to the progress of the game, but also the measurement period is the game. Since the timer counter that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress is also stored in the area allocated to the special work together with the other timer counters, the timer counter can be easily managed. At the same time, a timer counter whose measurement period does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game is set, and the timing at which a part of the RAM 41c is initialized according to the progress of the game is set. The usage of the timer counter can be easily changed by a later design change such as changing to a timer counter that may straddle. Further, if one timer counter is shared for a plurality of types of periods in which the measurement periods do not overlap as described above, the timing at which a part of the RAM 41c is initialized may be straddled according to the progress of the game. It is possible to measure the measurement period and the measurement period that does not straddle the timing at which a part of the RAM 41c is initialized according to the progress of the game with one timer counter.

Although the embodiments of the present invention have been described above with reference to the drawings, the present invention is not limited to the present invention and is included in the present invention even if there are changes or additions within the scope of the gist of the present invention. Needless to say.

In the embodiment, an example in which the present invention is applied to a slot machine in which the bet number is set by using medals and credits as the game value has been described, but the slot machine in which the bet number is set by using the game ball as the game value has been described. Alternatively, it may be applied to a fully credited slot machine that sets the number of bets using only credits as a gaming value. When the game ball is used as the game value, for example, one medal can correspond to five game balls, and when the bet number is set to 3 in the first embodiment, 15 game balls are used. Corresponds to setting the number of medals using.

Further, the value is not limited to one using only one of a plurality of types of game values such as medals and game balls, and for example, a plurality of types of game values such as medals and game balls can be used together. It may be. That is, it is possible to set the number of bets and play a game by using any of a plurality of types of game values such as medals and game balls, and a plurality of types of games such as medals and game balls are generated when a prize is generated. A slot machine that can pay out any value may be applied.

Further, in the embodiment, the slot machine has been described as an example of the gaming machine, but the initial setting processing, the timer interrupt processing, the command storage processing, and the normal time related to the main control unit 41 and the main control unit 41 disclosed in the above embodiment have been described. By launching a game ball into another gaming machine, for example, a gaming area, processing related to the sub-control unit 91 and the sub-control unit 91, such as command transmission processing, command transmission processing at the time of power interruption, timer counter update processing, etc. It may be applied to a pachinko gaming machine or the like in which a game is played and the launched game ball enters a winning opening provided in the game area to generate a prize, and the game ball is paid out as a prize ball.

1 Slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 Start switch 8L, 8C, 8R Stop switch 41 Main control unit 91 Sub control unit

Claims (1)

In the game machine that plays the game
A storage means that can store a program and is assigned an address that can identify a storage area,
A control means that controls according to a program stored in the storage means,
The first program calling means for calling the program stored in the specified address by specifying the address, and
A second program calling means for calling a program stored in a specific address corresponding to a specified parameter among a plurality of specific addresses assigned at predetermined intervals by specifying a parameter having a data amount smaller than that of the address. ,
With
The storage means
The first specific program is stored in the area starting from one specific address, the second specific program is stored in the area starting from the next specific address of one specific address, and the first specific program is stored. While storing the predetermined program in the area after the area and before the next specific address ,
Including an address storage means for storing the address of the interrupt program,
The control means includes an interrupt processing execution means that executes a program from the address of the interrupt program stored in the address storage means as an interrupt process based on the interrupt.
The game machine
A determination means for determining whether or not the address stored in the address storage means is within a predetermined range at startup, and
When it is determined that the address stored in the address storage means is not within the predetermined range, the activation prohibiting means for prohibiting the activation of the control means and the activation prohibiting means.
A game machine equipped with.