JP6628962B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine capable of playing a game.

  As a gaming machine, a game device such as a game ball is fired into a game area by a launch device, and a plurality of types of identification information are variably displayed when the game medium wins a start winning area such as a winning opening provided in the game area. And a slot machine that variably displays a plurality of types of identification information (for example, symbols) when a predetermined bet amount is set and a start operation is performed. In the gaming machine configured to be able to execute the variable display of the identification information in this manner, when the display result of the variable display of the identification information becomes a predetermined display result on the variable display unit, a predetermined game value (for example, a jackpot) State transition) to the player.

  As such a gaming machine, there is known a gaming machine that defines an interrupt address when an interrupt of a gaming machine control program occurs in an interrupt vector definition area (Patent Document 1).

JP 2002-52215 A (paragraph 0033 and the like)

  However, in the gaming machine of Patent Literature 1, when an unintended interrupt address is defined in the interrupt vector definition area, normal processing is performed until an interrupt occurs, but an interrupt occurs. Sometimes unintended processing may be executed.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a gaming machine capable of preventing an unintended interrupt process from being executed in advance.

In order to solve the above-mentioned problems, a gaming machine of the present invention
In a gaming machine (for example, slot machine 1) capable of performing a game,
Storage means (for example, ROM 208) for storing a program;
A microcomputer (for example, a portion shown in FIG. 11) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, a portion shown in FIG. 12) executed in response to the occurrence of the interrupt,
The microcomputer includes :
When the interrupt is enabled, an interrupt execution unit for executing processing in accordance with the interrupt program based on該割write (e.g., the portion shown in FIGS. 8 and 9),
Address storage means (for example, a portion shown in FIG. 13) having a storage area capable of storing an address of an interrupt program in the storage means;
Determining means (for example, a portion shown in FIG. 22) for determining whether or not an address stored in a storage area of the address storing means is within a predetermined range when the microcomputer is started;
A start restricting unit (for example, a part shown in FIG. 22) for restricting the start of the microcomputer when the judging unit judges that the address of the interrupt program is not within a predetermined range.
According to this configuration, execution of an unintended interrupt process can be prevented in advance.

The microcomputer includes a random number circuit (for example, a random number circuit 212) that generates numerical data that is a random number value,
The random number circuit,
Numerical update means;
Random number storage means for taking in and storing, as a random value, numerical data output from the numerical update means based on an input of a predetermined signal,
A first setting which enables new numerical data to be taken in and stored as a random value in the random value storage means when a predetermined signal is input while the random value is stored in the random value storage means; And when a predetermined signal is input while the random number value is stored in the random number value storage means, it is impossible to take in and store new numerical data as a random number value in the random number value storage means. Random number storage setting means (for example, a portion shown in [Operation of Random Number]) to be set to one of the two settings.
According to this configuration, it is possible to prevent an unintended random number value from being captured.

The microcomputer is
A random number circuit (for example, a random number circuit 212) for generating numerical data to be a random number value;
Setting content storage means (for example, a portion shown in FIG. 12) having a storage area capable of storing a setting related to the random number circuit;
An initial value setting means (for example, a part shown in FIG. 23) for setting an initial value indicating initial setting contents in at least a part of a storage area of the setting content storage means when the microcomputer is started.
According to this configuration, it is possible to prevent the numerical data that is a random number value from being updated with an unintended setting.

The microcomputer is
Storage area setting means (for example, setting of a program end address shown in FIG. 16) for setting a storage area in which a user program is stored when the microcomputer is started;
User program execution means (for example, CPU 207) for executing processing according to a user program stored in the storage area stored by the storage area setting means;
Abnormality control executing means for executing abnormality control when the user program executing means calls a program stored in an area other than the storage area set by the storage area setting means; (For example, a portion shown in FIG. 21),
The predetermined range includes at least the address of the area where the user program is stored (for example, the portion shown in FIG. 22).
According to this configuration, execution of an unauthorized program can be prevented.

The microcomputer is
A start-time interrupt prohibiting unit (for example, a part that performs the processing of Sa1 in FIG. 5) that prohibits an interrupt when the microcomputer is started;
A user program executing means (for example, CPU 207) for executing processing according to the user program;
A pre-setting interrupt prohibition unit (for example, executing a process of prohibiting an interrupt after the user program execution unit starts executing the process according to the user program and before the interrupt permission unit executes the setting related to the interrupt (for example, A part that performs the processing of Sa1 before Sa16a, Sa20a, and Sa26a in FIG. 5).
According to this configuration, execution of an unintended interrupt process can be prevented in advance.

The microcomputer is
Data storage means (for example, portions shown in FIGS. 12 and 14) which are referred to when the microcomputer is started and have a storage area capable of storing data for setting functions of the microcomputer;
Data setting means (for example, CPU 207) for setting the data in a storage area of the data storage means,
In the storage area of the data storage means, an unused area in which the data setting means does not set any function based on the value set in the storage area (for example, a random number circuit operation mode setting (related symbol name: HRDMD) ) Includes bits 3 of HEMDD, bits 5-7 of HSYSCNT in the system settings (related symbol name: HSYSCNT),
The activation restricting means restricts activation of the microcomputer when a specific value is set in the unused area (for example, a portion shown in FIG. 22).
According to this configuration, it is possible to prevent unintended settings from being made.

In order to solve the above-mentioned problems, a gaming machine of the present invention
In a gaming machine (for example, slot machine 1) capable of performing a game,
Storage means (for example, ROM 208) for storing a program;
A microcomputer (for example, a portion shown in FIG. 11) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, a portion shown in FIG. 12) executed in response to the occurrence of the interrupt,
The microcomputer includes:
Interrupt permitting means (for example, portions shown in FIGS. 5 and 6) for executing a process for permitting an interrupt after executing a process for performing a setting relating to an interrupt;
Interrupt processing executing means (for example, portions shown in FIGS. 8 and 9) for executing processing according to an interrupt program based on the interrupt when the interrupt is permitted;
Address storage means (for example, a portion shown in FIG. 13) having a storage area capable of storing an address of an interrupt program in the storage means;
Determining means (for example, a portion shown in FIG. 22) for determining whether or not an address stored in a storage area of the address storing means is within a predetermined range when the microcomputer is started;
A start restricting unit (for example, a part shown in FIG. 22) for restricting the start of the microcomputer when the judging unit judges that the address of the interrupt program is not within a predetermined range.
According to this configuration, execution of an unintended interrupt process can be prevented in advance.

The interrupt permitting means specifies, as settings relating to the interrupt, a time interval for an interrupt occurring at a predetermined cycle, and performs a setting for starting a timer for measuring the time interval from an initial value (see FIG. 27 and FIG. 28).
According to this configuration, execution of an unintended interrupt process can be prevented in advance.

The microcomputer is
Setting content storage means (for example, a portion shown in FIGS. 34 to 36) having a storage area capable of storing settings related to interrupts;
Initial value setting means (for example, portions shown in FIGS. 23 and 32) for setting an initial value indicating initial setting contents in at least a part of a storage area of the setting content storage means when the microcomputer is started. .
According to this configuration, it is possible to prevent in advance that the interrupt process is executed with an unintended setting.

In order to solve the above-mentioned problems, a gaming machine of the present invention
In a gaming machine (for example, slot machine 1) capable of performing a game,
Storage means (for example, ROM 208) for storing a program;
A microcomputer (for example, a portion shown in FIG. 11) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, a portion shown in FIG. 12) executed in response to the occurrence of the interrupt,
The microcomputer includes:
Interrupt processing executing means (for example, portions shown in FIGS. 8 and 9) for executing processing according to an interrupt program based on the interrupt when the interrupt is permitted;
Fluctuation data storage means (for example, a RAM 41c) for storing fluctuation data which fluctuates in accordance with execution of processing according to the program;
Initialization processing executing means (for example, a part performing the processing in FIGS. 5 and 6) for executing an initialization processing for initializing at least a part of the storage contents of the fluctuation data storage means when an initialization condition is satisfied; ,
Interrupt inhibiting means (for example, a part for performing the processing of Sa1 in FIG. 5) for inhibiting an interrupt when the initialization processing is being executed;
Address storage means (for example, a portion shown in FIG. 13) having a storage area capable of storing an address of an interrupt program in the storage means;
Determining means (for example, a portion shown in FIG. 22) for determining whether or not an address stored in a storage area of the address storing means is within a predetermined range when the microcomputer is started;
A start restricting unit (for example, a part shown in FIG. 22) for restricting the start of the microcomputer when the judging unit judges that the address of the interrupt program is not within a predetermined range.
According to this configuration, execution of an unintended interrupt process can be prevented in advance.

The predetermined storage area includes an unused area (for example, a part shown in FIG. 19),
A plurality of conditions (for example, the conditions of initialization 1 to 4) are set as initialization conditions,
The data control unit initializes the data of the storage area including the unused area according to the type of the established initialization condition (for example, a portion indicated by [about initialization]).
According to this configuration, execution of an unintended interrupt process can be prevented in advance.

The microcomputer includes external data output processing means (for example, a main control unit 41) for executing data output processing for outputting data to the outside,
The interrupt prohibiting unit prohibits the interrupt when the external data output processing unit is executing the data output process (for example, a portion that executes the interrupt prohibition before Sm3 in FIG. 10).
According to this configuration, it is possible to prevent output of unintended data.

In order to solve the above-mentioned problems, a gaming machine of the present invention
In a gaming machine (for example, slot machine 1) capable of performing a game,
Storage means (for example, ROM 208) for storing a program;
A microcomputer (for example, a portion shown in FIG. 11) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, a portion shown in FIG. 12) executed in response to the occurrence of the interrupt,
The microcomputer includes:
Interrupt processing executing means (for example, portions shown in FIGS. 8 and 9) for executing processing according to an interrupt program based on the interrupt when the interrupt is permitted;
Power supply stop time processing means for executing a power supply stop time process for backing up the execution state of the processing by the microcomputer when the power supply to the gaming machine is stopped (for example, a portion shown in [Modification]) When,
Recovery means (for example, a portion shown in [Modification]) for restarting execution of processing according to the program based on the execution state of the backed up processing;
Address storage means (for example, a portion shown in FIG. 13) having a storage area capable of storing an address of an interrupt program in the storage means;
Determining means (for example, a portion shown in FIG. 22) for determining whether or not an address stored in a storage area of the address storing means is within a predetermined range when the microcomputer is started;
Starting restriction means (for example, a part shown in FIG. 22) for restricting activation of the microcomputer when the determination means determines that the address of the interrupt program is not within a predetermined range;
Backing up information indicating whether or not interrupts are permitted in the power supply stop processing, and determining whether to permit interrupts based on the backed up information when restarting the processing by the recovery means. Is set (for example, the portion shown in [Modification]).
According to this configuration, execution of an unintended interrupt process can be prevented in advance.

The program includes a non-maskable interrupt program (for example, a portion related to the NMI interrupt in FIGS. 12 to 15) that is executed in response to the occurrence of a non-maskable interrupt in which the interrupt cannot be prohibited based on the input of the power supply stop signal. Including
When a non-maskable interrupt occurs, the microcomputer executes a non-maskable interrupt process executing means (for example, the NMI shown in FIGS. 12 to 15, 32, and 34) that executes a process according to the non-maskable interrupt program. Part related to interrupts, part shown in [Modification]),
The power supply stop processing includes processing according to the non-maskable interrupt program (for example, a portion shown in [Modification]),
The storage area of the address storage means contains the address of the non-maskable interrupt program (for example, the portion shown in FIG. 13),
The determining means determines at the time of starting the microcomputer whether or not the address of the non-maskable interrupt program stored in the storage area of the address storage means is within a predetermined range (for example, as shown in [Modification]). part),
The activation restricting means restricts the activation of the microcomputer when the determining means determines that the address of the non-maskable interrupt program is not within a predetermined range (for example, a portion shown in [Modification]).
According to this configuration, execution of an unintended interrupt process can be prevented in advance.

The program includes a non-maskable interrupt program (for example, a portion related to the NMI interrupt in FIGS. 12 to 15) that is executed in response to the occurrence of a non-maskable interrupt in which the interrupt cannot be prohibited based on the input of the power supply stop signal. Including
The microcomputer includes a non-maskable interrupt processing execution means (for example, a portion shown in [Modification]) that executes a process according to a non-maskable interrupt program when an unmaskable interrupt occurs,
The power supply stop processing includes processing according to the non-maskable interrupt program (for example, a portion shown in [Modification]),
The period from when the non-maskable interrupt occurrence condition is satisfied to when the non-maskable interrupt occurs is shorter than the period until the interrupt generation condition is satisfied and the interrupt is generated (for example, [Modification] Part shown).
According to this configuration, it is possible to suitably execute the power supply stop processing.

  Note that the present invention may have only the matters specifying the invention described in the claims of the present invention, or may have configurations other than the matters specifying the invention together with the matters specifying the invention described in the claims of the present invention. It may be something.

It is a front view of the slot machine to which the present invention is applied. FIG. 3 is an internal structural diagram of the slot machine. It is a figure showing the symbol arrangement of a reel. FIG. 3 is a block diagram illustrating a configuration of a slot machine. 9 is a flowchart illustrating control contents of an initialization process executed by the main control unit at the time of startup. 9 is a flowchart illustrating control contents of an initialization process executed by the main control unit at the time of startup. It is a flowchart which shows the control content of the game process which a main control part performs after a setting change process. 9 is a flowchart showing the control contents of a timer interrupt process (main) executed by the main control unit at regular intervals. 9 is a flowchart showing the control contents of a timer interrupt process (main) executed by the main control unit at regular intervals. 9 is a flowchart illustrating control contents of a power interruption process (main) executed in response to a main controller detecting a power interruption in a timer interruption process (main). FIG. 2 is a block diagram illustrating a configuration of a microcomputer. FIG. 3 is an explanatory diagram showing an address map of a memory space. FIG. 4 is an explanatory diagram showing a vector table address map. FIG. 4 is an explanatory diagram showing a list of HW (hardware) parameters. FIG. 9 is an explanatory diagram showing reset period / INP terminal setting. FIG. 4 is an explanatory diagram showing contents of a program end address. FIG. 9 is an explanatory diagram showing a setting example of a program end address. FIG. 4 is an explanatory diagram showing a RAM access prohibition address. FIG. 5 is an explanatory diagram showing an example of setting a RAM access prohibition address. FIG. 9 is an explanatory diagram showing a SW status. FIG. 4 is an explanatory diagram showing conditions under which an illegal access reset occurs. FIG. 4 is an explanatory diagram showing conditions under which the microcomputer does not start. FIG. 4 is an explanatory diagram showing a change in operation due to a reset factor of the microcomputer. FIG. 4 is an explanatory diagram showing a list of internal function registers. FIG. 4 is an explanatory diagram showing contents of a RAM protect register. FIG. 4 is an explanatory diagram illustrating an input example of a CTC clock. FIG. 4 is an explanatory diagram showing the contents of a CTC control register. FIG. 4 is an explanatory diagram showing the contents of a CTC data register. FIG. 4 is an explanatory diagram showing a method of clearing a WDT. FIG. 4 is an explanatory diagram showing a WDT control register. FIG. 4 is an explanatory diagram showing a WDT clear register. It is a block diagram of an interruption controller. FIG. 9 is an explanatory diagram illustrating an example of an interrupt processing procedure. FIG. 4 is an explanatory diagram showing the contents of an interrupt request register. FIG. 4 is an explanatory diagram showing the contents of an interrupt permission register. FIG. 4 is an explanatory diagram showing the contents of an interrupt priority register. FIG. 4 is an explanatory diagram showing the contents of an external signal input / reset factor register. FIG. 4 is an explanatory diagram showing a periodic reset monitor register. FIG. 3 is an explanatory diagram showing a register configuration. FIG. 4 is an explanatory diagram showing a program status word. FIG. 4 is an explanatory diagram showing a change in the value of an SP (stack pointer).

[Slot machine configuration example]
As shown in FIG. 1, the slot machine 1 of the present embodiment includes a housing 1a having an open front, and a front door 1b rotatably supported at a side end of the housing 1a. ing.

  As shown in FIG. 2, inside the housing 1a of the slot machine 1 of the present embodiment, reels 2L, 2C, 2R (hereinafter, left reel, middle reel, right Reels) are arranged side by side in the horizontal direction, and as shown in FIG. 1, three consecutive symbols among the symbols arranged on the reels 2L, 2C, 2R pass through the transparent window 3 provided on the front door 1b. It is arranged so that it can be seen.

  As shown in FIG. 3, "black 7", "net 7 (hatched in the figure)", "white 7", "BAR", "replay", A plurality of types of mutually identifiable symbols such as “plum”, “watermelon”, “cherry”, “bell”, and “orange” are drawn in a predetermined order, each of which includes 21 symbols. The symbols drawn on the outer peripheries of the reels 2L, 2C, 2R are displayed in upper, lower, middle, and lower tiers, respectively, in a transparent window 3 provided substantially at the center of the reel panel 1c of the front door 1b.

  The reels 2L, 2C, and 2R are provided correspondingly and rotated by reel motors 32L, 32C, and 32R (see FIG. 4), so that the symbols of the reels 2L, 2C, and 2R are continuously displayed on the see-through window 3. While the display is changing, the rotation of each of the reels 2L, 2C, and 2R is stopped, so that three consecutive symbols are derived and displayed on the see-through window 3 as a display result.

  Inside the reels 2L, 2C, 2R, a reel sensor 33L, 33C, 33R for detecting a reference position and a reel LED 55 for irradiating the reels 2L, 2C, 2R from the back are provided for the reels 2L, 2C, 2R, respectively. , Are provided. The reel LED 55 includes twelve LEDs corresponding to three consecutive symbols on the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  At a position corresponding to each of the reels 2L, 2C, 2R on the front door 1b, there is provided a horizontally long rectangular see-through window 3 which allows the reels 2L, 2C, 2R to be seen from the front side. The reels 2L, 2C, 2R can be visually recognized from the player side via the player.

  In the front door 1b, a medal insertion part 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and a credit (the number of medals stored as a game value owned by the player) are used. The MAXBET switch 6, which is operated when setting the maximum bet number (3 in any of the game states in the present embodiment) among the predetermined number of bets determined according to the game state, stored as credits Settlement switch 10 that is operated to settle the medals used for setting the number of medals and the number of bets (return the medals used for setting the number of credits and bet), and start that is operated when the game is started. A switch 7, a stop switch 8L, 8C, 8R operated when stopping the rotation of each of the reels 2L, 2C, 2R; 56 are respectively provided so as to be operated by the player.

  In the present embodiment, of the three reels 2L, 2C, and 2R that have started rotating, the reel that stops first is referred to as a first stop reel, the stop is the first stop, and the stop operation is the first stop reel. It is referred to as one stop operation (or first stop). Similarly, the reel that stops second is referred to as a second stop reel, the stop is referred to as a second stop, and the stop operation is referred to as a second stop operation (or a second stop). Also, the reel that stops third is referred to as a third stop reel, the stop is referred to as a third stop or a final stop, and the stop operation is referred to as a third stop operation (or a third stop).

  On the front door 1b, a credit indicator 11 displaying the number of medals stored as credits, the number of medals paid out upon occurrence of a prize, an error code indicating the content of the error when an error occurs, and the like are displayed. The game auxiliary display 12, the 1 BET LED 14 for notifying that the bet amount is set to 1 by lighting, the 2BET LED 15 for notifying that the bet amount is set to 2 by lighting, and the lighting to indicate that 3 bets are set The 3BET LED 16 for notifying, the insertion request LED 17 for notifying the state in which medals can be inserted by lighting, the start valid LED 18 for notifying by lighting that the game start operation by the operation of the start switch 7 is effective, the weight (previous game start) Waiting for reel rotation to start because a certain period has not elapsed since Weight in LED19 for notifying by lighting a a is that during the game display section 13 in the replay LED20 is provided for informing is provided by lighting the effect that during replay game, which will be described later.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying by lighting that the setting operation of the bet amount by operating the MAXBET switch 6 is valid, and the stop switches 8L, 8C, Inside the 8R, left, middle, and right stop valid LEDs 22L, 22C, and 22R (see FIG. 4) are provided to notify by light that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is valid. Have been.

  Below the stop switches 8L, 8C, 8R on the front door 1b, a lower panel 1d on which the title of the slot machine 1, a payout table 1 described later, and the like are printed is provided.

  Inside the front door 1b, a reset switch 23 for detecting a reset operation for canceling an error state to be described later and a hit state to be described later by a predetermined key operation. A set value display 24 for displaying a set value at that time, and enabling / disabling a stop function for controlling a stop state (a state in which the progress of the game is restricted until a reset operation is performed) at the end of BB described later. Switch 36a for selecting the automatic settlement function (automatic settlement function for controlling the settlement (return) of medals stored as credits regardless of the operation of the player) at the end of BB described later. The automatic settlement switch 36b for selecting invalidity and the flow path of medals inserted from the medal insertion section 4 are connected to a hopper tank 34a described later provided inside the housing 1a (see FIG. 2). ) Side or the medal payout opening 9 side, and has a flow path switching solenoid 30, and an inserted medal sensor 31 for detecting medals which are inserted from the medal input section 4 and flow down to the hopper tank 34 a side. A medal selector (not shown) and a door open detection switch 25 (see FIG. 4) for detecting the open state of the front door 1b are provided.

  As shown in FIG. 2, a reel sensor 33L capable of detecting the reel reference positions of the reels 2L, 2C, 2R, the reel motors 32L, 32C, 32R, and the reels 2L, 2C, 2R is provided inside the housing 1a. , 33C, 33R (see FIG. 4), an external output board 1000 for outputting an external output signal, a hopper tank 34a for storing medals inserted from the medal insertion section 4, and stored in the hopper tank 34a. A hopper unit 34 including a hopper motor 34b for paying out tokens from the medal payout exit 9, a payout sensor 34c for detecting medals paid out by driving the hopper motor 34b, and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 for storing medals overflowing from the hopper tank 34a is provided. Inside the overflow tank 35, there is provided a full tank sensor 35a which is provided at a height at which a predetermined amount of stored medals can be detected and is made of a pair of left and right conductive members which are separated from each other. It is possible to detect that the medal storage amount stored inside becomes greater than or equal to a predetermined amount when conducting by contact through the medal stored in the inside, that is, that the overflow tank is full. Has become.

  On the front face of the power supply box 100, it functions as a setting key switch 37 for switching to a setting change state or a setting confirmation state, and functions as a reset switch for canceling an error state or a stop state in a normal state. A reset / setting switch 38 functioning as a setting switch for changing a setting value of a winning probability (a payout rate) of an internal lottery described later, and a power switch 39 operated when the power is turned on / off are provided. .

  When playing a game in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or the number of bets is set using credits. To use the credit, the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the game state is set, the pay line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the game can be started. Become. In the present embodiment, the pay line LN is activated when the prescribed number of bets is set to three regardless of the game state and the prescribed number of bets is set regardless of the gaming state. If medals are inserted in more than the maximum number out of the specified number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether the combination of the symbols displayed in the perspective windows 3 of the reels 2L, 2C, and 2R is a combination of the winning symbols. In the present embodiment, as shown in FIG. 1, only the winning line LN set across the middle row of the reel 2L, the middle section of the reel 2C, and the middle section of the reel 2R, that is, the middle row, is a winning line. It is defined as. In the present embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

  Further, in the present embodiment, in order to make it easy to recognize that the combination of the symbols constituting the prize is arranged on the prize line LN, the invalid lines LM1 to LM4 are set separately from the prize line LN. The invalid lines LM1 to LM4 do not determine the winning based on the combination of the symbols aligned with the invalid lines LM1 to LM4. When the combination of the symbols constituting the specific prize is arranged on the winning line LN, the invalid lines are invalidated. When a combination of symbols (for example, bell-bell-bell) that wins when the winning line LN is aligned with any of the LM1 to LM4 is arranged, a symbol forming a specific winning on the winning line LN is formed. This is to make it easy to recognize that the combination is complete. In the present embodiment, as shown in FIG. 1, the upper line of the reel 2L, the upper line of the reel 2C, and the upper line of the reel 2R, that is, the invalid line LM1 and the reel 2L The lower line, the lower line of the reel 2C, the lower line of the reel 2R, that is, the invalid line LM2 set across the symbols arranged horizontally in the lower line, the upper line of the reel 2L, the middle line of the reel 2C, the lower line of the reel 2R, that is, the lower line Four types of invalid line LM3, invalid line LM4 set across the symbols lined up rightward, that is, the invalid line LM3 set across the symbols arranged in the lower row of the reel 2L, the middle row of the reel 2C, and the upper row of the reel 2R. It is defined as LM.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, 2R rotate, and the symbols on the reels 2L, 2C, 2R change continuously. When any of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the see-through window 3.

  When one of the reels 2L, 2C, and 2R is stopped, one game is completed, and a predetermined symbol combination (hereinafter, also referred to as a combination) on the winning line LN is displayed on each of the reels 2L, 2C, and 2R. When the game stops, a prize is generated, and a predetermined number of medals are awarded to the player according to the prize, and are added to the credit. When the number of credits reaches the upper limit (50 in this embodiment), medals are paid directly from the medal payout port 9 (see FIG. 1). Further, when a combination of symbols accompanied by a transition of the game state is stopped as a result of displaying the reels 2L, 2C, 2R on the payline LN, the game state is shifted to a game state corresponding to the combination of the symbols.

  In the present embodiment, the game starts when the operation of the start switch 7 is detected in a state where the operation of the start switch 7 is valid, and ends when all the reels stop. In addition, one unit of control (game control) for executing the game is started when all controls accompanying the end of the previous game are completed, and when all controls accompanying the end of the game are completed. finish.

  Further, in the slot machine 1 according to the present embodiment, after the game is started and each of the reels 2L, 2C, and 2R is rotated to start changing symbols, any one of the stop switches 8L, 8C, and 8R is operated. When operated, the rotation of the reel corresponding to the stop switch 8L, 8C, 8R is stopped, and the symbol is stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (millisecond).

  The reels 2L, 2C, and 2R rotate 80 times per minute, and change the symbols for 80 × 21 (the number of symbols per reel) = 1680 frames. Therefore, a maximum of four symbols are drawn during 190 ms. You can do it. In other words, the symbols that can be selected as the stop symbols are the symbols displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols four frames away from the symbols, for a total of five frames.

  Therefore, for example, when one of the stop switches 8L, 8C, and 8R is operated and the symbol displayed on the lower row of the reel corresponding to the stop switch is used as a reference, the symbol from the symbol to four frames ahead Since the symbol can be displayed in the lower row, when one of the stop switches 8L, 8R is operated in each of the reels 2L, 2C, 2R, the symbol displayed in the middle row of the reel corresponding to the stop switch is operated. Can be displayed on the winning line LN.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The drive power for the electrical components that constitute the slot machine 1 is generated by the power supply board 101 and supplied to each unit.

  A power supply of AC100V is externally supplied to the power supply board 101, and a DC voltage required for driving the electric components constituting the slot machine 1 is generated from the power supply of AC100V, and the game control board 40 and the game control board 40 Is supplied to the effect control board 90 connected via the. In addition, a command transmission line from the main control unit 41 to the sub-control unit 91, which will be described later, and a power supply line for supplying power from the game control board 40 to the effect control board 90 are connected via a system of cables and connectors. By connecting all of the connectors that connect these cables to the respective boards, each part of the effect control board 90 becomes operable, and a state in which a command from the main control unit 41 can be received. Become. For this reason, unless the command transmission line for transmitting a command from the main control unit 41 is connected to the effect control board 90, power is not supplied to the effect control board 90, and only the effect control board 90 operates. I will not do it.

  Further, the hopper motor 34b, the dispensing sensor 34c, the full tank sensor 35a, the setting key switch 37, the reset / setting switch 38, and the power switch 39 are connected to the power supply board 101.

  The game control board 40 includes the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, 8R, the settlement switch 10, the reset switch 23, the hitting switch 36a, the automatic settlement switch 36b, the inserted medal sensor 31, and the door opening. The detection switch 25, the reel sensors 33L, 33C and 33R are connected, and the payout sensor 34c, the full tank sensor 35a, the setting key switch 37, and the reset / setting switch 38 are connected via the power supply board 101, The detection signals of these connected switches are input.

  In addition, the game control board 40 includes the above-mentioned credit indicator 11, game assist indicator 12, payout indicators 13, 1 to 3 BET LEDs 14 to 16, insertion request LED 17, start valid LED 18, wait LED 19, replay LED 20, BET The switch valid LED 21, the left, middle, and right stop valid LEDs 22L, 22C, and 22R, the set value display 24, the flow path switching solenoid 30, and the reel motors 32L, 32C, and 32R are connected to each other. The hopper motor 34b is connected, and these electric components are driven based on the control of a main control unit 41 described later mounted on the game control board 40.

  The game control board 40 includes a main control unit 41, a random number generation circuit 42, a sampling circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, a power cutoff detection circuit 48, and a reset circuit 49. Is installed.

  The main control unit 41 is configured by a one-chip microcomputer, and includes a main CPU 41a, a ROM 41b, a RAM 41c, an I / O port 41d, and a random number generation circuit 42. The main control section 41 executes a program stored in the ROM 41b to perform processing relating to the progress of the game, and directly or indirectly controls each section of a control circuit mounted on the game control board 40.

  The random number generation circuit 42 is configured by a counter that counts up and updates the value each time a predetermined number of pulses are generated, and the sampling circuit 43 acquires the numerical value counted by the random number generation circuit 42. In the random number generation circuit 42, a range of numerical values to be counted for each type of random number is defined, and in the present embodiment, the range is set to 0 to 65535. The main CPU 41a sends the instruction to the sampling circuit 43 in accordance with the processing, thereby acquiring the numerical value indicated by the random number generation circuit 42 as a random number value (hereinafter, this function is referred to as a hardware random number function). The random numbers for the internal lottery described later are not directly used as the random numbers extracted by the hardware random number function, but are processed and used by software. The main CPU 41a also has a function of updating the value of a specific register by the above-described timer interrupt processing (main) and acquiring the updated numerical value as a random number (hereinafter, this function is referred to as a software random number function). .

  The switch detection circuit 44 takes in a detection signal input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits it to the main control section 41. The motor drive circuit 45 transmits the motor drive signal output from the main control unit 41 to the reel motors 32L, 32C, 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40. The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1, and when detecting a voltage drop, outputs a voltage drop signal indicating this to the main control unit 41. The reset circuit 49 supplies a system reset signal to the main control unit 41 when the power supply is unstable such as when the power is turned on or when the power is turned off.

  The CPU 41a of the main control unit 41 executes processing for controlling the progress of the game in the slot machine 1 by executing the program read from the ROM.

  As described above, in the main control unit 41, the CPU 41a executes control according to the program stored in the ROM 41b. Therefore, hereinafter, the execution (or processing) of the main control unit 41 (or the CPU 41a) means More specifically, the CPU 41a executes control according to a program. The same applies to the microcomputer mounted on a board other than the game control board 40.

  The RAM 41c provided in the main control unit 41 provides a work area for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power supply. That is, even if the power supply to the slot machine is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period. In the present embodiment, all areas of the RAM 41c are used as backup RAMs, and even if power supply to the slot machine is stopped, all contents of the RAM 41c are stored for a predetermined period.

  The ROM 41b provided in the main control unit 41 stores various selection data, table data, and the like used for controlling the progress of the game. For example, the ROM 41b stores data constituting a plurality of determination tables, determination tables, setting tables, and the like prepared for the CPU 41a to perform various determinations, determinations, and settings. The ROM 41b stores table data constituting a plurality of command tables used for the CPU 41a to transmit control signals serving as various control commands from the game control board 40.

  In the RAM 41c provided in the main control section 41, a game control data holding area is provided as an area for holding various data used for controlling the progress of a game in the slot machine 1 and the like. For example, a DRAM is used as the RAM 41c, and a refresh operation for maintaining stored data contents is required. The CPU 41a has a built-in refresh register for performing this refresh operation. For example, the refresh register is composed of 8 bits, and the lower 7 bits are automatically incremented each time the CPU 41a fetches an instruction from the ROM 41b. Therefore, the update of the stored value in the refresh register is performed every execution time of one instruction in the CPU 41a.

  The main control unit 41 transmits various commands to the sub control unit 91. The command transmitted from the main control unit 41 to the sub control unit 91 is transmitted in only one direction, and the command is not transmitted from the sub control unit 91 to the main control unit 41.

  The main control unit 41 receives detection states of various switches connected to the game control board 40 from an input port. Then, the main control unit 41 executes a basic process of shifting stepwise according to the detection states of various switches input from these input ports.

  Further, the main control unit 41 can execute the interrupt process by interrupting the basic process when an interrupt occurs. In the present embodiment, a timer interrupt process (main), which will be described later, is executed at fixed time intervals (about 0.56 ms in the present embodiment).

  In addition, the main control unit 41 is set to prohibit other interrupts during execution of the interrupt process, and when a plurality of interrupts occur simultaneously, the main control unit 41 gives priority to a predetermined order. Interrupts to execute are set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt occurs at that time. It will be.

  The effect switch 56 is connected to the effect control board 90, and a detection signal of the effect switch 56 is input thereto.

  The rendering control board 90 is connected to rendering devices such as a liquid crystal display 51 (see FIG. 1), a rendering effect LED 52, speakers 53 and 54, and the above-mentioned reel LED 55 arranged on the front door 1b of the slot machine 1. These effect devices are driven based on control by a sub-control unit 91 described later mounted on the effect control board 90.

  In the present embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, and the reel LED 55. However, an output control unit that directly performs output control of the effect device separately from the sub-control unit 91 is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output pattern of the rendering device may be determined by the sub-control unit 91, and the output control unit may control the output of the rendering device based on the output pattern determined by the sub-control unit 91. In such a configuration, the sub-control unit 91 and the output The output control of the effect device is performed by both of the control units.

  Further, in the present embodiment, the liquid crystal display 51, the effect LED 52, the speakers 53 and 54, and the reel LED 55 are illustrated as the effect devices. However, the effect devices are not limited thereto, and may be, for example, mechanically driven. A display device, a mechanically driven role object, or the like may be applied as the rendering device.

  The effect control board 90 includes a microcomputer including a sub CPU 91a, a ROM 91b, a RAM 91c, and an I / O port 91d, like the main control section 41, and controls the effect. A display control circuit 92 for controlling the display of the liquid crystal display 51 connected to the display device; an effect driving LED 52; an LED drive circuit 93 for controlling the drive of the reel LED 55; an audio output circuit 94 for controlling the audio output from the speakers 53 and 54; A reset circuit 95 that supplies a reset signal to the sub CPU 91a when the power is turned on or when an initialization command from the sub CPU 91a is not input for a predetermined time, and detects a detection signal input from the effect switch 56 connected to the effect control board 90. Switch detection circuit 96 outputs time information including date information and time information Clock device 97, a power supply voltage supplied to the slot machine 1, and when detecting a voltage drop, a power cutoff detection circuit 98 that outputs a voltage drop signal indicating the voltage drop to the sub CPU 91a, and other circuits. The sub CPU 91a receives a command transmitted from the game control board 40, performs various controls for performing an effect, and controls each part of a control circuit mounted on the effect control board 90. Control directly or indirectly.

  The reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that supplies a system reset signal to the main control unit 41 in the game control board 40. When the power is turned on, the sub-control unit 91 executes the main control. It is designed to be started earlier than the section 41. On the other hand, in the power interruption detection circuit 98, the voltage at which the voltage drop signal is output is set lower than that of the power interruption detection circuit 48 which outputs the voltage drop signal to the main control unit 41 in the game control board 40. In, the sub-control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  The sub-control unit 91 has an interrupt function, like the main control unit 41, and generates an interrupt when a command is received from the main control unit 41 to acquire the command transmitted from the main control unit 41. , Execute the command reception interrupt processing stored in the buffer. Further, the sub-control unit 91 executes a timer interrupt process (sub), which will be described later, by generating an interrupt every time the number of input system clocks reaches a certain number, that is, at certain intervals.

  Further, unlike the main control unit 41, when an interrupt occurs based on the reception of a command, the sub-control unit 91 interrupts the timer interrupt process (sub) even during execution of the process. , The command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur simultaneously.

  The backup power is also supplied to the sub-control unit 91 at the time of a power failure, and the data stored in the RAM 91c is retained while the backup power is supplied. That is, even if the power supply to the slot machine is stopped, at least a part of the contents of the RAM 91c is stored for a predetermined period. In the present embodiment, all areas of the RAM 91c are used as backup RAMs, and even if power supply to the slot machine is stopped, all contents of the RAM 91c are stored for a predetermined period. In the present embodiment, all areas of the RAM 91c are used as backup RAMs, and even if power supply to the slot machine is stopped, all contents of the RAM 91c are stored for a predetermined period.

[Settings]
In the slot machine 1 of the present embodiment, the payout rate of medals changes according to the set value. More specifically, the payout rate of medals is changed by using a winning probability according to a set value in an internal lottery described later. The set value is made up of six levels from 1 to 6, where 6 is the highest payout rate and the payout rate decreases as the value decreases in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in the order of 5, 4, 3, 2, and 1, the advantage gradually decreases.

  In order to change the set value, it is necessary to turn on the power of the slot machine 1 after turning on the setting key switch 37. When the setting key switch 37 is turned on and the power is turned on, the set value read from the RAM 41c is displayed as a display value on the set value display 24, and the set value can be changed by operating the reset / setting switch 38. Move to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated one by one (when further operated from the setting 6, the display returns to the setting 1). . Then, when the start switch 7 is operated, the display value is determined as the set value. Then, when the setting key switch 37 is turned off, the determined display value (set value) is stored in the RAM 41c of the main control unit 41, and the state shifts to a state where the game can proceed.

  Further, in order to confirm the set value, after the game is over, the setting key switch 37 may be turned on with no bet amount set. When the setting key switch 37 is turned on in such a situation, the setting value read from the RAM 41c is displayed on the setting value display 24, and the state shifts to a setting check state in which the setting value can be checked. In the setting confirmation state, the progress of the game is not possible, and by setting the setting key switch 37 to the off state, the setting confirmation state ends and the game returns to a state in which the game can proceed.

  In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not the voltage drop signal from the power interruption detection circuit 48 is detected each time the timer interrupt processing (main) is performed. A power failure determination process is performed, and when it is determined in the power failure determination process that a voltage drop signal has been detected, a power failure process (main) is performed. In the power interruption processing (main), the destruction diagnosis data (5AH in this embodiment) in which any bit becomes 1 (ie, specific data other than 0) is stored in the RAM 41c, and the data is stored in all areas of the RAM 41c. The processing for calculating the RAM parity adjustment data so that the RAM parity based on the stored data becomes 0, and storing the data in the RAM 41c is performed. Note that the RAM parity is a value calculated as an exclusive OR of values stored in respective bits of a corresponding area (all areas in the present embodiment) of the RAM 41c. Therefore, if the RAM parity based on the data stored in all the areas of the RAM 41c is 0, the RAM parity adjustment data is 0, and the RAM parity based on the data stored in all the areas of the RAM 41c is 1. For example, the RAM parity adjustment data is 1.

  The main control unit 41 calculates the RAM parity based on the data stored in all the areas of the RAM 41c at the time of the start, regardless of whether the system reset or the user reset is performed. And the processing state of the main control unit 41 is returned to the state before the power failure based on the data stored in the RAM 41c, provided that the RAM parity is 0 and the value of the destruction diagnosis data is also correct. However, if the RAM parity is not 0 (1) or the value of the destructive diagnosis data is incorrect, it is determined that the RAM is abnormal, and the RAM abnormal error code is set in the register to control the RAM abnormal error state. Then, the progress of the game is disabled. Note that, unlike the normal error state, the RAM abnormal error state is not released even when the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the above-described setting change state. Will not be released until the

  In the present embodiment, all data stored in the RAM 41c is retained by the backup power supply even during a power failure, and the main control unit 41 determines that the data in the RAM 41c is normal when the power is turned on. In such a case, the control state is restored to the state before the power failure based on the data stored in the RAM 41c. However, of the data stored in the RAM 41c, only the data necessary for returning to the control state at the time of a power failure is backed up, and It may be configured to return to the control state before the power failure based on the data backed up at the time of turning on.

  In addition, when returning to the control state before the power failure when the power is turned on, it is not necessary to return all the control states to the control state before the power failure, and the minimum control state that does not disadvantage the player It is not necessary to restore all the states of the input ports to the state before the power failure, for example.

[About initialization]
Next, initialization of the RAM 41c of the main control unit 41 will be described. The storage area of the RAM 41c of the main control unit 41 is divided into an important work, a non-preserved work, a general work, a special work, an unused area, and a stack area.

  The important work stores data that is inconvenient to be initialized, such as various display devices, LED display data, I / O input / output data, and a game time counter, and an RT flag and the number of remaining RT games described later. Work. The unsaved work is a work that holds the state of various switches, and a value is always set at the time of startup, regardless of whether data in the RAM 41c is destroyed. The general work is a work in which data that can be initialized at the end of BB, such as a stop control table, a stop symbol, the number of paid out medals, the total number of paid out medals in BB, and a game state flag described later are stored. The special work is a work in which data, such as various software random numbers, that is initialized only before the setting is started is stored. The unused area is an unused area in the storage area of the RAM 41c, and is initialized if any one of a plurality of initialization conditions described later is satisfied. The stack area is an area in which data saved from the register of the main control unit 41 is stored. The unused stack area is, like the unused area, one of a plurality of initialization conditions described later. However, if the condition is satisfied, the initialization is performed. However, the used stack area is not initialized for the continuation of the program.

  In the present embodiment, the main control unit 41 starts the data processing when the setting key switch 37 is turned on, when a RAM error occurs, when BB ends, and when the setting key switch 37 is turned off, the data in the RAM 41c. Is not destroyed, when the five initialization conditions at the end of one game are satisfied, four types of initialization with different areas initialized according to each initialization condition are performed.

  Initialization 1 is a state in which the setting key switch 37 is turned on at the time of start-up, and is an initialization performed prior to the transition to the setting change state or an initialization performed when a RAM abnormality error occurs. In the storage area of the RAM 41c, all the areas (including the unused area and the unused stack area) other than the important work and the used stack area, that is, the areas from the non-preserved work to the unused stack area are initialized. You. Initialization 2 is initialization performed at the end of BB. In initialization 2, the general work, the unused area, and the unused stack area of the storage area of the RAM 41c, that is, the area from the general work to the unused stack area, are stored. Initialized. Initialization 3 is initialization performed when the setting key switch 37 is off at the time of startup and the data in the RAM 41c is not destroyed. In initialization 3, the unsaved work, the unused area, and the unused The used stack area is initialized. The initialization 4 is an initialization performed at the end of one game. In the initialization 4, an unused area and an unused stack area of the storage area of the RAM 41c are initialized.

  In the present embodiment, the interrupt is prohibited before the initialization 1 and the initialization 3 are performed in the initialization processing (see FIGS. 5 and 6) described later. Initialization 2 is performed after interrupts are prohibited at the end of the game. When initialization 1 is performed, interrupts are prohibited at the end of one game and then initialization 1 is performed. In this embodiment, the initialization 1 is performed before the transition of the setting change state. However, the initialization 1 is performed at the end of the setting change state, or both before the transition to the setting change state and at the end of the setting change state. May be.

  As described above, in the present embodiment, when a RAM abnormality error occurs at the time of power-on or the like, the initialization 1 is executed, and the control state before that is initialized. The RT flag and the number of remaining RT games assigned to the work are retained without being initialized. On the other hand, the game state flag assigned to the general work is initialized as the initialization 1 is executed.

[Internal lottery]
In the slot machine 1 of the present embodiment, as described above, the prescribed number of bets that can be set according to the gaming state (usually, inside, BB (RB)) is determined, and is determined according to the gaming state. The game can be started on the condition that the specified prescribed number of bets has been set. In the present embodiment, the pay line LN is activated when a specified number of bets is set according to the gaming state.

  In the slot machine 1 according to the present embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line LN (hereinafter, the activated pay line LN is simply referred to as the pay line LN). Wins when a combination of symbols called a role is completed. The combination may be a combination of the same symbols or a combination including different symbols. The types of winning combinations are determined according to the game state, but are roughly divided into small winning combinations with medal payout and re-starting so that the next game can be started without setting the number of bets. There are a gaming role (hereinafter, also referred to as “replay”) and a special role (hereinafter, also referred to as “bonus”) accompanied by a transition to a gaming state advantageous to the player. Hereinafter, the small role and the replaying role are collectively referred to as a general role. In order for a winning of each combination determined according to the gaming state to occur, it is necessary to win an internal lottery described later and set a winning flag of the combination in the RAM.

  In addition, among the winning flags of each of these roles, the winning flag of the small role and the replaying role is valid only in the game in which the flag is set, and is invalid in the next game. The combination is enabled until the combination of the permitted combinations is completed by the flag, and is invalid in the game in which the combination of the permitted combinations is completed. That is, once the winning flag of the special role is won, even if the combination of the roles permitted by the flag cannot be aligned, the winning flag is not invalidated and is carried over to the next game. It becomes.

  In the internal lottery, it is determined whether or not the winning of each of the above-mentioned roles is permitted before the display results of all the reels 2L, 2C, 2R are derived and displayed (actually, when the start switch 7 is detected). Is what you do. In the internal lottery, first, when the start switch 7 is detected, a random number for the internal lottery (an integer from 0 to 65535) is obtained. Specifically, the value of the random number value storage work assigned to the RAM 41c is set to the lottery work similarly assigned to the RAM 41c. Then, numerical data stored in the lottery work, the value of the game state flag for specifying the game state, and the RT to be described later are specified for each combination determined according to the game state and whether or not the special combination is carried over. The determination is performed in accordance with the value of the RT flag, the number of bets, and the determination value of each combination determined according to the set value. If the special role does not win in the game that has won the special role in the internal lottery, the special role won status will be carried over to the next game and thereafter, and the special role will continue until the special role wins. It is to maintain the winning state.

  In the internal lottery, a random number value for internal lottery (stored in a lottery work) is determined based on the role to be subjected to the internal lottery, the current game state flag value, the RT flag value, and the number of determination values determined corresponding to the set value. Are sequentially added to each other, and when the result of the addition overflows, it is determined that the winning combination has been won. Therefore, the winning combination is determined based on the probability (the number of judgment values / 65536) according to the magnitude of the number of judgment values.

  When the winning of any of the winning combinations is determined, the winning flag corresponding to the winning-determined winning combination is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as a special role storing work in which the special role winning flag is set, and the lower byte is a general role winning work. Assigned as a general role storage work for which the flag is set. Specifically, when the special combination is won, the special combination winning flag indicating that the special combination has been won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When the general combination is won, the general combination winning flag indicating that the general combination has been won is set in the general combination storage work. If no winning combination or combination of winning combinations is won, only the general combination storing work is cleared.

[Reel stop control]
Next, stop control of the reels 2L, 2C, 2R executed in the reel rotation processing in Sd3 of FIG. 7 will be described.

  The main control unit 41 refers to the table index and the table creation data stored in the ROM 41b when the rotation of the reels has started and when the reels have stopped and the reels that are still rotating still remain. Then, a stop control table is created for each rotating reel. When any one of the stop switches 8L, 8C, 8R corresponding to the reel being rotated is effectively detected, the stop control table of the corresponding reel is referred to, and the slip of the referred stop control table is performed. Based on the frame number, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the table index, an index indicating a head address of an area in which table creation data is stored from a reference address when referencing the table index, for each setting state of a winning flag by an internal lottery (hereinafter, referred to as an internal winning state). The difference up to the address where the data is stored is registered. As a result, it is possible to acquire a difference corresponding to the internal winning state and add the difference to the reference address to acquire the corresponding index data. Even if the winning status of the role is different, if the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes a stop control table indicating the number of sliding frames according to the stop operation position, and an address of the stop control table to be referred to according to the reel stop state.

  The stop control table referred to according to the reel stop status indicates whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, only the right reel is stopped, the left, It may differ depending on whether the middle reel is stopped, the left and right reels are stopped, or the middle and right reels are stopped. The stop control table address to be referred to for each situation is registered for each spinning reel, and based on the start address of the table creation data, The address of the stop control table to be referred to according to the situation can be specified. From the specified address, it is necessary according to each situation. And to be able to identify the stop control table. Even if the stop status of the reels or the stop positions of the stopped reels are different, when the same stop control table is applied, the same address may be registered as the address of the stop control table. In such a case, the same stop control table is referred to.

  The stop control table is data that can specify the number of sliding frames at each timing when the stop operation is performed. In the present embodiment, the reel motors 32L, 32C, 32R use stepping motors that make one revolution with a cycle of 168 steps (0 to 167). That is, by driving the reel motors 32L, 32C, 32R by 168 steps, the reels 2L, 2C, 2R make one revolution. Twenty-one areas (frames) divided into 16 steps (the number of steps in which one symbol moves) for one rotation of the reel are defined, and these areas include areas 0 to 20 from the reel reference position. A number has been assigned. On the other hand, the number of symbols arranged on one reel is also 21, and symbol numbers from 0 to 20 are assigned to the symbols on each reel from the reel reference position. , Area numbers 0 to 20 are assigned in order. In the stop control table, the number of sliding frames for each area number is compressed and stored according to a predetermined rule. By expanding the stop control table, the number of sliding frames for each area number can be obtained. I have.

  As described above, in the stop control table created with reference to the table index and the table creation data, the area corresponding to each area number is set at the stop reference position (in the present embodiment, the see-through window 3 when the operation of the stop switches 8L, 8C, and 8R is detected at the timing (the timing at which the number of steps from the reel reference position is included in the range of the number of steps of each area number) located at the position of the lower symbol 3). This is a table in which the number of frames is set.

  Next, the procedure for creating the stop control table will be described. First, at the start of reel rotation, the start address of table creation data according to the internal winning state of the game is acquired. Specifically, first, the table index is referred to, index data corresponding to the internal winning state is obtained, and table creation data is specified based on the obtained index data, and all reels are identified from the specified table creation data. Acquires the address of the stop control table of each reel corresponding to the rotating state, and develops the stop control table of each reel stored at the acquired address to create a stop control table for all reels.

  When any one of the reels stops or any two of the reels stop, the index data acquired at the start of the reel rotation, that is, the start address of the table creation data according to the internal winning state of the game. The table creation data is identified based on the table creation data, and the stopped reel and the stop control table address of the unstopped reel corresponding to the area number of the stop position of the reel are acquired from the identified table creation data. The stop control table of each stored reel is expanded to create a stop control table for unstopped reels.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, 8R corresponding to the spinning reel, the control for deriving the display result to the relevant reel is described. More specifically, when any one of the stop switches 8L, 8C, and 8R is effectively detected, the stop operation position is determined based on the number of steps from the reel reference position when the stop operation is detected. The number of sliding frames corresponding to the area number of the specified stop operation position is acquired by referring to the stop control table of the reel where the stop operation has been detected. Then, control is performed to rotate and stop the reel by the acquired number of sliding frames. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps until the number of sliding frames acquired and stopped is calculated, and the reel is rotated and stopped by the calculated number of steps. Perform control. As a result, the area corresponding to the area number corresponding to the area number corresponding to the area number of the stop operation position where the stop operation is detected is the stop reference position (in the present embodiment, the see-through window 3). (The lower symbol area).

  In the table index of the present embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state, and one table creation data includes one reel. Only one address is stored as the address of the storage area of the stop control table corresponding to the stop state (and the stopped position of the stopped reel). That is, table creation data corresponding to one internal winning state in one gaming state, and a stop control table corresponding to a reel stop state (and a stopped reel stop position) are uniquely defined. Is also unique with respect to one internal winning state in one game state and a reel stop state (and a stopped reel stop position). Therefore, when all of the gaming state, the internal winning state, and the reel stop state (and the stopped reel stop position) are the same, the reels are controlled based on the same stop control table, that is, the same control pattern. Is performed.

  Further, in the present embodiment, a value of 0 to 4 is defined as the number of sliding frames, and it is possible to stop the reel by drawing a maximum of 4 frame symbols after detecting the stop operation. In other words, the stop position of the symbol can be specified from a maximum of five frames including the stop operation position where the stop operation is detected. Further, since it is necessary to move one frame to move the reel for one symbol, it is possible to draw up to four symbols and stop the reel after detecting the stop operation. The stop position of the symbol can be designated from a range of up to five symbols including the operation position.

  In the present embodiment, when any of the winning combinations has been won, the winning combination is drawn to the winning line LN within the range of four frames as much as possible, and the winning combination is drawn so as not to be aligned with the winning line LN. Creates a stop control table in which the number of sliding frames is determined, and performs stop control of the reels. If none of the roles are elected, the stop control in which the number of sliding frames in which none of the roles are aligned is determined. A table is created and reel stop control is performed. As a result, when the stop operation is performed, if the winning combination in the pay-in line LN within a pull-in range of up to four frames can be aligned and stopped, a control for aligning and stopping the winning combination is performed. In the case of a winning combination, control is performed to stop the machine in a pull-in range of a maximum of four frames.

  If the special role and the small role are elected at the same time, such as when the small role is elected while the special role has been carried over before the previous game, the winning small role is placed on the winning line LN within a range of 4 frames. The number of sliding frames is determined so as to draw in as much as possible, and for the stop operation position where the winning small role cannot be drawn within the maximum of four frames in the winning line LN, the winning special role is placed in the winning line LN. A stop control table in which the number of sliding frames is determined so as to draw in the frame as much as possible is generated, and reel stop control is performed. As a result, when the stop operation is performed, if it is possible to stop all the winning combinations in the pay-in line LN within a pull-in range of a maximum of four frames, a control is performed to stop the small winnings together. If it is not possible to draw in the small role that has been won in the up to four frames in the line LN, if the special roles that have been won in the up to four frames in the winning line LN can be aligned and stopped, Control is performed to stop the rolls in line with each other, and for the winning combination that has not been won, control is performed to stop the rolls within the pull-in range of 4 frames. That is, in such a case, the control for aligning the small combination with the pay line LN is given priority over the special combination, and the special combination can be won only when the small combination cannot be drawn. When the special combination and the small combination can be drawn in at the same time, only the small combination is drawn in, so that the small combination and the small combination are not aligned with the winning line LN.

  In this embodiment, the special role and the small role are simultaneously won, such as when the small role is won while the special role is carried over from before the previous game, or when the special role and the small role are newly won at the same time. In the case of winning, the winning small role is given priority over the winning special role, and only when the small role cannot be drawn, the special role is controlled to be aligned with the winning line LN. In the case where the special combination is won simultaneously, the control for aligning the special combination with the winning line LN is given priority over the small combination, and the control for aligning the small combination with the winning line LN may be performed only when the special combination cannot be drawn. .

  When the special role and the replay are elected at the same time, for example, when the special role has been carried over before the previous game and the special role and the replay are elected at the same time, when the stop operation is performed, the maximum pay line LN is displayed. Control is performed in which the symbols of the replaying game are aligned and stopped within the four-frame pull-in range. In this case, the symbols constituting the re-games or the symbols constituting the re-games simultaneously won are arranged within 5 symbols, that is, at intervals of 4 frames or less on any of the reels 2L, 2C and 2R. In the case where the special role and the replaying role are simultaneously elected, regardless of the operation timing of the stop switches 8L, 8C, 8R by the player, since it can be stopped at any position within the pull-in range of four frames. Instead, the re-game players will always win. That is, in such a case, the control for aligning the re-game combination with the pay line LN has priority over the special combination, and the re-game combination always wins. When the special combination and the re-game combination can be drawn in at the same time, only the re-game combination is drawn in, and the special combination is not aligned with the pay line LN at the same time as the re-game combination.

  In the present embodiment, after the rotation of the reels 2L, 2C, 2R is started, the main controller 41 rotates the reels for which the stop operation has not yet been detected until the operation of the stop switches 8L, 8C, 8R is detected. And the control to stop the display result on the corresponding reel is performed on condition that the operation of the stop switches 8L, 8C, 8R is detected. Even if the reel rotation is temporarily stopped due to the occurrence of the reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is resumed. On the condition that the operation of the stop switches 8L, 8C, and 8R is detected, the control of stopping the display result on the corresponding reel is performed.

  In the present embodiment, the control for stopping the display result on the corresponding reel is performed on condition that the operation of the stop switches 8L, 8C, 8R is detected. After that, when a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is considered that the stop operation has been performed, and the automatic stop control for automatically stopping each reel is performed. You may do it. In this case, since the reels stop without the player's operation, it is preferable to derive a display result that does not constitute any combination even if any combination has been won.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described.

[Initial setting process]
The main control unit 41 generates a system reset when a system reset signal is input from the reset circuit 49, and the microcomputer performs various settings at the time of startup, such as a function setting referring to HW parameters described later. Thereafter, according to a program stored in the ROM 41b as a user program, an initial setting process shown in the flowcharts of FIGS. 5 and 6 is performed.

  As shown in FIGS. 5 and 6, the main control unit 41 first executes a timer interrupt process (main) executed by the main control unit 41 described in FIGS. 8 and 9 at regular intervals (intervals of 0.56 ms). Is prohibited (Sa1). Next, the built-in device, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sa2).

  Next, access to the RAM 41c is permitted (Sa4), and the RAM parity of all storage areas (including the unused area and the unused stack area) of the RAM 41c is calculated (Sa5).

  In the step Sa6, it is determined whether or not the RAM parity calculated in the step Sa5 is 0. If the power interruption interrupt processing (main) is normally performed, the RAM parity should be 0. If the RAM parity is not 0 in the step Sa6, the data stored in the RAM 41c is not normal. In this case, after executing initialization 1 for initializing all storage areas other than the used stack area and important work in the storage area of the RAM 41c (Sa22), it is determined whether the setting key switch 37 is on. (Sa23), and if the setting key switch 37 is on, a setting change start command indicating that the setting is being changed is generated (Sa19), and the generated setting change start command is stored in the command buffer (Sa20). ).

  Then, the main control unit 41 sets a register of a timer circuit incorporated in the main control unit 41 so that a timer interrupt is periodically performed at predetermined time intervals (Sa20a). For example, a value corresponding to 0.56 ms is set in a predetermined register (time constant register). In this embodiment, it is assumed that a timer interrupt is periodically performed every 0.56 ms. In the timer circuit, the setting of this register initializes the timer, and starts counting time from the initial value.

  Next, the main control unit 41 sets the random number generation circuit 42 (Sa20b). In setting the random number circuit, the main control unit 41 writes, in a built-in register, random number maximum value setting data designating a random number maximum value preset by a user. Further, the main control unit 41 checks whether the maximum random number set in the built-in register is not less than a predetermined lower limit, and if the maximum random number is less than the lower limit, the main controller 41 sets the random number maximum in the random number maximum setting register. Execute the random number maximum value resetting process for resetting the maximum random number value. Further, the main control unit 41 executes an initial value changing process for changing the initial value of the count value updated by the counter of the random number generation circuit 42. Further, the main control unit 41 writes the random number update mode selection data into the random number update mode selection register. Further, the main control unit 41 writes cycle setting data (data for setting how many times the frequency of the reference clock signal is to be divided) that specifies the cycle of the random number generation clock signal set in advance by the user. Further, the main control unit 41 sets whether or not to update the initial value input to the counter when the count value is updated to a predetermined final value by the counter of the random number generation circuit 42. Further, when the count value is updated to the predetermined final value by the counter of the random number generation circuit 42, the CPU 56 sets whether or not to change the permutation of the count value updated by the counter. Then, the main control unit 41 writes the random number circuit activation data. By doing so, the game control microcomputer 560 activates the random number generation circuit 42.

  Next, the main control unit 41 permits the interruption of the timer interruption process (main) executed at regular intervals (interval of 0.56 ms) by the main control unit 41 described in FIGS. 8 and 9 (Sa21). Then, the process proceeds to a setting change process for changing the winning probability of the winning combination, that is, a setting change state. When the setting change process ends, the process proceeds to a game process shown in FIG.

  If the setting key switch 37 is off in the step of Sa23, an error code indicating RAM abnormality is set in the register (Sa24), an error start command indicating RAM abnormality is generated (Sa25), and the generated error start command is The data is stored in the buffer (Sa26). Then, the timer interrupt is set in the same manner as Sa20a (Sa26a), and the random number generation circuit 42 is set in the same manner as Sa20b (Sa26b), and the main control unit 41 described in FIGS. The interruption of the timer interruption process (main) executed at an interval of 0.56 ms) is permitted (Sa27), and the process shifts to error processing, that is, a RAM abnormal error state. Then, for example, when the reset / setting switch 38 is operated by a game clerk or the like, and the RAM abnormal error state is released, the process proceeds to the game processing shown in FIG.

  If the RAM parity is 0 in step Sa6, it is further determined whether the destruction diagnosis data is normal or not (Sa7). If the power interruption processing (main) is performed normally, the destruction diagnosis data should have been set. If the destruction diagnosis data is not normal in the step Sa7 (the destruction diagnosis data is stored at the time of the power failure). In the case other than 5A (H), the data in the RAM 41c is not normal. Therefore, the processing shifts to the step Sa22 to execute the initialization 1, and then the setting key switch 37 is turned on in the step Sa23. For example, the processing of Sa19 to Sa21 described above is performed, and the processing shifts to the setting change processing, ie, the setting change state. If the setting key switch 37 is off in the step of Sa27, the processing of Sa24 to Sa27 described above is performed, and the processing shifts to error processing, that is, a RAM abnormal error state. Then, when the RAM abnormality error state is released, the process proceeds to a game process shown in FIG.

  If it is determined in step Sa7 that the destructive diagnosis data is normal, the data in the RAM 41c is normal. Therefore, the destructive diagnostic data is cleared (Sa8), and the unsaved work, unused area, and unused data in the RAM 41c are cleared. After performing initialization 3 for initializing the used stack area (Sa9), it is determined whether or not the setting key switch 37 is on (Sa10). If the setting key switch 37 is on, initialization 1 is executed. (Sa15), the above-described processes of Sa19 to Sa21 are performed, and the process proceeds to the setting change process, that is, the setting change state. When the setting change process ends, the process proceeds to a game process shown in FIG.

  If the setting key switch 37 is off in the step of Sa10, each register is restored to the state before the power interruption, that is, the state saved in the stack (Sa11), and the power interruption recovery 1 command (see FIG. 8) is generated. And store it in the command buffer (Sa12). Next, a power failure recovery 2 command (see FIG. 8) is generated and stored in the command buffer (Sa13). Next, a power failure recovery 3 command (see FIG. 8) is generated and stored in the command buffer (Sa14). Next, a power failure recovery 4 command (see FIG. 8) is generated and stored in the command buffer (Sa15). Next, a hot start command (see FIG. 8) is generated and stored in the command buffer (Sa16). Then, the timer interrupt is set in the same manner as in Sa20a (Sa16a), and the random number generation circuit 42 is set in the same manner as in Sa20b (Sa16b), and the main control unit 41 described in FIG. 8 and FIG. The interruption of the timer interruption process (main) executed at an interval of 0.56 ms) is permitted (Sa17), and the process returns to the last execution before the power interruption. If any of the processes in the game process shown in FIG. 7 has been performed before the power interruption, the process of Sd1 to Sd6 of the game process is performed based on the value of the program counter (PC) returned in Sa11. The process returns to the process performed before the power interruption. Further, for example, if any of the processes in the timer interrupt process shown in FIGS. 8 and 9 is performed before the power interruption, based on the value of the program counter (PC) restored in Sa11, The processing returns to the processing performed before the power interruption among the processing of Sk1 to Sk26 of the timer interrupt processing.

[About various commands]
Next, a command transmitted from the main control unit 41 to the sub control unit 91 will be described. The command transmitted from the main control unit 41 to the sub-control unit 91 includes 1-byte mode data indicating the type of command and 1-byte EXT data indicating the content of the command. The sub-control unit 91 determines the type of the command from the mode data, and determines the content of the command from the EXT data.

  Each command is temporarily stored in a command transmission buffer provided in a special work of the RAM 41c of the main control unit 41, and is executed in the command transmission processing (main) executed in the timer interruption processing (main) shown in FIGS. In Sk16), it is transmitted to the sub control unit 91.

  When a command is received from the main control unit 41, the sub-control unit 91 outputs an image displayed on the liquid crystal display 51, a sound output from the speakers 53 and 54, and a front door according to the type of the received command. 1b is controlled.

  The setting change start command is a command indicating that the setting change has been started. The setting change start command is transmitted at the start of the setting change. A value indicating that the setting change has been started is set in the EXT data.

  The setting change end command is a command indicating that the setting change has ended and the setting value selected by the setting change. The setting change end command is transmitted when the setting change ends. In the EXT data, one of six types of setting values selected by changing the setting is set.

  The error start command is a command indicating that an error has occurred. One of eight types of errors is set in the EXT data. The error start command is transmitted at the start of error processing. The eight types of errors include an overflow tank overflow error indicating that the medals in the overflow tank 35 are full, a payout medal no error indicating that the hopper tank 34a has run out of medals, and a medal to be dispensed is a hopper tank. 34a, etc., a payout medal clogging error indicating that clogging has occurred, a throw-in signal error error indicating that a medal detection error has occurred in the medal selector, a reel rotation error error indicating that reel rotation is not performed normally, A prize-winning flag indicating that a prize is expected to be won based on the result of the internal lottery and an actual prize-winning result do not match, and an illegal prize error and a RWM content error indicating a RAM abnormality are set.

  The error release command is a command indicating that the error has been released. The error release command is transmitted when error processing is released. A value indicating that the error has been cleared is set in the EXT data.

  The settlement start command is a command indicating that the settlement of medals has started. The settlement start command is transmitted at the start of the settlement process. Either data indicating that the inserted medals have been settled or data indicating that the credited medals have been settled are set in the EXT data.

  The settlement end command is a command indicating that the settlement of medals has been completed. The settlement end command is transmitted at the end of the settlement process. A value indicating that the settlement has been completed is set in the EXT data.

  The medal insertion command is a command indicating that a medal has been inserted. The medal insertion command is transmitted when a medal is inserted without adding credits. In the EXT data, a value indicating the number of inserted medals (any of 1 to 3) is set.

  The credit increase command is a command indicating that the number of credited medals has increased. The credit increase command is transmitted when a medal is inserted with addition of credit. In the EXT data, a value indicating that the credit has increased is set.

  The game counter 1 command is a command indicating a count value of 0 to 127, which is counted every time a game is played. The game counter 1 command is transmitted when an operation of the start switch is received. In the EXT data, a value indicating any one of the count values of 0 to 127 is set.

  The reel acceleration information command is a command indicating that the rotation of the reel has started. The reel acceleration information command is transmitted when a start switch operation is received. In the EXT data, a value indicating any one of the nine types of reel start patterns is set.

  The internal winning command is a command indicating whether or not BB has been won and the state of the RT. The internal winning command is transmitted when the operation of the start switch is received. In the EXT data, a value indicating whether or not the BB has been won and a state of the RT are set.

  The winning number command is a command indicating the result of the internal lottery. The winning number command is transmitted when the operation of the start switch is received. In the EXT data, a value indicating the result of the internal lottery is set.

  The BB insertion number 1 command is a command indicating the number of medals inserted in the BB game. The BB insertion number 1 command is transmitted at the start of reel rotation. A value indicating the number of inserted medals is set in the EXT data.

  The reel stop reception 1 command is a command indicating that the first stop has been performed. The reel stop reception 1 command is transmitted when a stop switch operation is received. In the EXT data, a value indicating a reception state of each stop switch (that is, whether or not the stop switch is operated) and a lighting state of an LED built in each stop switch (whether or not lighting is being performed) are set.

  The reel sliding frame number 1 command is a command indicating the number of frames until the reel stops when the first stop is performed. The reel slip frame number 1 command is transmitted when an operation of the stop switch is received. In the EXT data, a value indicating the number of frames (0 to 4 frames) until the reel stops is set.

  The reel stop position 1 command is a command indicating the position where the reel stops when the first stop is performed. The reel stop position 1 command is transmitted when an operation of the stop switch is received. A value indicating a reel stop position (frame number 0 to 20) is set in the EXT data.

  The reel stop reception 2 command is a command indicating that the second stop has been performed. The reel stop reception 2 command is transmitted when a stop switch operation is received. In the EXT data, a value indicating a reception state of each stop switch (that is, whether or not the stop switch is operated) and a lighting state of an LED built in each stop switch (whether or not lighting is being performed) are set.

  The reel sliding frame number 2 command is a command indicating the number of frames until the reel stops when the second stop is performed. The reel slip frame number 2 command is transmitted when an operation of the stop switch is received. In the EXT data, a value indicating the number of frames (0 to 4 frames) until the reel stops is set.

  The reel stop position 2 command is a command indicating the position where the reel stops when the second stop is performed. The reel stop position 2 command is transmitted when a stop switch operation is received. A value indicating a reel stop position (frame number 0 to 20) is set in the EXT data.

  The reel stop reception 3 command is a command indicating that the third stop has been performed. The reel stop reception 3 command is transmitted when a stop switch operation is received. In the EXT data, a value indicating a reception state of each stop switch (that is, whether or not the stop switch is operated) and a lighting state of an LED built in each stop switch (whether or not lighting is being performed) are set.

  The reel slip frame number 3 command is a command indicating the number of frames until the reel stops when the third stop is performed. The reel slip frame number 3 command is transmitted when an operation of the stop switch is received. In the EXT data, a value indicating the number of frames (0 to 4 frames) until the reel stops is set.

  The reel stop position 3 command is a command indicating the position where the reel stops when the third stop is performed. The reel stop position 3 command is transmitted when a stop switch operation is received. A value indicating a reel stop position (frame number 0 to 20) is set in the EXT data.

  The game counter 2 command is a command indicating a count value of 0 to 127 which is counted every time a game is played. The game counter 2 command is transmitted after stopping all reels. In the EXT data, a value indicating any one of the count values of 0 to 127 is set.

  The RT information 2 command is a command indicating whether or not BB has been won, whether or not RB has been won, and the state of RT. The RT information 2 command is transmitted when an operation of the start switch is received. In the EXT data, a value indicating whether or not BB or RB has been won and a state of the RT are set.

  The winning number 1 command is a command indicating the type of winning. The winning number 1 command is transmitted at the start of the medal payout process. In the EXT data, a value indicating the operating state of the BB (whether or not the BB is being performed) and the type of winning is set.

  The winning number 2 command is a command indicating the type of winning. The winning number 1 command is transmitted at the start of the medal payout process. In the EXT data, a value indicating the operating state of the BB (whether or not the BB is being performed) and the type of winning is set.

  The winning number command is a command indicating the number of medals paid out by winning. The winning number command is transmitted at the start of the medal payout process. In the EXT data, a value indicating the number of payout medals is set.

  The BB payout number 1 command is a command indicating the payout number of medals at the time of BB. The BB payout number 1 command is transmitted at the start of the medal payout process during BB. In the EXT data, a value indicating the number of payout medals in the BB (upper 7 bits) is set.

  The BB payout number 2 command is a command indicating the payout number of medals at the time of BB. The BB payout number 2 command is transmitted at the start of the medal payout process during BB. In the EXT data, a value (lower 7 bits) indicating the number of payout medals in BB is set.

  The BB end waiting command is a command indicating that the BB is waiting for the end. The BB end waiting command is transmitted when BB ends. In the EXT data, a value indicating the type of the BB waiting for completion (one type in the present embodiment) is set.

  The BB end command is a command indicating that the BB ends. The BB end command is transmitted at the end of BB, at the start of automatic settlement, or at the start of stop processing. In the EXT data, a value indicating the type of BB to be ended (one type in the present embodiment) is set.

  The RT information 1 command is a command indicating the state of the RT. The RT information 1 command is transmitted at the end of the game. A value indicating the state of the RT is set in the EXT data.

  The BB operation type command is a command indicating whether or not BB is being performed. The BB operation type command is transmitted at the end of the game. In the EXT data, a value indicating whether or not BB is being performed is set.

  The game end command is a command indicating a game state (BB, RB, replay winning) when the game is ended. The game end command is transmitted when the game ends. In the EXT data, a value indicating a gaming state (BB, RB, replay winning) when the game is ended is set.

  The door command is a command indicating whether or not the front door 1b is open. The door command is transmitted when the power is turned on, when a setting change is started, when an RWM content error starts, when the game ends, and when the door is opened and closed. In the EXT data, a value indicating the open state of the door (whether it is open or closed) is set.

  The power-off recovery 1 command is a command indicating a count value of 0 to 127, which is counted every time the game is played. The power-off recovery 1 command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating any one of the count values of 0 to 127 is set.

  The power interruption recovery 2 command is a command indicating whether or not BB has been won and the state of RT. The power-off recovery 2 command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating whether or not the BB has been won and a state of the RT are set.

  The power interruption recovery 3 command is a command indicating whether or not BB is being performed and the number of inserted medals. The power-off reset 3 command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating whether or not BB is being performed and the number of inserted medals is set.

  The power-off recovery 4 command is a command indicating a game state (BB, RB, replay winning) when the game is ended. The power-off recovery 4 command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating a gaming state (BB, RB, replay winning) when the game is ended is set.

  The hot start command is a command for restarting without turning off the power. The hot start command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating restart without turning off the power is set.

[Game processing]
FIG. 7 is a flowchart showing the control content of the game processing executed by the main control unit 41.

  As shown in FIG. 7, in the game process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a winning determination process (Sd4), a payout process (Sd5), and a game end process (Sd6) ) Are executed in order, and when the game end processing ends, the processing returns to the BET processing again.

  In the BET process in the step Sd1, the process waits in a state in which a bet amount can be set, sets a specified number of bets according to a game state, and starts a game when the start switch 7 is operated. .

  In the internal lottery process in the step Sd2, it is determined whether the winning of each of the above-mentioned winning combinations is permitted based on the random number value for the internal lottery latched simultaneously with the start of the game by the detection of the start switch 7 in the step Sd1 (that is, the display). A process for determining whether or not to derive the result is performed. In this internal lottery process, a winning flag is set in the RAM 41c based on each lottery result. When a special combination (BB or RB) is won by an internal lottery, a special combination carryover flag is set. Then, as described above, the presence / absence of the special role carryover flag is determined to determine whether or not the special role has been carried over, and the winning role according to the presence / absence of the carryover (the special role is excluded from the internal lottery during the special role carryover). Is performed).

  In the reel rotation process in the step Sd3, the process of rotating each of the reels 2L, 2C, 2R in response to the operation of the start switch 7, the result of the internal lottery in the step Sd2, and the stop switch 8L, 8C, 8R by the player. A process for stopping the rotation of the corresponding reels 2L, 2C, 2R is executed in response to the detection of the operation.

  In the prize determination process in the step Sd4, when it is determined in the step Sd3 that the rotation of all the reels 2L, 2C, 2R has stopped, a prize is won according to the display result derived on each of the reels 2L, 2C, 2R. A process for determining whether or not the error has occurred is executed. When the special combination is won, the special combination carry over flag is cleared in this processing.

  In the payout process in the step Sd5, when the occurrence of a prize is determined in the step Sd4, processes such as addition of credits and payout of medals are performed based on the number of payouts according to the prize.

  In the process at the time of ending the game in the step Sd6, a process of setting a gaming state in preparation for the next game is executed.

  In the game process, a command is generated in accordance with the progress control of the game, set in the command buffer, and transmitted to the sub control unit 91.

[Timer interrupt processing (main)]
FIGS. 8 and 9 are flowcharts showing the control contents of the timer interrupt processing (main) executed by the main control unit 41 interrupting the initial setting processing and the game processing at regular intervals (interval of 0.56 ms). Note that other interrupts are automatically prohibited during the execution of the timer interrupt processing (main).

  As shown in FIG. 8 and FIG. 9, in the timer interrupt processing (main), first, a register in use is saved in a stack area (Sk1).

  Next, a power failure determination process is performed (Sk2). In the power failure determination processing, it is determined whether or not a voltage drop signal is input from the power interruption detection circuit 48. If the voltage reduction signal is input, whether or not the voltage reduction signal was input in the previous power failure determination processing is determined. If a voltage drop signal is also input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that fact is set.

  After the power failure determination process in step Sk2, it is determined whether or not the power failure flag is set (Sk3). If the power failure flag is not set, the process proceeds to Sk4, where the power failure flag is set. , The processing shifts to the power interruption processing (main).

  In step Sk4, port input processing for inputting detection data of various switches from an input port is performed.

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt processing (main) from the four types of timer interrupts 1 to 4 is advanced by 1 (Sk5). In this embodiment, the timer interrupt 1 is a branching process during the timer interrupt for controlling the motor to start the reels. Specifically, the processes of Sk9 to Sk11 such as a reel start process described later. Is performed. The timer interrupt 2 is a branching process during the timer interrupt for performing LED display control, updating a time counter, monitoring a door open / close state, controlling output of control signals and the like, and updating commands and external output signals. Specifically, the processes of Sk12 to Sk17, such as an LED dynamic display process described later, are performed. The timer interrupt 3 is a branching process during the timer interrupt for detecting the passage of the origin of the reel, monitoring the switch input, and reading the random number value. More specifically, the timer interruption 3 is described later. Processing of Sk20 to Sk22 such as time processing is performed. The timer interrupt 4 is a branching process during the timer interrupt for detecting the input of the stop switch and performing the stop control of the reel. Specifically, the processes of Sk23 to Sk25 such as a stop switch process described later. Is performed. In step Sk5, 1 is added when the branch counter value is 0 to 2, and updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Every time the timer interrupt processing (main) is executed.

  Next, it is determined with reference to the branch counter value whether it is 2 or 3, that is, whether it is timer interrupt 3 or timer interrupt 4 (Sk6), and if it is not timer interrupt 3 or timer interrupt 4, that is, if it is not timer interrupt 4, In the case of 1 or timer interrupt 2, it is checked whether or not the reel motors 32L, 32C, 32R are starting or rotating at a constant speed, and if the reel motors 32L, 32C, 32R are starting or rotating at a constant speed. For example, a motor phase signal output process for outputting the phase signal data changed in the motor step process of Sk10 described later and the phase signal data changed in the final stop process of Sk24 described later is executed (Sk7).

  Next, it is determined whether or not it is 1 by referring to the branch counter value, that is, whether or not it is the timer interrupt 2 (Sk8). If it is not the timer interrupt 2, that is, if it is the timer interrupt 1, the reel motor Reel start processing (Sk9) for controlling the step time interval at the start of 32L, 32C, 32R, motor step processing (Sk10) for changing the phase signal data of reel motors 32L, 32C, 32R, reel motors 32L, 32C , 32R are stopped, and after a predetermined time elapses, a motor phase signal standby process (Sk11) for changing the phase signal to one-phase excitation is sequentially performed, and then the process proceeds to Sk25.

  In the case of timer interrupt 2 in step Sk8, an LED dynamic display process for dynamically lighting various indicators (Sk12), and a control signal output process for outputting data such as lighting signals of various LEDs to an output port. (Sk13), time counter update processing for updating various time counters (Sk14), monitoring of the detection state of the door open detection switch 25, door monitoring processing for requesting transmission of a door command (Sk15), and setting in the command buffer. After sequentially executing a command transmission process (Sk16) for transmitting various commands such as a setting change command, a return command, and an error command to the sub-control unit 91, and an external output signal update process (Sk17) for updating an external output signal, Sk25 is executed. Proceed to step.

  If the timer interrupt is the timer interrupt 3 or the timer interrupt 4 in the step of Sk6, it is further determined whether or not the timer interrupt is 3 by referring to the branch counter value, that is, whether or not the timer interrupt is 4 (Sk18). If it is not the interrupt 4, that is, if it is the timer interrupt 3, the rotation of the reels 2 </ b> L, 2 </ b> C, and 2 </ b> R is checked for passing through the origin (passing of the reel reference position), and the occurrence of the reel rotation error is detected and stopped. Check that the preparation is complete (whether the stop preparation completion code is set). If the preparation for the stop is complete and the motor is rotating at a constant speed, operate the stop switch corresponding to the rotating reel. The process of passing through the origin to be activated (Sk20), whether the detection state of the switches such as the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, and 8R has changed. After performing a switch input determination process (Sk21) for requesting the transmission of a constant, operation detection command, and the like, and a random value reading process (Sk22) for reading numerical data from the random value register R1D and storing the data in a random value storage work, Sk26 is performed. Proceed to step.

  Further, if the timer interrupt is 4 in the step of Sk18, when the stop operation position is stored in the work of the stop reel upon detection of the stop switches 8L, 8C, 8R, the stop stored in the work of the stop reel is performed. Stop switch processing (Sk23) for determining the stop position from the operation position and calculating how many steps to stop after, counting the number of steps up to the stop calculated in the stop switch processing, and when it is time to stop. A stop process (Sk24) for starting braking by two-phase excitation, a final stop process (Sk25) for three-phase excitation after a predetermined time from the start of braking in the stop process, and then the process proceeds to Sk26.

  In step Sk26, the register saved in the stack area in Sk1 is restored, and the process returns to the process before the interruption.

[Power interruption processing (main)]
FIG. 10 is a flowchart showing the control contents of the power interruption processing (main) executed when the main control unit 41 determines that the power interruption flag is set in the above-described timer interruption processing (main).

  In the power interruption processing (main), first, all registers that may be used are saved in the stack area (Sm1). The values of the I register and the IY register are used, but are not stored here because the same fixed value is always set with the initialization at the time of startup.

  Next, destruction diagnosis data (5A (H) in the present embodiment) is set (Sm2). Then, the main control unit 41 described with reference to FIGS. 8 and 9 prohibits the interruption of the timer interruption process (main) executed at regular intervals (interval of 0.56 ms) and initializes all output ports ( Sm3). Next, RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including the unused area and the unused stack area) of the RAM 41c becomes 0 (Sm4), and access to the RAM 41c is performed. Prohibition (Sm5).

  Thereafter, the voltage drops, the CPU 41a of the main control unit 41 stops, and the process shifts to a standby state. Then, if the voltage decreases in this standby state, the operation is internally stopped. Therefore, the operation of the main control unit 41 is reliably stopped at the time of power interruption.

  In the present embodiment, the interrupt is prohibited before the output port is initialized. However, the output port for outputting data to the sub-control board 90, the external output board 1000, and the reel motor and the reel sensor is set. The interrupt may be set to be disabled before writing the data or writing the data to the serial communication circuit.

[Configuration of microcomputer]
As shown in FIG. 11, microcomputers used as the main control unit 41 and the sub control unit 91 include a clock generation circuit 200, a reset controller 201, an interrupt controller 202, a WDT (watchdog timer) 203, and a CTC (counter timer). 204, arithmetic circuit 205, address decoder 206, CPU 207 used as main CPU 41a and sub CPU 91a, ROM 208 used as ROM 41b and ROM 91b, RAM 209 used as ROM 41c and RAM 91c, M1 counter 210, inspection port 211, random number generation circuit 42 Used random number circuit 212, general-purpose initial value random number circuit 212, serial communication circuit 214, PWM (pulse width modulation) output circuit 215, interrupt / general-purpose output circuit 216, random number And a part latch input circuit 217.

  The microcomputer shown in FIG. 11 includes, as security functions, an individual ID, ROM reading restriction, 64-pin SZIP sealing, and an inspection port 211.

  The CPU 207 operates at a frequency of 10 MHz (minimum instruction execution time: 100 msec).

  The ROM 208 has a capacity of 10,240 bytes, and the RAM 209 has a capacity of 512 bytes.

  In addition, four reset functions are provided: a system reset, a WDT (watchdog timer) reset, a periodic reset, and an illegal access reset.

  Further, as an interrupt function, there are provided two functions of an external terminal interrupt (INT / NMI) and a CTC interrupt (CTC0, CTC1, CTC2).

  As chip select terminals, 16 are used in the CS mode and 23 are used in the ECS mode. The CTC 204 has 16 bits × 3 channels.

  Further, the random number circuit 212 has a total of 16 channels of 8 bits fixed length random number × 8 channels, 16 bit fixed length random number × 2 channels, 8 bit variable length random number × 4 channels, 16 variable length random numbers × 2 channels. Further, the general-purpose initial value random number circuit 212 has one channel.

  The serial communication circuit 214 has three channels for transmission and one channel for reception.

  Further, the arithmetic circuit 205 calculates CRC16, checksum, and horizontal parity.

  The PWM output circuit 217 has four channels. The general purpose external latch input circuit has three inputs.

  Also, four general-purpose input / output terminals are provided on the input side and three are provided on the output side. The address decoder 207 is used for outputting CS0 to CS15.

[Address map of memory space]
Next, an address map of a memory space in the ROM 208 and the RAM 209 of the microcomputer shown in FIG. 11 will be described with reference to FIG. The memory space shown in FIG. 12 is a memory space accessed by a 16-bit address. The memory space is accessed by a memory instruction. In FIG. 12, 0000h to 7FFFh is the memory space of the RAM, and 8000h to FFFFh is the memory space of the ROM.

  The memory space addresses 0000h to 01FFh of the RAM 209 are available areas that can be accessed. The memory space addresses 0200h to 0FFFh are unused areas where access is prohibited. Internal registers are allocated to the memory space addresses 1000h to 1080h. The memory space addresses 1081h to 7FFFh are unused areas where access is prohibited. ROM is allocated to the memory space addresses 8000h to A7FFh. The memory space addresses A800h to FFFFh are unused areas where access is prohibited.

  In the memory space of the ROM 208, programs / data are allocated to addresses 8000h to A6FFh. Further, ROM comments are assigned to addresses A700h to A7FFh. A vector table is assigned to addresses A780h to A7A7h. HW parameters are assigned to addresses A7A8h to A7FFh.

  As described above, the 512-byte RAM is arranged in 0000h to 01FFh. When a system reset or a WDT reset occurs, a RAM protection state is set. In the RAM protected state, the RAM can be read but cannot be written. To release the RAM protection state, 00h or 80h is set in the RAM protection register (RAMPT).

  The internal function registers are a group of registers for controlling each function mounted on the microcomputer of FIG. If 1 is set in the internal function register arrangement (HRGACS) of the system setting (HSYSCNT) of the HW parameter, it can be arranged in the I / O space.

  In addition, a 10,240-byte ROM is arranged at 8000h to A7FFh. In the ROM area, programs / data, ROM comments, vector tables, and HW parameters are arranged.

  The microcomputer executes the program from 8000h after the system reset, the WDT reset, the periodic reset, and the illegal access reset. The program cannot be executed outside this area.

  The ROM comment is an area for setting a title, a version, and the like of a program, in which arbitrary data can be set. The data set here can be read from the inspection ports (TXD, RXD, STB, DIR).

  The vector table is a table for setting the head address of the subroutine of the CALLV instruction and the head address of the interrupt processing. 0000h is set in the unused vector table. If the values set in the vector table are other than 0000h and 8000h to HPRGEND, the microcomputer does not start. HPRGEND is set by the program end address of the HW parameter.

  The HW parameter is a parameter for setting the internal function of the microcomputer by hardware. The setting is described as a constant table. It cannot be written by a program.

[Vector table address map]
Next, an address map of the vector table in the memory space of the ROM 208 shown in FIG. 12 will be described with reference to FIG.

  As shown in FIG. 13, in the vector table, the memory space addresses A780h to A79Fh are the vector tables for the CALLV instruction, and the memory space addresses A7A0h to A7A7h are the vector tables for the interrupt processing.

  In the memory space addresses A780h to A781h of the CALLV instruction vector table, (lower) and (upper) values of CALLV0 are set. In the memory space addresses A782h to A783h, (lower) and (higher) values of CALLV1 are set. The (lower) and (upper) values of CALLV2 are set in the memory space addresses A784h to A785h. The (lower) and (upper) values of CALLV3 are set in the memory space addresses A786h to A787h. The (lower) and (upper) values of CALLV4 are set in the memory space addresses A788h to A789h. In the memory space addresses A78Ah to A78Bh, (lower) and (higher) values of the CALLV5 are set. (Lower) and (higher) values of CALLV6 are set in the memory space addresses A78Ch to A78Dh. In the memory space addresses A78Eh to A78Fh, (lower) and (higher) values of the CALLV7 are set. In the memory space addresses A790h to A791h, (lower) and (upper) values of the CALLV8 are set. In the memory space addresses A792h to A793h, (lower) and (upper) values of the CALLV 9 are set. In the memory space addresses A794h to A795h, (lower) and (upper) values of the CALLV 10 are set. The (lower) and (upper) values of the CALLV 11 are set in the memory space addresses A796h to A797h. The (lower) and (upper) values of the CALLV 12 are set in the memory space addresses A798h to A799h. The (lower) and (upper) values of the CALLV 13 are set in the memory space addresses A79Ah to A79Bh. In the memory space addresses A79Ch to A79Dh, (lower) and (upper) values of the CALLV 14 are set. The (lower) and (upper) values of the CALLV 15 are set in the memory space addresses A79Eh to A79Fh.

  INT / NMI (lower order) and (upper order) values are set in memory space addresses A7A0h to A7A1h of the interrupt processing vector table. The (lower) and (upper) values of CTC0 are set in the memory space addresses A7A2h to A7A3h. In the memory space addresses A7A4h to A7A5h, (lower) and (higher) values of CTC1 are set. (Lower) and (higher) values of CTC2 are set in the memory space addresses A7A6h to A7A7h.

[List of HW parameters]
Next, the HW parameters in the memory space of the ROM 208 shown in FIG. 12 will be described with reference to FIG.

  As shown in FIG. 14, the symbol HCSATRO is associated with the memory space address A7A8h, and is used for CS / PWM setting. The memory space address A7A9h is associated with the symbol HCSATR1 and is used for CS / PWM setting. The memory space address A7AAh is associated with the symbol HCSATR2 and is used for CS / PWM setting. The memory space address A7ABh is associated with the symbol HCSATR3 and is used for CS / PWM setting. The memory space address A7ACh is associated with the symbol HCSATR4 and is used for CS / PWM setting. The memory space address A7ADh is associated with the symbol HCSATR5 and is used for CS / PWM setting. The memory space address A7AEh is associated with the symbol HCSATRD and is used for CS / PWM setting.

  The memory space address A7AFh is associated with the symbol HPRST and is used for periodic reset setting.

  The symbol HRDMD is associated with the memory space address A7B0h, and is used for setting a random number circuit operation mode.

  The memory space address A7B1h is associated with the symbol HSYSCNT and is used for system setting.

  The memory space address A7B2h is associated with the symbol HSYSCNT and is used for reset period / INP terminal setting.

  The memory space addresses A7B3h to A7B4h are associated with the symbol HRPGEND and are used for setting a program end address.

  The memory space addresses A7B5h to A7B6h are associated with the symbol HRAMSTAT and are used for setting a RAM access prohibition address.

  The memory space addresses A7B7h to A7B8h are associated with the symbol HRAMEND and are used as RAM access prohibition addresses.

  The memory space addresses A7B9h to A7CCh are associated with the symbol HSWSTS and are used for setting the SW status.

  The memory space addresses A7CDh to A7CFh are used for setting a maker code.

  The memory space addresses A7D0h to A7D7h are used for setting a product code.

  The memory space addresses A7D8h to A7FFh are used for setting a security code.

[Reset period / INP terminal setting]
Next, the reset period / INP terminal setting in the HW parameter shown in FIG. 14 will be described with reference to FIG.

  As shown in FIG. 15, the symbol HPORTEN is associated with bit 7 of the memory space address A7B2h. In HPORTEN, INP terminal function setting is set. When set to 0, it is set not to be used as an interrupt input terminal, and when set to 1, it is set to be used as an interrupt input terminal.

  The symbol HPORTMD is associated with bit 6 of the memory space address A7B2h. In HPORTMD, interrupt input setting and automatic mutual authentication setting are performed. When it is set to 0, it is set to be an INT interrupt input, and when it is set to 1, it is set to be an NMI interrupt input.

  Further, the symbol HRTMEN is associated with bit 5 of the memory space address A7B2h. In the HRTMENU, a reset period extension setting is set. Then, the setting is made so as not to be extended when set to 0, but to be extended when set to 1. The extension time is fixed time + fluctuation time.

  The symbol HRRDEN is associated with bit 4 of the memory space address A7B2h. In HRRDEN, the reset period extension setting is set. When bit 4 of A7B2h is set to 0, it does not always fluctuate at 0 msec, and when MCLK (system clock) = 20 MHz, when it is set to 1, it takes 0 msec to 1275 msec (5 msec, 256 types). It is set to fluctuate. Each time the system is reset, the time is different from the previous time.

  The symbol HRSTM is associated with bits 3 to 0 of the memory space address A7B2h. In HRSTM, a fixed time is set. Then, when MCLK = 20 MHz, when 0h is set, it is set to be 1.0 sec. Also, when set to 1h, it is set to 2.0 seconds. Thereafter, it is set so as to be longer by 1.0 sec according to the set value, and to be 30.0 sec at the maximum.

  As described above, in the settings of HPORTEN and HPORTMD, whether an interrupt process is started when an L-level signal is input to the interrupt input / general-purpose input terminal (INP) and whether the interrupt request is INT An interrupt or an NMI interrupt can be selected.

  Further, regardless of the setting state of HORTEN, the input level of the INP terminal can be read from the external signal input / reset factor register (PINSTS), so that it can be used as a general-purpose input.

  Also, when HEMTEN is set to 0, the reset period is not extended regardless of the settings of HRRDEN and HRSTM.

  Also, when HRTMENU is set to 1, the period from the system reset period of 400.5 msec (when MCLK = 20 MHz) to the start of the program can be extended. The extended time is the sum of the fixed time set by HRSTM and the variable time set by HRRDEN.

For example, the system reset time when HRTMEN = 1, HRRDEN = 1, and HRSTM4h are set as follows.
400.5 msec + 5.0 msec + (0 to 1275 msec) = 5.4005 sec to 6.6755 sec (when MCLK = 20 MHz)

[Program end address]
Next, the program end address in the HW parameter shown in FIG. 14 will be described with reference to FIG.

  “8000h to A6FFh” in the memory space address is defined as an area for storing “program / data” as shown in FIG. However, the capacity of “program / data” differs depending on the contents of control of the gaming machine, and is not stored in all of these areas. In this microcomputer, by setting a program end address, a range of an area where “program / data” is stored is set, and when an area where “program / data” is not accessed is accessed, illegal It can be set so that an access reset occurs. Although the setting is performed by designating the end address (final address) for the range of the area where “program / data” is stored, the start address (start address) may be designated. Further, a plurality of separated areas may be set.

  As shown in FIG. 16, a symbol HPRGEND (lower order) is associated with bits 7 to 0 of the memory space address A7B3h, and a symbol HPRGEND (higher order) is associated with bits 7 to 0 of the memory space address A7B4h. In HPRGEND, a program end address is set. Then, the final address of the ROM area used for 8000h to A6FFh is set.

  If HPRGEND is set to a value other than 8000h to A6FFh, an error occurs and the microcomputer does not start. The final address is set in HPRGEND. If the entire ROM area can be accessed, HPRGEND = A6FFh is set. When an area from address +1 set by HPRGEND to A6FFh is accessed, an illegal access reset occurs.

  As shown in FIG. 17, for example, when HPRGEND = 8852h is set, an illegal access reset occurs when accessing 8852h.

[RAM access prohibition address]
Next, the RAM access prohibition address in the HW parameter shown in FIG. 14 will be described with reference to FIG.

  As shown in FIG. 18, bits 7 to 0 of the memory space address A7B5h are associated with the symbol HRAMSTAT (lower), and bits 7 to 0 of the memory space address A7B5h are associated with the symbol HRAMSTAT (upper). In HRAMSTAT, a RAM access prohibition start address is set. Then, the start address of the RAM area whose access is prohibited is set in 0000h to 01FFh.

  Bits 7 to 0 of the memory space address A7B7h are associated with the symbol HRAMEND (lower order), and bits 7 to 0 of the memory space address A7B8h are associated with the symbol HRAMEND (upper order). In HRAMEND, a RAM access prohibition end address is set. Then, the last address of the RAM area whose access is prohibited is set in 0000h to 01FFh.

If the values set in HRAMSTAT and HRAMEND do not satisfy the following relationship, the microcomputer is not started as an error state.
0000h ≦ HRAMSTAT ≦ HRAMEND ≦ 01FFh

  Also, the start address of the RAM area for which access is prohibited is set to HRAMSTAT, and the final address of the RAM area for which access is prohibited is set to HRAMEND.

  When accessing the entire RAM area, HRAMSTAT = 0000h and HRAMEND = 0000h are set.

  In addition, an illegal access reset occurs when an access prohibited area set by HRAMSTAT and HRAMEND is accessed.

  As shown in FIG. 19, for example, when HRAMSTAT = 00F2h and HRAMEND = 01A7h are set, an illegal access reset occurs when accessing 002Fh to 01A7h. The settings of HRAMSTAT and HRAMEND can be invalidated by setting of a RAM protect register (RAMPT).

[SW status]
Next, the SW status in the HW parameter shown in FIG. 14 will be described with reference to FIG.

  As shown in FIG. 20, the symbols HSWSTS0 (lower) are associated with bits 7-0 of the memory space address A7B9h, and the symbol HSWSTS0 (upper) is associated with bits 7-0 of the memory space address A7B8h. The same applies to HSWSTS 1 to 9. Then, in the HSWSTS0-9, the setting of the SW status 0-9 is performed. Then, the address of the RAM monitored by the inspection device is set to 0000h to 01FFh.

  If a value other than 0000h to 01FFh is set in HSWSTS0 to 9, the microcomputer does not start as an error state.

  If the address of the RAM access prohibition area set by the RAM access prohibition address (HRAMSTAT, HRAMEND) of the HW parameter is set in HSWSTS0-9, the microcomputer is not started as an error state.

  Also, the addresses monitored by the inspection device are set to HSWSTS0 to HSWSTS9.

  If the SW status is not used, 0000h is set. However, if 0000h is set in the RAM access prohibition area, the microcomputer does not start as an error state, so it is preferable not to include 0000h in the RAM access prohibition area.

[Conditions that cause illegal access reset]
Next, conditions under which an illegal access reset occurs in the microcomputer shown in FIG. 11 will be described with reference to FIG. In the case shown in FIG. 21, it is determined that the access is unauthorized, and an illegal access reset occurs. When an illegal access reset occurs, only the CPU core is reset, and the internal functions are not reset.

  As shown in FIG. 21, in the CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting content is HCSRW0 = 00; when the CS function is invalid (the same applies to HCSRW1 to HCSRW23), CS0 (C0h in the I / O space). ) (CS1 to CS23 are also the same), which is a condition for generating an illegal access reset.

  In the CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting content is HCSRW0 = 01; in synchronization with the R0 signal (the same applies to HCSRW1 to HCSRW23), writing to CS0 (C0h in the I / O space). (Similarly for CS1 to CS23) is a condition for generating an illegal access reset.

  Further, in the CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting is HCSRW0 = 10; in synchronization with the W0 signal (the same applies to HCSRW1 to HCSRW23), reading from CS0 (C0h in the I / O space) is performed. (Similarly for CS1 to CS23) is a condition for generating an illegal access reset.

  Further, in the CS / PWM setting (symbol name: HSCMOD), the setting content is HCSMD = 0; in the CS mode, the access to the ECS area (D0h to D7h of the I / O space) is illegal access reset. Is the condition for the occurrence of

  Further, in the CS / PWM setting (symbol name: HCSMOD), when the setting content is HCSMD = 1; in the ECS mode, an access to the CS15 (CFh in the I / O space) is required to generate an illegal access reset. It becomes.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 0; memory space, an I / O access to an internal register is a condition for generating an illegal access reset.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 1; I / O space, the memory access to the internal register is a condition for generating an illegal access reset.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 1; I / O space, the memory access to the internal register is a condition for generating an illegal access reset.

  Next, regarding the setting of the program end address (symbol name: HPRGEND), the condition for generating an illegal access reset is that an access is made to the area between A6FFh and the address following the address set as the program end address. .

  Next, regarding the RAM access prohibition address (symbol name: HRAMSTAT, HRAMEND), an illegal access reset occurs because there was access to an area between the start address and the last address of the RAM area set as the RAM access prohibition address. Condition.

  Next, with respect to the internal function register (symbol name: MKCODE), writing to MKCODE is a condition for generating an illegal access reset.

  Next, with respect to the internal function register (symbol name: PRCODE), writing to PRCODE is a condition for generating an illegal access reset.

  Next, with respect to the internal function register (symbol name: CPCODE), writing to CPCODE is a condition for generating an illegal access reset.

  Next, writing to the area (8000h to A7FFh) set as the ROM area, access to the ROM comment area (A700h to A77Fh), and access to the HW parameter area (A7A8h to A77Fh). Access is a condition for generating an illegal access reset.

  Next, an access to an unused area (200h to FFFh, 10B1h to 7FFFh, A800h to FFFh) in the memory space is a condition for generating an illegal access reset.

  Next, an access to an unused area (B1h to BFh) in the I / O space is a condition for generating an illegal access reset.

  Next, the fact that the CPU core fetches the undefined instruction is a condition for generating an illegal access reset.

[Condition not to start]
Next, conditions under which the microcomputer shown in FIG. 11 is not activated will be described with reference to FIG. When the condition shown in FIG. 22 is satisfied, it is determined that an error has occurred, and the microcomputer does not start.

  As shown in FIG. 22, in the setting of the vector table (related symbol name: HPRGEND), if a value other than 0000h and 8000h to HPRGEND is set, the condition that the microcomputer is not started is satisfied.

  In the CS / PWM setting (related symbol names: HCSMD, HCSRW16 to HCSRW23), the condition that the microcomputer is not started when the value set in the CS / PWM setting is HCSMD = 0 and the HCSRW16 is set to a value other than 00 Is satisfied. The same applies to HCSRW17 to HCSRW23.

  In the CS / PWM setting (related symbol names: HCSMD, HCSRW15), if HCSMD = 1 and a value other than 00 is set for HCSRW15, the condition that the microcomputer is not started is satisfied.

  In the CS / PWM setting (related symbol names: HPW0MD to HPW3MD, HCSRW11 to HCSRW14), if HPW0MD = 1 and HCSRRW11 are set to values other than 00, the condition that the microcomputer is not started is satisfied. If HPW1MD = 1 and HCSRW12 is set to a value other than 00, the condition that the microcomputer is not started is satisfied. If HPW2MD = 1 and HCSRW13 is set to a value other than 00, the condition that the microcomputer is not started is satisfied. If HPW3MD = 1 and HCSRW14 is set to a value other than 00, the condition that the microcomputer is not started is satisfied.

  In the CS / PWM setting (related symbol name: HCSMOD), the condition that the microcomputer is not started when bit 4 = 1 of the HCSMOD is set is satisfied. When bit 5 = 1 of HCSMOD is set, the condition that the microcomputer is not started is satisfied. When bit 6 = 1 of HCSMOD is set, the condition that the microcomputer is not started is satisfied.

  In the setting of the random number circuit operation mode (related symbol name: HRDMD), the condition that the microcomputer does not start when the bit 3 of HEMDD is set is satisfied.

  In the random number circuit operation mode setting (related symbol name: HFRCLK), the condition that the microcomputer is not started when HFRCLK = 1 is set and there is no random number external clock (EXCLK) input is satisfied.

  In the setting of the random number circuit operation mode (related symbol name: HRDMYE), the condition that the microcomputer is not started when HRDMYE = 1 is satisfied.

  In the system setting (related symbol name: HSYSCNT), if bit 5 = 1 of HSYSCNT is set, the condition that the microcomputer is not started is satisfied. When bit 6 = 1 of HSYSCNT is set, the condition that the microcomputer is not started is satisfied. If bit 7 = 1 of HSYSCNT is set, the condition that the microcomputer is not started is satisfied. It should be noted that bits 5 to 7 of HSYSCNT are unused bits that are not used for setting any function, and are normally set to 0.

  In the system settings (related symbol names: HLNKMD, HAUTLK), if HLNKMD = 0 and HAUTLK = 1 are set, the condition that the microcomputer is not started is satisfied.

  In the program end address (related symbol name: HPRGEND), if a value other than 8000h to A6FF is set in HPRGEND, the condition that the microcomputer is not started is satisfied.

  In the RAM access prohibition address (related symbol names: HRAMSTAT, HRAMEND), the condition that the microcomputer is not started is satisfied unless 0000h ≦ HRAMSTAT ≦ HRAMEND ≦ 01FFh is not satisfied.

  In the SW status (related symbol names: HSWSTS0 to HSWSTS9), if HSSWTS0 is set to a value other than 0000h to 01FFh, the condition that the microcomputer is not started is satisfied. The same applies to HSWSTS1 to HSWSTS9.

  In the SW status (related symbol names: HSWTSTS0 to HSWSTS9, HRAMSTAT, HRAMEND), the condition that the microcomputer is not started when HSSWTS0 is set to the value of the access prohibition right area set by HRAMSTAT and HRAMEND is satisfied. The same applies to HSWSTS1 to HSWSTS9.

[Changes in operation due to reset factors]
Next, a change in operation of the microcomputer shown in FIG. 11 due to a reset factor will be described with reference to FIG. As shown in FIG. 23, the operation changes due to four types of reset factors.

  When the system reset is performed, the system reset period is set. When the reset factor is any of the WDT reset, the periodic reset, and the illegal access reset, the system reset period is not set.

  When the reset period is extended by the system reset, the extension of the reset period is set when the extension of the reset period is set to be valid by the HW parameter, and is set by any of the WDT reset, the periodic reset, and the illegal access reset. If the reset period is not extended, the extension of the reset period is not set.

  When any of a system reset, a WDT reset, a periodic reset, and an illegal access reset is performed, the CPU core is initialized.

  When a system reset is performed, the input / output terminals are initialized. When any of the WDT reset, the periodic reset, and the illegal access reset is performed, the input / output terminals are not initialized.

  Further, even when any of system reset, WDT reset, periodic reset, and illegal access reset is performed, the contents of the RAM do not change.

  The RAM is set to the protected state when any of the system reset and the WDT reset is performed, and the RAM is not set to the protected state when any of the periodic reset and the illegal access reset is performed.

  Also, if any of the system reset and the WDT reset is performed, the CTC is initialized, and if any of the periodic reset or the illegal access reset is performed, the CTC is not initialized.

  When a system reset is performed, the WDT is initialized, and when any of the WDT reset, the periodic reset, and the illegal access reset is performed, the WDT is not initialized.

  When a system reset is performed, the order of the clear values in the WDT cyclic clear mode is initialized. When any of the WDT reset, the periodic reset, and the illegal access reset is performed, the WDT cyclic clear mode is cleared. The order of the values is not initialized.

  Further, when a system reset is performed, serial communication is interrupted and transmission and reception are initialized, and when any of WDT reset, periodic reset, and illegal access reset is performed, initialization is not performed.

  The interrupt controller is initialized when any one of a system reset and a WDT reset is performed, and the interrupt controller is not initialized when any one of a periodic reset and an illegal access reset is performed.

  When a system reset is performed, external signal input / reset factors, register reset factors, and bits 5 to 7 of PINSTS are initialized, and one of WDT reset, periodic reset, and illegal access reset is performed. Is not initialized.

  The random number circuit is initialized when any one of a system reset and a WDT reset is performed, and the random number circuit is not initialized when any one of a periodic reset and an illegal access reset is performed.

  Also, the initial value of the random number is different every time when any of the system reset and the WDT reset is performed, and the initial value of the random number is changed to the value before the reset when any of the periodic reset and the illegal access reset is performed. Set to value.

  Further, when a system reset is performed, the random number error status register is initialized, and is not initialized when any of a WDT reset, a periodic reset, and an illegal access reset is performed.

  When a system reset is performed, the general-purpose initial value random number is different each time. When any of the WDT reset, the periodic reset, and the illegal access reset is performed, the general-purpose initial value random number does not change.

  The M1 counter is initialized when any of a system reset and a WDT reset is performed, and the M1 counter is not initialized when any of a periodic reset and an illegal access reset is performed.

  Further, the periodic reset monitor is initialized when any one of the system reset and the WDT reset is performed, and the periodic reset monitor is not initialized when any one of the periodic reset and the illegal access reset is performed.

  The arithmetic function is initialized when any of the system reset and the WDT reset is performed, and the arithmetic function is not initialized when any of the periodic reset and the illegal access reset is performed.

  The PWM output is initialized when any of the system reset and the WDT reset is performed, and the PWM output is not initialized when any of the periodic reset and the illegal access reset is performed.

[Internal function register]
Next, the internal function register shown in FIG. 12 will be specifically described with reference to FIG. In the figure, S indicates “system reset”, and W indicates “WDT reset”. R / W (Read / Write) indicates that R / W is readable and writable, R is only readable, and W is only writable. Also, description will be made with some functions omitted.

  The functions not illustrated include a random number maximum value register that determines the maximum value of the random number value to be updated by the random number circuit, an external latch signal permission register that determines an operation when the random number value is acquired, an external latch signal mode register, and the like. The registers relating to the random number circuit are included, and these initialization factors are a system reset and a WDT reset (see FIG. 23).

  As shown in FIG. 24, a RAM protect register (RAMPT) is assigned to the I / O space address 00h and the memory space address 1000h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT0) is assigned to the I / O space address 01h and the memory space address 1001h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT1) is assigned to the I / O space address 02h and the memory space address 1002h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT2) is assigned to the I / O space address 03h and the memory space address 1003h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC0) is assigned to the I / O space addresses 04h and 05h and the memory space addresses 1004h and 1005h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC1) is assigned to the I / O space addresses 06h and 07h and the memory space addresses 1006h and 1007h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC2) is assigned to the I / O space addresses 08h and 09h and the memory space addresses 1008h and 1009h. R / W is R / W, and initialization factors are S and W.

  A WDT control register (WDTCNT) is assigned to the I / O space address 0Ah and the memory space address 100Ah. R / W is R / W, and initialization factors are S and W.

  A WDT clear register (WDTCLR0) is assigned to the I / O space address 0Bh and the memory space address 100Bh. And R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR1) is assigned to the I / O space address 0Ch and the memory space address 100Ch. And R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR2) is assigned to the I / O space address 0Dh and the memory space address 100Dh. And R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR3) is assigned to the I / O space address 0Eh and the memory space address 100Eh. And R / W is W. There is no initialization factor.

  An interrupt request register (IRR) is assigned to the I / O space address 23h and the memory space address 1023h. R / W is R / W, and initialization factors are S and W.

  An interrupt permission register (IRR) is assigned to the I / O space address 24h and the memory space address 1024h. R / W is R / W, and initialization factors are S and W.

  An interrupt priority register (IPR) is assigned to the I / O space address 25h and the memory space address 1025h. R / W is R / W, and initialization factors are S and W.

  An external signal input / reset factor register (PINSTS) is assigned to the I / O space address 26h and the memory space address 1026h. R / W is R / W, and the initialization factor is S.

  A periodic reset monitor register (ITRMN) is assigned to the I / O space address 94h and the memory space address 1094h. R / W is R, and initialization factors are S and W.

  An operation data register (CDAT) is assigned to the I / O space address 95h and the memory space address 1095h. R / W is R / W, and initialization factors are S and W.

  A horizontal parity operation result register (CPTY) is assigned to the I / O space address 96h and the memory space address 1096h. R / W is R / W, and initialization factors are S and W.

  A checksum operation result register (CSUM) is assigned to the I / O space addresses 97h and 98h and the memory space addresses 1097h and 1098h. R / W is R / W, and initialization factors are S and W.

  A CRC16 operation result register (CCRC) is assigned to the I / O space addresses 99h and 9Ah and the memory space addresses 1099h and 109Ah. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC0) is assigned to the I / O space address 9Bh and the memory space address 109Bh. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC1) is assigned to the I / O space address 9Ch and the memory space address 109Ch. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC2) is assigned to the I / O space address 9Dh and the memory space address 109Dh. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC3) is assigned to the I / O space address 9Eh and the memory space address 109Eh. R / W is R / W, and initialization factors are S and W.

  A maker code register (MKCODE) is assigned to the I / O space addresses A2h, A3h and A4h, and the memory space addresses 10A2h, 10A3h and 10A4h. And R / W is R. There is no initialization factor.

  A product code register (PRCODE) is assigned to the I / O space addresses A5h to ACh and the memory space addresses 10A5h to 10ACh. And R / W is R. There is no initialization factor.

  A chip code register (CPCODE) is assigned to the I / O space addresses ADh to B0h and the memory space addresses 10ADh to 10B0h. And R / W is R. There is no initialization factor.

[RAM Protect]
Next, the RAM protection will be described. The RAM protect is a function of preventing the RAM from being rewritten by an erroneous operation.

  The operation of the RAM protection is as follows. After the system reset or the WDT reset has occurred, the RAM is in the RAM protected state. In the RAM protected state, data can be read from the RAM, but data cannot be written to the RAM. When writing data to the RAM, the RAM protection is set invalid in the RAM protection register (RAMPT). When the setting of the RAM access prohibition area of the RAMPT is set to invalid, the RAM access prohibition area exists when HRAMSTAT = 0000h and HRAMEND = 0000h are set even if the RAM access prohibition area of the HW parameter is set valid. Therefore, no illegal access reset occurs.

[RAM protect register]
Next, the RAM protector register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 25, in the RAM protect register, a symbol RAMPT is associated with bits 7 to 0 of a memory space address 1000h (I / O space address 00h). In the RAMPT, setting of RAM protection and control of a RAM access prohibition area are performed. At 00h, the RAM access prohibited area is set to be invalid, and the RAM protect is set to be invalid. In 01h, the RAM access prohibited area is set to be invalid, and the RAM protection is set to be valid. At 80h, the RAM access prohibited area is set to be valid, and the RAM protection is set to be invalid. At 81h, the RAM access prohibited area is set to be valid, and the RAM protect is set to be valid. A state other than these values is maintained. Note that R / W is R / W, and the initial value is 81h.

[Counter timer (CTC)]
Next, CTC will be described with reference to FIG. The microcomputer shown in FIG. 11 has three channels of 16-bit CTC.

  The operation of the CTC is as follows. The CTC counts down the set timer value and outputs an interrupt request signal to the interrupt controller when the timer value reaches 0000h. 0000h at this time is called a terminal count. Each channel of the CTC (CTC0 to CTC2) can be operated independently, so that interrupts can be generated at three types of time intervals.

  As shown in FIG. 26, since CTC0 and CTC1 can use the terminal count of CTC2 as a clock source, long time intervals can be easily created. For example, when the terminal count of CTC2 is set to the clock source of CTC0, the timer value of CTC2 is set to 2 msec, and CTC0 is set to 65,000 counts, 2 msec × 65,000 = 130 sec can be counted. The CTC is initialized when a system reset or a WDT reset occurs.

The operation mode of the CTC is as follows. The CTC has two operation modes, a one-shot timer mode that operates only once and an interval timer mode that operates repeatedly. The one-shot timer mode counts down from the set timer value, and stops counting down when the terminal count is reached. Then, when the terminal count is reached, one interrupt request is issued.
When the timer value is set to 5: 5 → 4 → 3 → 2 → 1 → 0 (stop)

In the interval timer mode, down counting is performed from the set timer value, and when the terminal count is reached, down counting is performed again from the set timer value. Then, each time the terminal count is reached, an interrupt request is repeatedly generated.
When the timer value is set to 5: 5 → 4 → 3 → 2 → 1 → 5 → 4 → ... (repeat)

  Regarding the setting of the timer value, the timer value of the CTC can be set to an arbitrary value or four types of fixed values (1 msec, 2 msec, 4 msec, 1.4890 msec).

To set an arbitrary value, a timer value is set in a CTC data register (CTC0 to CTC2), and a timer value setting method, an operation mode, a clock frequency division, and a clock source of a CTC control register (TMCNT0 to TMCNT2) are set.
Example of setting to generate an interrupt every 3 msec in CTC0 1. CTC0 = 012Ch Timer value = 300
2. TMCNT = 02h Timer value setting method = arbitrary value, operation mode = interval timer mode, clock division = 10 μsec, clock source = MLCK division

The fixed value is set by setting a timer value setting method, an operation mode, and a fixed value of the CTC control registers (TMCNT0 to TMCNT2).
Example of setting CTC0 to generate an interrupt every 4 msec 1. TMCNT = 0Bh Timer value setting method = fixed value, operation mode = interval timer mode, fixed value setting = 4 msec
No need to set CTC0 (CTC0 data register).

After the system reset and the WDT reset, the CTC stops counting operation of the CTC.
Activation of CTC is set in the following order.
1. The timer value is set in the CTC data register (CTC0-2).
2. Set the CTC control registers (TMCNT0-2).
When a fixed value is set in the timer value setting method, 1. Setting of the CTC data registers (CTC0 to CTC2) is unnecessary. It is activated simply by setting TMCNT0 to TMCNT2. If TMCNT0 to TMCNT2 is set even while the CTC is in the counting operation, it is updated with the settings of CTC0 to TMCNT2 and TMCNT0 to TMCNT2. The timer value during counting is counted down again from the set value of CTC0-2.

[CTC control register]
Next, the CTC control register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 27, in the CTC control register, bit 7 of memory space address 1001h (I / O space address 01h) is not used and is always 0. Note that R / W is R, and the initial value is 0.

  Bit 6 of the memory space address 1001h (I / O space address 01h) is associated with the symbol C0CKCEL, and bit 6 of the memory space address 1002h (I / O space address 02h) is associated with the symbol C1CKCEL. In C0CKCEL and C1CKCEL, the clock sources of CTC0 to CTC1 are set. At 0, it is set to the frequency division of MCLK, and at 1, it is set to the terminal count of CTC2. Note that R / W is R / W, and the initial value is 0.

  When C0CKCEL is set to 0, CTC0 is counted down by the clock set to C0CKCEL. When C0CKCEL is set to 1, CTC0 is counted down by the terminal count of CTC2. When C1CKCEL is set to 0, CTC1 is counted down by the clock set to C1CKCEL. When C1CKCEL is set to 1, CTC1 is counted down by the terminal count of CTC2.

  Bits 4 to 5 of memory space address 1001h (I / O space address 01h) are associated with symbol C0CLK, and bits 5 to 4 of memory space address 1002h (I / O space address 02h) are associated with symbol C1CLK. The symbol C2CLK is associated with bits 4 to 5 of the memory space address 1003h (I / O space address 03h). In C0CLK, C1CLK, and C2CLK, clock frequency division setting of CTC0 to CTC2 is performed. Then, when MLCK = 20 MHz, 00 is set to 10 μsec, 01 is set to 1 μsec, 10 is set to 5 μsec, and 11 is set to 20 μsec. Note that R / W is R / W, and the initial value is 0.

  CTC2 counts down with the clock set to C2CLK.

  Bits 3 and 2 of memory space address 1001h (I / O space address 01h) are associated with symbol TMCEL0, and bits 2 and 3 of memory space address 1002h (I / O space address 02h) are associated with symbol TMCEL1. The symbol TMCEL2 is associated with bits 2 and 3 of the memory space address 1003h (I / O space address 03h). In TMCEL0, TMCEL1, and TMCEL2, fixed values of CTC0 to CTC2 are set. Then, 00 is set to 1 msec (timer value = 03E8h), 01 is set to 2 msec (timer value = 07D0h), 10 is 4 msec (timer value = 0FA0h), and 11 is 1.489 msec (timer value = 03E8h). 05D1h). Note that R / W is R / W, and the initial value is 0.

  The setting time of TMCEL0 to TMCEL2 is a predetermined time when the MCLK frequency setting (HSYSCLK) of the system setting (HSYSCNT) of the HW parameter is set to the same frequency as the system clock (MCLK).

  The symbol TMMOD0 is associated with bit 1 of the memory space address 1001h (I / O space address 01h), and the symbol TMMOD1 is associated with bit 1 of the memory space address 1002h (I / O space address 02h). Symbol TMMOD2 is associated with bit 1 of address 1003h (I / O space address 03h). In TMMOD0, TMMOD1, and TMMOD2, the operation modes of CTC0 to CTC2 are set. At 0, the one-shot timer mode is set, and at 1, the interval timer mode is set. Note that R / W is R / W, and the initial value is 0.

  Symbol TMFVM0 is associated with bit 0 of memory space address 1001h (I / O space address 01h), and symbol TMFVM1 is associated with bit 0 of memory space address 1002h (I / O space address 02h). Symbol TMFVM2 is associated with bit 1 of address 1003h (I / O space address 03h). In TMFVM0, TMFVM1, and TMFVM2, the timer value setting method for CTC0 to CTC2 is set. At 0, it is set to an arbitrary value, and at 1 it is set to a fixed value. Note that R / W is R / W, and the initial value is 0.

  When 0 is set to TMFVM0 to 2, the setting of TMCEL0 to 2 is invalid. When 1 is set to TMFVM0 to TMFVM2, the settings of C0CKSEL, C1CKSEL, C0CLK, C1CLK, and C2CLK are invalid. At this time, the timer values of CTC0 to CTC2 are any one of 03E8h, 07D0h, 0FA0h, and 05D1h, and the clock division is performed at 1 μsec, depending on the set values of TMSEL0 to TMSEL2. It does not affect the set values of C0CLK, C1CLK, C2CLK, and the CTC data registers (CTC0 to CTC2).

[CTC data register]
Next, the CTC control register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 28, in the CTC control register, symbol CTC0 (lower order) is associated with bits 7 to 0 of memory space address 1004h (I / O space address 04h), and memory space address 1005h (I / O space Bits 7 to 0 of the address 05h) are associated with the symbol CTC0 (upper). In CTC0, the timer value of CTC0 is set. When reading, the count value is read. In the case of writing, the value to be written increases by 65,536 in 0000h, 1 in 0001h, and thereafter by 1, and 65,535 is written in FFFFh. Note that R / W is R / W, and the initial value is FFFFh.

  Bits 7 to 0 of memory space address 1006h (I / O space address 06h) are associated with symbol CTC1 (lower order), and bits 7 to 0 of memory space address 1007h (I / O space address 07h) are symbol CTC1. (Upper). In CTC1, the timer value of CTC1 is set. Otherwise, CTC1 is the same as CTC0.

  Bits 7-0 of memory space address 1008h (I / O space address 08h) are associated with symbol CTC2 (lower order), and bits 7-0 of memory space address 1009h (I / O space address 09h) are symbol CTC2. (Upper). In CTC2, the timer value of CTC2 is set. Otherwise, CTC2 is the same as CTC0.

  As described above, the timer values of CTC0 to CTC2 are set in the CTC data register. When 0000h is set, 65,536 is set. This register is unnecessary when 1 (fixed value) is set in TMFVM0 to TMFVM2 of the CTC control register (TMCNT0 to 2).

  Also, the count values of CTC0 to CTC2 can be read from this register. The count value can be read even when 1 (fixed value) is set in TMFVM0 to 2 of the CTC control registers (TMCNT0 to 2). The reading of the count value is performed after activating the CTC.

  When the count value is read using the 2-byte read instruction, the count value being updated is not read. When the upper and lower bits are separately read by a 1-byte read command, the count value may be updated halfway.

[Watchdog timer (WDT)]
The watchdog timer (WDT) can quickly detect a program operation abnormality due to noise or the like, and return to a normal state by generating a WDT reset.

  The WDT operates as follows. For the WDT, a time of 0.1 sec to 12.7 sec (in the case of MCLK = 20 MHz) can be set in WDT control registers (WDTCNT) in 0.1 μsec units. If the WDT is not cleared within the set time, a WDT reset occurs, and the CPU core and internal functions are reset. If the WDT is not cleared again within a set time from the time when the WDT was cleared, a WDT reset occurs, so it is necessary to continuously clear the WDT.

  When a WDT reset occurs, its cause can be confirmed by an external signal input / reset cause register (PINSTS). WDT is initialized when a system reset occurs.

  The WDT is activated when the same value is set in the WDT control register (WDTCNT) twice consecutively. Once activated, it cannot be stopped and the set value of WDTCNT cannot be changed.

  As shown in FIG. 29, the clearing of the WDT includes a simple clear mode and a cyclic clear mode. In the simple clear mode, the WDT is cleared by setting 18h in the WDT clear register (WDTCLR0) other than the set time. Thereafter, 18h is repeated for WDTCLR0 except for the set time. In the circulation clear mode, the WDT is cleared by setting 60h in the WDT clear register (WDTCLR1) within the first set time. Within the next set time, the WDT clear register (WDTCLR2) is set to 03h to clear the WDT, and within the next set time, the WDT clear register (WDTCLR3) is set to 24h to clear the WDT. Thereafter, the setting in this order is repeated. If a different order or a different value is set, the WDT is not cleared, and does not affect the operation of the WDT.

[WDT control register]
Next, the CTC control register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 30, in the WDT control register, symbol WDTND is associated with bit 7 of memory space address 100Ah (I / O space address 0Ah). In WDTND, a clear mode is set. At 0, the simple clear mode is set, and at 1, the cyclic clear mode is set. Note that R / W is R / W, and the initial value is 0.

  Bits 6 to 0 of the memory space address 100Ah (I / O space address 0Ah) are associated with the symbol WDT. In the WDT, a timer is set. When MCLK = 20 MHz, the WDT can be stopped at 00h, 0.1 μsec can be set as the minimum value at 01h, and 12.7 sec can be set as the maximum value at 7Fh. Note that R / W is R / W, and the initial value is 0.

  When setting WDTCNT, the same value is set twice within 15 μsec (when MCLK = 20 MHz). Once set, WDTCNT cannot be changed. If 00h is set to WDTCNT twice consecutively, WDT will not start. Even if 00h is set twice consecutively after starting the WDT, the WDT cannot be stopped.

[WDT clear register]
Next, the WDT clear register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 31, in the WDT clear register, the symbol WDTCLR0 is associated with bits 7 to 0 of the memory space address 1008h (I / O space address 08h). In WDTCLR0, WDT clear setting in the simple clear mode is performed. Then, it is set to 18h. Note that R / W becomes W.

  The symbol WDTCLR1 is associated with bits 7 to 0 of the memory space address 1009h (I / O space address 09h). In the WDT CLR1, the setting of the WDT clear in the cyclic clear mode is performed. Then, it is set to 60h. Note that R / W becomes W.

  The symbol WDTCLR2 is associated with bits 7 to 0 of the memory space address 100Dh (I / O space address 0Dh). In WDTCLR2, setting of WDT clear in the cyclic clear mode is performed. Then, it is set to 03h. Note that R / W becomes W.

  Bits 7 to 0 of the memory space address 100Eh (I / O space address 0Eh) are associated with the symbol WDTCLR2. In WDTCLR3, the setting of WDT clear in the cyclic clear mode is performed. Then, it is set to 24h. Note that R / W becomes W.

  The order of WDT clear (60h → 03h → 24h) in the circulation clear mode is maintained when a WDT reset occurs. Initialized when a system reset occurs.

[Interrupt controller]
Next, the interrupt controller will be described. FIG. 32 is a block diagram of the interrupt controller.

  As an interrupt operation, first, an interrupt factor and an interrupt are set.

The interrupt factors include an input signal of an interrupt input / general-purpose input terminal (INP) and terminal counts of CTC0 to CTC2. An interrupt occurs in the following cases.
1. 1. When the INP terminal goes low. 2. When CTC0 reaches the terminal count. 3. When CTC1 reaches the terminal count. When CTC2 reaches terminal count

  When the INP terminal is used as an interrupt input signal, 1 (used as an interrupt input terminal) is set in the INP terminal function setting (HPORTEN) of the reset period / INP terminal setting (HRSTCNT) of the HW parameter.

  The INP terminal can select an INT interrupt input or an NMI interrupt input by setting an interrupt input terminal (HPORTMD) of the HRSTCNT.

  The four interrupt factors can be individually set to enable or disable the interrupt by an interrupt enable register (IER). Further, the priority of interrupt can be set by an interrupt priority register (IPR).

  For interrupts other than NMI, the acceptance of the interrupt request and the inhibition of the acceptance of the interrupt request are made independently of the interrupt controller by an interrupt master permission flag (IMF) assigned to the program status word (PSW) of the CPU core. Can be set.

  The setting of the IMF is performed by an EI (IMF = 1) instruction and DI (IMF = 0).

  When the CPU core is in the interrupt permitted state (IMF = 1), the interrupt controller outputs an interrupt request signal to the CPU core.

  In the case of an NMI interrupt, an interrupt request signal is output to the CPU core regardless of whether the interrupt is enabled or disabled.

  The interrupt request register (IRR), interrupt enable register (IER), and interrupt priority register (IPR) are initialized when a system reset or a WDT reset occurs.

The interrupt processing is started in the next step.
1. When an interrupt occurs, the cause of the interrupt is latched in an interrupt request register (IRR).
2. An interrupt request signal is output to the CPU core according to the setting state of IER, IPR, and IMF.
3. The CPU core determines whether there is an interrupt request during the M1 cycle.
4. If there is an interrupt request, the instruction fetched in the M1 cycle is discarded, and the program counter (PC) is not updated. Since this PC is pushed onto the stack in "8." below, execution of the program is restarted from this PC when the interrupt processing is completed. While the LDIR and CPIR instructions are being executed, there is an M1 cycle each time the processing is repeated. At this time, the presence or absence of an interrupt request is also determined.
5. M1 and IPEQ0 are simultaneously set to L level, indicating that the CPU core has accepted the interrupt.
6. The bit corresponding to the interrupt cause of IRR is cleared to 0.
7. The head address of the interrupt processing corresponding to the interrupt factor is read from the interrupt processing vector table.
8. The data is pushed onto the stack in the order of PSW, PC upper byte (PCH), and PC lower byte (PCL).
9. The IMF is cleared to 0, and the interrupt is disabled.
10. The address read from the vector table for interrupt processing is set in the PC counter.
11. Start interrupt processing.
The above processing is performed when the interrupt request is an INT interrupt and CTC0 to CTC2 interrupts. In the case of an NMI interrupt, an interrupt request signal is output regardless of the settings of IER, IPR, and IMF.

  PSW and PC are automatically saved on the stack during interrupt acceptance processing, but general-purpose registers (W, A, B, C, D, E, H, L, IX, IY) of the CPU core are automatically saved. Not done. Evacuate the program as necessary.

  In addition. There are a method of saving general-purpose registers by a PUSH instruction and a method of switching banks of general-purpose registers. For example, in the case of a system in which the interrupt processing is not started in multiples, the normal processing uses the bank 0 of the general-purpose register, executes the LD, RBS, 1 (RBS = 1) instruction at the head of the interrupt processing, and executes the bank processing. By switching to 1, the register in bank 0 can be saved.

  Since the register bank selector (RBS) is included in the PSW, when the return instruction (RETI or RETN) of the interrupt processing is executed, the PSW returns from the stack and automatically switches to bank 0.

  No special measures other than execution of the return instruction (RETI or RETN) are required to end the interrupt processing. When the return instruction is executed, the PSW and the PC are returned from the stack and return to the processing before the start of the interrupt processing. The clearing of the interrupt factor is automatically performed by the interrupt controller when the interrupt request is received. Since the IMF and the RBS are included in the PSW, a return instruction automatically returns from the stack. Therefore, there is no need to execute the EI command or the RBS switching before the end of the interrupt processing.

  Since the interrupt can be accepted immediately after the execution of the EI instruction, if the EI instruction and the return instruction are described consecutively, a new interrupt may be accepted when the return instruction is fetched.

FIG. 33 shows an example of the interrupt processing procedure when executing the interrupt processing in CTC0. The details of the example of FIG. 33 are as follows.
1. In the main routine, bank 0 (RBS = 0) of general-purpose registers is used.
2. In the CTC0 interrupt routine, bank 1 (RBS = 1) of the general-purpose register is used.
3. The end of the interrupt processing is only execution of RETI.

[Interrupt request register]
Next, an interrupt request register in the internal function register shown in FIG. 24 will be described with reference to FIG. The interrupt request register is a register that latches an interrupt request signal.

  As shown in FIG. 34, in the interrupt request register, the symbol IRR3 is associated with bit 7 of the memory space address 1023h (I / O space address 23h). In the IRR3, a CTC2 interrupt request is set. In the case of reading, when 0, no interrupt request is set, and when 1, an interrupt request is set. When writing, it is set to clear when it is 0, and it is set to do nothing when it is 1. Note that R / W is R / W, and the initial value is 0.

  The symbol IPR2 is associated with bit 6 of the memory space address 1023h (I / O space address 23h). In the IRR2, a CTC1 interrupt request is set. Otherwise, IRR2 is the same as IRR3.

  The symbol IPR1 is associated with bit 5 of the memory space address 1023h (I / O space address 23h). In the IRR1, a CTC0 interrupt request is set. Otherwise, IRR1 is the same as IRR3.

  Bit 4 of the memory space address 1023h (I / O space address 23h) is associated with the symbol IPR0. In IRR0, an INT / NMI interrupt request is set. Otherwise, IRR0 is the same as IRR3.

  Bits 3 to 30 of memory space address 1023h (I / O space address 23h) are not used and are always 0. Note that R / W is R, and the initial value is 0.

  When the CPU core receives the interrupt request, the interrupt controller automatically clears the interrupt request to zero. If 0 is set, it can be cleared, but if 1 is set, an interrupt request cannot be set.

  Since the IRR is located before the interrupt enable register (IER), the IRR is latched even if the interrupt factor is set to disable the interrupt by the IER. When ignoring an interrupt request generated while the interrupt is prohibited, the interrupt request is cleared by setting IRR to 0 before permitting the interrupt.

[Interrupt enable register]
Next, the interrupt permission register in the internal function register shown in FIG. 24 will be described with reference to FIG. The interrupt permission register is a register that permits an interrupt request signal.

  As shown in FIG. 35, in the interrupt permission register, the symbol IER3 is associated with the bit 7 of the memory space address 1024h (I / O space address 24h). In IER3, CTC2 interrupt permission is set. When the value is 0, the interrupt is prohibited, and when the value is 1, the interrupt is permitted. Note that R / W is R / W, and the initial value is 0.

  Symbol IER2 is associated with bit 6 of memory space address 1024h (I / O space address 24h). In IER2, CTC1 interrupt permission is set. Otherwise, IER2 is the same as IER3.

  Bit 5 of the memory space address 1024h (I / O space address 24h) is associated with the symbol IER1. In IER1, CTC0 interrupt permission is set. Otherwise, IER1 is the same as IER3.

  Bit 4 of the memory space address 1024h (I / O space address 24h) is associated with the symbol IER0. In IER0, setting of INT interrupt permission is performed. Otherwise, IER0 is the same as IRR3.

  Bits 0 to 3 of the memory space address 1024h (I / O space address 24h) are unused and are always 0. Note that R / W is R, and the initial value is 0.

  If an interrupt is permitted while the interrupt request signal is latched in the interrupt request register (IER), the interrupt request signal is immediately output to the CPU core.

[Interrupt priority register]
Next, an interrupt permission register in the internal function register shown in FIG. 24 will be described with reference to FIG. The interrupt priority register is a register for setting the priority of the interrupt factors (INT, CTC0, CTC1, CTC2).

  As shown in FIG. 36, in the interrupt priority register, the symbol IPR3 is associated with bits 7 to 6 of the memory space address 1025h (I / O space address 25h). In IPR3, CTC2 priority is set. At 00, the priority is set to the lowest level 0. In addition, at the time of 01, the priority is set to level 1 which has a higher priority than 00 and has a lower priority than 10. In addition, at the time of 10, the priority is set to level 2 having a higher priority than 01 and having a lower priority than 11. In the case of 11, the highest priority is set to level 3. Note that R / W is R / W, and the initial value is 0.

  Bits 5 to 4 of the memory space address 1025h (I / O space address 25h) are associated with the symbol IPR2. In IPR2, CTC1 priority is set. Otherwise, IPR2 is the same as IPR3.

  Bits 3 and 2 of the memory space address 1025h (I / O space address 25h) are associated with the symbol IPR1. In IPR1, CTC0 priority is set. Otherwise, IPR1 is the same as IPR3.

  Bits 1 to 0 of the memory space address 1025h (I / O space address 25h) are associated with the symbol IPR0. In IPR0, INT priority is set. Otherwise, IPR0 is the same as IPR3.

  If a plurality of interrupt factors occur at the same time, the interrupt factor with a higher priority outputs an interrupt request signal to the CPU core. There are four levels of priority, with level 3 being the highest and level 0 the lowest. Also, at the same level, INT, CTC0, CTC1, CTC2 are in the order of higher priority.

[External signal input / reset source register]
Next, an interrupt permission register in the internal function register shown in FIG. 24 will be described with reference to FIG. The external signal input / reset factor register can know the state of the interrupt input / general-purpose input terminal (INP) and the random number external latch 0 to 2 terminals (EXLATCH0 to 2) and the reset generation factor.

  As shown in FIG. 37, in the external signal input / reset factor register, the symbol WDTRST is associated with bit 7 of the memory space address 1026h (I / O space address 26h). In WDTRST, the setting of the WDT reset occurrence is performed. Then, in the case of reading, it is set that it does not occur when the value is 0, and that it occurs when the value is 1. In the case of writing, it is set to clear when 0, and to do nothing when 1. Note that R / W is R / W, and the initial value is 0.

  The symbol IARST is associated with bit 6 of the memory space address 1026h (I / O space address 26h). In IARST, the setting of occurrence of illegal reset is performed. Other than that, IARST is the same as WDTRST.

  The symbol INTRST is associated with bit 5 of the memory space address 1026h (I / O space address 26h). In the INTRST, the setting of the occurrence of the periodic reset is performed. Otherwise, INTST is the same as WDTRST.

  Bit 4 of the memory space address 1026h (I / O space address 26h) is unused and is always 0. Note that R / W is R, and the initial value is 0.

  The symbol INPS is associated with bit 3 of the memory space address 1026h (I / O space address 26h). In INPS, an INP terminal number is set. When 0, the terminal number is set to L, and when 1, the terminal number is set to R. Note that R / W becomes R.

  The symbol LTC2 is associated with bit 2 of the memory space address 1026h (I / O space address 26h). In the LTC2, an EXLATCH2 terminal number is set. Other than that, LTC2 is the same as INPS.

  The symbol LTC1 is associated with bit 1 of the memory space address 1026h (I / O space address 26h). In the LTC1, an EXLATCH1 terminal number is set. Other than that, LTC1 is the same as INPS.

  The symbol LTC0 is associated with bit 0 of the memory space address 1026h (I / O space address 26h). In the LTC0, an EXLATCH0 terminal number is set. Other than that, LTC0 is the same as INPS.

  For WDTRST, IARST, and INTRST, the state of the corresponding reset factor is set. WDTRST, IARST, and INTRST are held until a system reset occurs, and are cleared to 0 after the system reset. To clear WDTRST, IARST, and INTRST, set 0.

  INPS, LTC2, LTC1, and LTC0 have the signal levels of the corresponding terminals set as they are. In the INPS, the signal level of the INP terminal is set regardless of the setting state of the INP terminal function setting (HPORTEN) in the reset period of the HW parameter / INP terminal setting (HRSTCNT).

  A noise filter of five CPU clocks is inserted in the INP terminal. A noise filter of 128 random number clocks is inserted in the EXLATCH0 to EXLATCH2 terminals. Therefore, when a continuous L level signal (or H level signal) of 5 clocks or 128 clocks is input, 0 (or 1) is set.

  PINSTS is initialized when a system reset occurs.

[Operation of random number]
The random number circuit includes an 8-bit fixed-length random number circuit, a 16-bit fixed-length random number circuit, an 8-bit variable-length random number circuit, and a 16-bit variable-length random number circuit. The start value of the first week after the system reset is updated every time the system is reset. The pattern of the random number sequence is automatically updated. The 16-bit fixed-length random number can transpose the bit sequence. For the 16-bit fixed-length random number, the operation clock can be selected from 又 は of MCLK or Ｘ of EXCLK. A random number value can be latched by three random number external latch terminals. Equipped with a function to determine the abnormality of the random number circuit.

  The 8-bit fixed-length random number circuit and the 16-bit fixed-length random number circuit start automatically after a system reset or a WDT reset. The 8-bit variable-length random number circuit and the 16-bit variable-length random number circuit are stopped after the system reset or the WDT reset, and are activated when the maximum value is set. The random number circuit is initialized by a system reset or a WDT reset. When a periodic reset or illegal access reset occurs, the operation continues without affecting the random number function.

  The random number circuit updates the random number value while taking discrete values with the initial value as a start value, and causes all values to appear once without duplication. After all the values have appeared, another value is used as a start value, the appearance pattern of the sequence is changed to another pattern, and all the values are updated again while taking discrete values.

  The random number value is updated at the rising edge of the random number clock (1/2 of MCLK or 1/2 of EXCLK). A random number value can be latched by a signal input to the random number external latch 0 to 2 terminals (EXLATCH0 to 2).

  Holding or updating of the latch data register can be set by an external latch signal mode register (RDEXLM). When RDEXLM is set to 0 (hold), a random number value is latched in the random number latch data register only when a signal is input to EXLATCH0 to EXLATCH2 with the random number latch data register cleared. When there is latch data in the random number latch data register, a signal is input to EXLATCH0 to EXLATCH 2 and the random number latch data register is not updated and the latch data up to that time is held. When RDEXLM is set to 1 (update), the latch data is updated each time a signal is input to EXLATCH0-2.

[Periodic reset monitor register]
Next, the periodic reset monitor register in the internal function register shown in FIG. 24 will be described with reference to FIG. The periodical reset monitor can read the value of the periodical reset timer counter.

  As shown in FIG. 38, in the periodic reset monitor register, the symbol ITRMN is associated with bits 7 to 0 of the memory space address 1094h (I / O space address 94h). In the ITRMN, the setting of the periodic reset monitor is performed. Then, it is set to one of 00h to FFh. Note that R / W is R, and the initial value is 0.

  The periodic reset operates according to a periodic reset setting (HPRST) of the HW parameter. The periodic reset counter is initialized to 00h by a system reset or a WDT reset, and is counted up by a periodic reset clock. The periodic reset counter value can be read from the periodic reset monitor register (ITRMN).

[Register configuration]
Next, the register configuration will be described.

[General-purpose registers]
As shown in FIG. 39, two register banks, bank 0 and bank 1, are provided as register banks. Each register bank includes eight 8-bit general registers W, A, B, C, D, E, H, L and two 16-bit general registers IX and IY. W, A, B, C, D, E, H, and L are used for 8-bit transfer and operation. Further, these registers can be combined and used as WA, BC, DE, and HL. WA, BC, DE, HL, IX, and IY can be used for 16-bit transfer and calculation. The general-purpose register is initialized at 00h or 0000h at the time of system reset, WDT reset, periodic reset, and illegal access reset.

[Program status word (PSW)]
Next, the PSW shown in FIG. 39 will be described with reference to FIG. The PSW is a register that holds the state of the operation result and the execution result of the instruction, and is composed of eight types of flags. The PSW is cleared to 00h at the time of a system reset, a WDT reset, a periodic reset, and an illegal access reset due to the initialization with the CPU core described above.

  As shown in FIG. 40, in the PSW, a symbol JF (jump status flag) is associated with bit 7. JF is a flag used in a 1-byte-length JRS instruction or the like. As shown in the example in the figure, there are a case where a zero flag is set and a case where a carry flag is set by an instruction. Also, as shown in the example in the figure, in the case of INC and DEC instructions, the carry flag does not change, but the jump status flag is set under the condition that the carry flag is set.

  Bit 6 is associated with ZF (zero flag). ZF is set to 1 when the operation result or transfer data is 00h (8 bits) or 0000h (16 bits), and is cleared to 0 otherwise. The exchange command (XCH dst, src) is set when the value stored in dst is 0.

  Further, a CF (carry flag) is associated with bit 5. The carry or borrow at the time of calculation is set in CF. In the case of a division instruction, 1 is set when the division by 0 or the division result is 0100h or more. In the case of the INC and DEC instructions, the carry flag does not change and retains its value even when carry or borrow occurs.

  Further, HF (half carry flag) is associated with bit 4. In HF, a carry or borrow to the fourth bit is set at the time of an 8-bit operation.

  In addition, SF (sign flag) is associated with bit 3. SF is set to 1 when the calculation result MBS is 1, and cleared to 0 otherwise.

  Further, VF (overflow flag) is associated with bit 2. VF is set to 1 when the operation result overflows, and cleared to 0 otherwise.

  Further, RBS (register bank selector) is associated with bit 1. RBS indicates the bank selected by the general-purpose register.

  Also, bit 0 is associated with an IMF (interrupt master permission flag). The IMF becomes IMF = 0 by the DI instruction, and the acceptance of the maskable interrupt is prohibited. With the EI instruction, IMF = 1, and acceptance of the maskable interrupt is permitted.

[Stack pointer (SP)]
Next, the SP shown in FIG. 39 will be described with reference to FIG. SP is a 16-bit register indicating the top address of the stack.

  As shown in FIG. 41, it is post-decremented at the time of a PUSH instruction, at the time of a subroutine call, or at the time of receiving an interrupt, and is pre-incremented at the time of a POP instruction or a return instruction. At the time of a subroutine call (CALL instruction, CALLV instruction), PUSH is performed in the order of higher and lower return addresses. At the time of accepting an interrupt, a PUSH is performed in the order of a program status word, a return address higher, and a lower address. The SP is initialized at 01FFh at system reset, WDT reset, periodic reset, and illegal access reset.

[Program counter (PC)]
Next, the PC shown in FIG. 39 will be described. This is a 16-bit register indicating the address where the instruction to be executed next is stored. The system is initialized to 8000h by a system reset, a WDT reset, a periodic reset, and an illegal access reset. After the system reset, the WDT reset, the periodic reset, and the illegal access reset are released, the program execution is started from the address 8000h.

[Overview of operation at startup of microcomputer]
In the microcomputer configured as described above, when power is supplied and reset signals are input from the reset circuit 49 and the reset circuit 95, a system reset is performed.

  By this system reset, each function of the microcomputer performs the operation described as the change in the operation due to the reset factor (see FIG. 23). For example, the initialization of the CPU core is performed, and accordingly, the PSW is cleared to 00h. Therefore, the IMF becomes 0 and the interrupt prohibition state is set. In addition, an initial value is set in an internal function register (CTC control register, register relating to a random number circuit, etc.) for which system reset is determined as an initialization factor (see FIG. 24).

  Further, various functions are set with reference to the HW parameters (see FIG. 14). Here, in the HW parameter, it is determined whether or not a condition that the microcomputer does not start (see FIG. 22) is satisfied. If the condition is satisfied, the microcomputer does not start.

  Thereafter, after the set system reset time has elapsed, the initialization processing shown in FIGS. 5 and 6 is executed according to the user program (the program stored in “Program / Data” in FIG. 12).

[Modification]
In the above embodiment, the power interruption process is executed in the timer interrupt process (main) shown in FIGS. 8 and 9; however, the power interruption process may be executed by an NMI interrupt (non-maskable interrupt).

  In this case, when the interrupt request signal is input, an NMI interrupt is generated and the power interruption process is executed regardless of the interrupt permission / prohibition state. In the power interruption processing, first, the interruption permission / inhibition state immediately before the power interruption is backed up and set to the interruption inhibition. Next, a process similar to the power interruption process (main) shown in FIG. 10 is executed. Then, when the microcomputer is started up and the initial setting process is executed, the process of Sa17 in FIG. 6 is not performed, and the interruption permission / prohibition state is restored based on the interruption permission / prohibition state when the power is turned off. Let it.

  In the case where the power interruption process is performed as described above, if the value set in the vector table shown in FIG. 13 is a value other than 0000h, 8000h to HPRGEND, and if the condition for not starting shown in FIG. Restrict launching. That is, when the value of INT / NMI at the addresses A7A0h to A7A1h in the vector table is a value other than 0000h and 8000h to HPRGEND, the activation of the microcomputer is restricted if the condition of not starting shown in FIG. 22 is satisfied. As a result, it is possible to prevent unintended non-maskable interrupt processing from being performed.

  Further, in this modification, during the period (for example, three cycles) from the input of the NMI interrupt request signal to the occurrence of the NMI interrupt, the condition for generating the timer interrupt process (main) is satisfied. It is shorter than the period (for example, 4 cycles) from when the timer interrupt occurs until the timer interrupt occurs. For this reason, the power interruption processing can be suitably performed.

  Note that, in the present modified example, an example in which the power interruption processing (main) and the initial setting processing are performed is described, but the power interruption processing (sub) and the initial setting processing (sub) performed by the sub control unit 91 are performed. Is also good.

[Effects of the above embodiment]
In the above-described embodiment, the interrupt is permitted after the timer interrupt is set in the initial setting process, and when the value set in the vector table is a value other than 0000h, 8000h to HPRGEND, the activation of the microcomputer is limited ( In this example, the portions shown in FIGS. 5, 6, and 22).
Therefore, execution of unintended interrupt processing can be prevented in advance.

In the above embodiment, if TMCNT0 to TMCNT2 is set even while the CTC is counting, the settings of CTC0 to TMCNT2 and TMCNT0 to 2 are updated, and the timer value during counting is again reduced from the set value of CTC0 to CTC2. Counting (in this example, the portions shown in FIGS. 27 and 28).
Therefore, execution of unintended interrupt processing can be prevented in advance.

In the above embodiment, when a system reset is performed and the interrupt controller is initialized, initial values are set in the interrupt request register, the interrupt permission register, and the interrupt priority register (in this example, FIG. 23). And the part shown in FIG. 32).
Therefore, it is possible to prevent in advance that the interrupt process is executed with an unintended setting.

In the above embodiment, when the function of the program end address is used, when the symbol is HPRGEND, and when the set content is the program end address, illegal access is made to the HPRGEN1 to A6FFh areas. An access reset occurs. (In this example, the part shown in FIG. 21).
Therefore, execution of an unauthorized program can be prevented.

In the above-described embodiment, in the initial setting process, the interrupt is set to be prohibited before the timer interrupt is set (in this example, the portion that performs the process of Sa1 in FIG. 5).
Therefore, execution of unintended interrupt processing can be prevented in advance.

In the above embodiment, in the random number circuit operation mode setting (related symbol name: HRDMD), when HEMDD bit 3 = 1, or in the system setting (related symbol name: HSYSCNT), HSYSCNT bit 5 = 1, HSYSCNT bit 6 = 1 and HSYSCNT bit 7 = 1, the activation of the microcomputer is limited (in this example, the portion shown in Fig. 22).
Therefore, it is possible to prevent an unintended setting from being made in advance.

In the above embodiment, the interrupt is permitted after setting the random number generation circuit in the initial setting process, and when the value set in the vector table is a value other than 0000h, 8000h to HPRGEND, the activation of the microcomputer is limited ( In this example, the portions shown in FIGS. 5, 6, and 22).
Therefore, execution of unintended interrupt processing can be prevented in advance.

In the above embodiment, when RDEXLM is set to 0 (hold), a random number value is latched in the random number latch data register only when a signal is input to EXLATCH0 to EXLATCH2 with the random number latch data register cleared. When 1 (update) is set to RDEXLM, the latch data is updated each time a signal is input to EXLATCH0 to EXLATCH (in this example, the portion indicated by [random number operation]).
Therefore, it is possible to prevent an unintended random number value from being captured.

In the above embodiment, when the system reset is performed to initialize the random number circuit, an initial value is set in each register related to the random number circuit (in this example, a portion shown in FIG. 23).
Therefore, it is possible to prevent the numerical data that is the random number value from being updated by an unintended setting.

In the above embodiment, interrupts are prohibited during the initial setting process, and when the value set in the vector table is a value other than 0000h, 8000h to HPRGEND, the activation of the microcomputer is restricted (in this example, FIGS. 6, the part shown in FIG. 22).
Therefore, execution of unintended interrupt processing can be prevented in advance.

In the above embodiment, one of the initializations 1 to 4 is selected and executed according to the initialization condition (in this example, a portion indicated by [about initialization]).
Therefore, execution of unintended interrupt processing can be prevented in advance.

In the above embodiment, the interrupt is set to be prohibited before the output port is initialized (in this example, the interrupt is prohibited before Sm3 in FIG. 10).
Therefore, output of unintended data can be prevented.

In the above-described embodiment, in the power interruption processing, the interrupt permission / inhibition state at the time of power interruption is backed up, and the interruption permission / prohibition state at the time of power interruption is restored by the initial setting processing. In the case of a value other than 8000h to HPRGEND, the activation of the microcomputer is restricted (in this example, [modification], the portion shown in FIG. 22).
Therefore, execution of unintended interrupt processing can be prevented in advance.

In the above embodiment, when the value of INT / NMI at addresses A7A0h to A7A1h of the vector table is a value other than 0000h and 8000h to HPRGEND, the activation of the microcomputer is restricted (in this example, [Modification], FIG. 22). Part shown).
Therefore, execution of unintended interrupt processing can be prevented in advance.

In the above embodiment, the period from the input of the NMI interrupt signal to the occurrence of the NMI interrupt is longer than the period from the time when the condition for generating the timer interrupt processing (main) is satisfied to the time when the timer interrupt is generated. Is also short (in this example, the portion shown in [Modification]).
Therefore, the power interruption processing can be suitably performed.

[Other variations]
In the above embodiment, the example in which the present invention is applied to the initial setting process, the timer interrupt process (main), and the power interruption process (main) by the main control unit 41 has been described. The present invention may be applied to timer interrupt processing (sub) and power interruption processing (sub).

  [About gaming machines]

  As described above, in the above embodiment, the slot machine has been described as an example. However, for example, the configuration shown in the above embodiment is applied to a pachinko game machine using a game ball, and the invention according to the claims Can be realized.

  Further, in the above-described embodiment, the slot machine for setting the number of bets using medals and credits has been described as an example. However, the present invention is not limited to this. For example, gaming machines used in pachinko gaming machines Claims wherein the configuration shown in the above-described embodiment is applied to a slot machine for setting a bet amount using a ball or a fully credit type slot machine for setting a bet amount using only credits. Can be realized. When a game ball is used as a game medium, for example, when one medal corresponds to five game balls, and when the number of bets is set to 3 in the above-described embodiment, 15 game balls are used. Is used to set the number of bets.

  Further, the gaming machine of the present invention is not limited to one using only one of a plurality of types of gaming values such as medals and gaming balls. A game value may be used together. That is, it is possible to set a bet amount and play a game by using any of a plurality of types of gaming values such as medals and game balls, and to generate a plurality of types of games such as medals and game balls by winning. A gaming machine capable of paying out any of the utility values is also included in the gaming machine of the present invention.

1 Slot machine 2L, 2C, 2R Reel 6 MAXBET switch 7 Start switch 8L, 8C, 8R Stop switch 41 Main control unit 41a CPU
41b ROM
41c RAM
91 Sub-control unit 91a CPU
91b ROM
91c RAM

Claims (1)

In gaming machines that can play games,
Storage means for storing the program;
A microcomputer that executes processing according to a program stored in the storage means,
The program includes an interrupt program executed in response to the occurrence of the interrupt,
The microcomputer includes :
When the interrupt is enabled, the interrupt process execution means for executing processing in accordance with the interrupt program based on該割write,
Address storage means having a storage area capable of storing an address of an interrupt program in the storage means;
Determining means for determining whether or not the address stored in the storage area of the address storage means is within a predetermined range at the time of starting the microcomputer;
A gaming machine comprising: a starting restriction unit that restricts starting of the microcomputer when the determination unit determines that the address of the interrupt program is not within a predetermined range.

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