JP6611231B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine capable of playing a game.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and multiple types of identification information are variably displayed when the game medium wins in a start prize area such as a prize opening provided in the game area. There are pachinko machines in which a predetermined number of bets are set and a slot machine in which a plurality of types of identification information (for example, symbols) are variably displayed when a start operation is performed. In a gaming machine configured to be able to execute variable display of identification information in this way, when a display result of variable display of identification information becomes a predetermined display result in the variable display unit, a predetermined game value (for example, jackpot) Some are configured to give the player a transition to a state, etc.).

  As such a gaming machine, there is known a gaming machine that defines an interruption address when an interruption of a gaming machine control program occurs in an interruption vector definition area (Patent Document 1).

JP 2002-52215 A (paragraph 0033 etc.)

  However, in the gaming machine of Patent Document 1, when an unintended interrupt address is defined in the interrupt vector definition area, normal processing is executed until an interrupt occurs, but an interrupt has occurred. Sometimes unintended processing may be performed.

  The present invention has been made paying attention to such problems, and an object thereof is to provide a gaming machine that can prevent an unintended interrupt process from being executed in advance.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 11) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, the portion shown in FIG. 12) that is executed in response to the occurrence of an interrupt.
The microcomputer is
Interrupt setting means for performing an interrupt setting process for setting a time interval at which an interrupt occurs for an interrupt that occurs at a predetermined period;
A timing means for timing the time interval at which the interrupt occurs;
Storage area setting means for setting a storage area in which a user program is stored when the microcomputer is activated (for example, setting of a program end address shown in FIG. 16);
User program execution means (for example, CPU 207) for executing processing according to the user program stored in the storage area set by the storage area setting means;
Abnormal control execution means (for example, a portion shown in FIG. 21) for executing abnormal control when the user program execution means calls a program stored in an area other than the storage area set by the storage area setting means;
Interrupt permitting means (for example, the part shown in FIG. 5 and FIG. 6) for executing a process for permitting an interrupt after executing the interrupt setting process ;
Interrupt processing execution means (for example, the portion shown in FIG. 8 and FIG. 9) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
Address storage means (for example, a portion shown in FIG. 13) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 22) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
An activation restriction unit (for example, a portion shown in FIG. 22) that restricts activation of the microcomputer when the determination unit determines that the address of the interrupt program is not within a predetermined range;
The time measuring means starts measuring time from an initial value based on the time interval at which the interrupt is generated by the interrupt setting process,
The predetermined range includes at least an address of an area where a user program is stored (for example, a portion shown in FIG. 22).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The interrupt permission means designates a time interval for an interrupt that occurs at a predetermined cycle as a setting relating to the interrupt, and executes a setting for starting a timer that measures the time interval from an initial value (for example, FIG. 27 and the portion shown in FIG. 28).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The microcomputer
Setting content storage means (for example, a portion shown in FIGS. 34 to 36) having a storage area capable of storing settings relating to interrupts;
Initial value setting means (for example, a portion shown in FIGS. 23 and 32) for setting an initial value indicating initial setting contents in at least a part of the storage area of the setting content storage means when the microcomputer is started up. .
According to this configuration, it is possible to prevent the interrupt process from being executed with unintended settings in advance.

The microcomputer
Storage area setting means for setting a storage area in which a user program is stored when the microcomputer is activated (for example, setting of a program end address shown in FIG. 16);
User program execution means (for example, CPU 207) for executing processing according to the user program stored in the storage area stored by the storage area setting means;
Abnormal control execution means (for example, a portion shown in FIG. 21) that executes abnormal control when the user program execution means calls a program stored in an area other than the storage area set by the storage area setting means. Prepared,
The predetermined range includes at least an address of an area where the user program is stored (for example, a portion shown in FIG. 22).
According to this configuration, execution of an unauthorized program can be prevented.

The microcomputer
An interrupt prohibition means at start-up that prohibits an interrupt when the microcomputer is started (for example, a portion that performs the processing of Sa1 in FIG. 5);
User program execution means (for example, CPU 207) for executing processing according to the user program;
Pre-setting interrupt prohibition means for executing a process for prohibiting an interrupt after the user program execution means starts executing a process in accordance with the user program and before the interrupt permission means executes a process for setting the interrupt. (For example, the portion that performs the processing of Sa1 before Sa16a, Sa20a, and Sa26a in FIG. 5).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The microcomputer
Data storage means (for example, the portion shown in FIGS. 12 and 14) having a storage area that is referred to when the microcomputer is started and that can store data for setting the function of the microcomputer;
Data setting means (for example, CPU 207) for setting the data in the storage area of the data storage means,
The storage area of the data storage means is an unused area (for example, a random number circuit operation mode setting (related symbol name: HRDMD) that the data setting means does not set any function based on a value set in the storage area. ) Includes bit 3 of HEDMD, and system settings (related symbol name: HSYSCNT) and HSYSCNT bits 5 to 7),
The activation restriction means restricts the activation of the microcomputer when a specific value is set in the unused area (for example, a portion shown in FIG. 22).
According to this configuration, an unintended setting can be prevented.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 11) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, the portion shown in FIG. 12) that is executed in response to the occurrence of an interrupt.
The microcomputer is
Numerical value updating means (for example, random number generation circuit 42) for updating and outputting numerical data;
Interrupt permitting means for executing processing for permitting an interrupt after executing processing for setting numerical data updating by the numerical value updating means (for example, a portion for performing the processing of Sa17, Sa21, and Sa27 in FIGS. 5 and 6) )When,
Interrupt processing execution means (for example, the portion shown in FIG. 8 and FIG. 9) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
Address storage means (for example, a portion shown in FIG. 13) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 22) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
Start limiting means (for example, a portion shown in FIG. 22) for limiting the start of the microcomputer when the determination means determines that the interrupt program address is not within a predetermined range.
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The microcomputer includes a random number circuit (for example, a random number circuit 212) that generates numerical data to be a random value,
The random number circuit includes:
Numeric update means,
Random value storage means for capturing and storing numerical data output from the numerical value updating means based on an input of a predetermined signal as a random value;
A first setting that allows new numerical data to be taken in and stored as random number values in the random value storage means when a predetermined signal is input when the random value values are stored in the random value storage means And when a predetermined signal is input when a random value is stored in the random value storage means, new numerical data cannot be stored in the random value storage means as a random value. Random value storage setting means (for example, a portion shown in [Random number operation]) is set.
According to this configuration, it is possible to prevent an unintended random value from being taken in.

The microcomputer
A random number circuit (for example, the random number circuit 212) that generates numerical data to be a random number value;
Setting content storage means (for example, a portion shown in FIG. 12) having a storage area capable of storing settings relating to the random number circuit;
Initial value setting means (for example, a part shown in FIG. 23) is provided for setting an initial value indicating initial setting contents in at least a part of the storage area of the setting content storage means when the microcomputer is activated.
According to this configuration, it is possible to prevent numerical data that becomes a random value from being set unintentionally.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 11) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, the portion shown in FIG. 12) that is executed in response to the occurrence of an interrupt.
The microcomputer is
Interrupt processing execution means (for example, the portion shown in FIG. 8 and FIG. 9) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
Fluctuating data storage means (for example, RAM 41c) for storing fluctuating data that fluctuates in accordance with execution of processing according to a program;
An initialization process execution means (for example, a part for performing the processes of FIGS. 5 and 6) for executing an initialization process for initializing at least a part of the stored contents of the variation data storage means when the initialization condition is satisfied; ,
Interrupt prohibiting means for prohibiting interrupts when executing the initialization process (for example, a part for performing the processing of Sa1 in FIG. 5);
Address storage means (for example, a portion shown in FIG. 13) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 22) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
Start limiting means (for example, a portion shown in FIG. 22) for limiting the start of the microcomputer when the determination means determines that the interrupt program address is not within a predetermined range.
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The predetermined storage area includes an unused area (for example, the portion shown in FIG. 19).
A plurality of conditions (for example, conditions for initialization 1 to 4) are set as initialization conditions,
The data control means initializes the data in the storage area including the unused area in accordance with the type of the initialization condition that is satisfied (for example, the part indicated by “About initialization”).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The microcomputer includes external data output processing means (for example, main control unit 41) for executing data output processing for outputting data to the outside.
The interrupt prohibiting means prohibits the interrupt when the external data output processing means is executing the data output process (for example, a part that executes the interrupt prohibition before Sm3 in FIG. 10).
According to this configuration, it is possible to prevent unintended data from being output.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 11) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, the portion shown in FIG. 12) that is executed in response to the occurrence of an interrupt.
The microcomputer is
Interrupt processing execution means (for example, the portion shown in FIG. 8 and FIG. 9) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
When the power supply to the gaming machine is stopped, the power supply stop processing means for executing the power supply stop processing for backing up the execution state of the processing by the microcomputer (for example, the portion shown in [Modification]) When,
A recovery means (for example, a portion shown in [Modification]) for restarting the execution of the process according to the program based on the execution state of the backed-up process;
Address storage means (for example, a portion shown in FIG. 13) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 22) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
An activation restriction unit (for example, a portion shown in FIG. 22) that restricts activation of the microcomputer when the determination unit determines that the address of the interrupt program is not within a predetermined range;
Whether or not to allow interruption based on the backed up information when backing up information indicating whether or not interruption is permitted in the power supply stop process and restarting the process by the recovery means Is set (for example, a portion shown in [Modification]).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The program is a non-maskable interrupt program that is executed in response to the occurrence of a non-maskable interrupt that cannot be prohibited based on the input of a power supply stop signal (for example, the portion related to the NMI interrupt in FIGS. 12 to 15). Including
When the non-maskable interrupt occurs, the microcomputer performs non-maskable interrupt processing execution means (for example, the NMI shown in FIGS. 12 to 15, 32, and 34) that executes processing according to the non-maskable interrupt program. The part concerning the interrupt, the part shown in [Modification]
The power supply stop process includes a process according to a non-maskable interrupt program (for example, a portion shown in [Modification]),
The storage area of the address storage means includes the address of the non-maskable interrupt program (for example, the portion shown in FIG. 13),
The determination means determines whether the address of the non-maskable interrupt program stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated (for example, as shown in [Modification] portion),
The activation restriction means restricts the activation of the microcomputer when the determination means determines that the address of the non-maskable interrupt program is not within a predetermined range (for example, a portion shown in [Modification]).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The program is a non-maskable interrupt program that is executed in response to the occurrence of a non-maskable interrupt that cannot be prohibited based on the input of a power supply stop signal (for example, the portion related to the NMI interrupt in FIGS. 12 to 15). Including
The microcomputer includes non-maskable interrupt processing execution means (for example, a portion shown in [Modification]) that executes processing according to a non-maskable interrupt program when a non-maskable interrupt occurs.
The power supply stop process includes a process according to a non-maskable interrupt program (for example, a portion shown in [Modification]),
The period from when the non-maskable interrupt generation condition is satisfied until the non-maskable interrupt is generated is shorter than the period until the interrupt generation condition is satisfied and the interrupt is generated (for example, [Modification] Part shown).
According to this configuration, it is possible to suitably execute the power supply stop process.

  In addition, this invention may have only the invention specific matter described in the claim of this invention, and has a structure other than this invention specific matter with the invention specific matter described in the claim of this invention. It may be a thing.

It is a front view of the slot machine to which the present invention is applied. It is an internal structure figure of a slot machine. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. It is a flowchart which shows the control content of the initial setting process which a main control part performs at the time of starting. It is a flowchart which shows the control content of the initial setting process which a main control part performs at the time of starting. It is a flowchart which shows the control content of the game process which a main control part performs after a setting change process. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the power interruption process (main) performed according to having detected the power interruption in the timer interruption process (main). It is a block diagram which shows the structure of a microcomputer. It is explanatory drawing which shows the address map of memory space. It is explanatory drawing which shows a vector table address map. It is explanatory drawing which shows the list of HW (hardware) parameters. It is explanatory drawing which shows a reset period / INP terminal setting. It is explanatory drawing which shows the content of a program end address. It is explanatory drawing which shows the example of a setting of a program end address. It is explanatory drawing which shows RAM access prohibition address. It is explanatory drawing which shows the example of a setting of RAM access prohibition address. It is explanatory drawing which shows SW status. It is explanatory drawing which shows the conditions which an illegal access reset generate | occur | produces. It is explanatory drawing which shows the conditions which a microcomputer does not start. It is explanatory drawing which shows the change of the operation | movement by the reset factor of a microcomputer. It is explanatory drawing which shows the list of an internal function register. It is explanatory drawing which shows the content of RAM protection register. It is explanatory drawing which shows the example of a CTC clock input. It is explanatory drawing which shows the content of the CTC control register. It is explanatory drawing which shows the content of the CTC data register. It is explanatory drawing which shows the clear method of WDT. It is explanatory drawing which shows a WDT control register. It is explanatory drawing which shows a WDT clear register. It is a block diagram of an interrupt controller. It is explanatory drawing which shows the example of an interruption process procedure. It is explanatory drawing which shows the content of the interrupt request register. It is explanatory drawing which shows the content of the interruption permission register. It is explanatory drawing which shows the content of the interrupt priority order register | resistor. It is explanatory drawing which shows the content of the external signal input / reset factor register. It is explanatory drawing which shows a periodical reset monitor register. It is explanatory drawing which shows a register structure. It is explanatory drawing which shows a program status word. It is explanatory drawing which shows the change of the value of SP (stack pointer).

[Slot machine configuration example]
As shown in FIG. 1, the slot machine 1 according to the present embodiment includes a housing 1a having an open front surface and a front door 1b pivotally supported on a side end of the housing 1a. ing.

  As shown in FIG. 2, inside the casing 1a of the slot machine 1 according to the present embodiment, reels 2L, 2C, and 2R (hereinafter referred to as a left reel, a middle reel, and a right reel) in which a plurality of types of symbols are arranged on the outer periphery. As shown in FIG. 1, three consecutive symbols among the symbols arranged on the reels 2L, 2C, and 2R are provided from a see-through window 3 provided on the front door 1b. Arranged to be visible.

  As shown in FIG. 3, the outer peripheral portions of the reels 2L, 2C, and 2R have “black 7”, “net 7 (shaded 7 in the figure)”, “white 7”, “BAR”, “replay”, A plurality of types of mutually distinguishable symbols such as “plum”, “watermelon”, “cherry”, “bell”, and “orange” are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in upper, middle, and lower three stages in the see-through window 3 provided in the approximate center of the reel panel 1c of the front door 1b.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and rotated by reel motors 32L, 32C, and 32R (see FIG. 4), so that the symbols of the reels 2L, 2C, and 2R are continuously formed in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R are reel sensors 33L, 33C, and 33R that detect a reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. , Is provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  At the position corresponding to each reel 2L, 2C, 2R on the front door 1b, a horizontally long rectangular see-through window 3 that allows the reels 2L, 2C, 2R to be seen through from the front side is provided. The reels 2L, 2C, 2R can be visually recognized from the player side.

  The front door 1b uses a medal insertion unit 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player's own game value). MAXBET switch 6 that is operated when setting the maximum bet number (3 in any game state in this embodiment) out of a prescribed number of bets determined according to the game state, stored as credits Settlement switch 10 that is operated when the medal used for setting the number of medals and the bet is set (to return the medals used for setting the credit and the number of bets), start that is operated when starting the game Stop switch 8L, 8C, 8R operated when stopping the rotation of the switch 7, the reels 2L, 2C, 2R, and the effect switch for use in the effect. 56 are respectively provided so as to be operated by the player.

  In this embodiment, among the three reels 2L, 2C, and 2R that have started to rotate, the reel that stops first is referred to as a first stop reel, the stop is the first stop, and the stop operation is the first stop reel. This is referred to as one stop operation (or first stop). Similarly, the reel that stops second is referred to as a second stop reel, the stop is referred to as a second stop, and the stop operation is referred to as a second stop operation (or second stop). The reel that stops third is referred to as a third stop reel, the stop is referred to as a third stop or final stop, and the stop operation is referred to as a third stop operation (or third stop).

  The front door 1b also displays a credit indicator 11 that displays the number of medals stored as credits, the number of medals paid out due to the occurrence of a prize, an error code indicating the contents when an error occurs, and the like. Game assist indicator 12, 1BETLED14 that notifies that the bet number is set by 1 by lighting, 2BETLED15 that notifies that the bet number is set by 2 and 2 that the bet number is set by 3 3BET LED 16 to notify, insertion request LED 17 to notify that a medal can be inserted by lighting, start effective LED 18 to notify that the game start operation by the operation of the start switch 7 is effective, wait (the previous game start) Waiting for the start of reel rotation because a certain period has not elapsed since Weight in LED19 for notifying by lighting a a is that during the game display section 13 in the replay LED20 is provided for informing is provided by lighting the effect that during replay game, which will be described later.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying that the setting operation of the bet amount by the operation of the MAXBET switch 6 is valid, and stop switches 8L, 8C, The left, middle, and right stop valid LEDs 22L, 22C, and 22R (see FIG. 4) are provided inside the 8R to notify that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is valid by lighting. It has been.

  Further, below the stop switches 8L, 8C, and 8R on the front door 1b, a lower panel 1d on which a title of the slot machine 1 and a payout table 1 to be described later are printed is provided.

  Inside the front door 1b, there is a reset switch 23 for detecting a reset operation for releasing an error state described later and a stop state described later by a predetermined key operation, while changing a set value and confirming a set value described later. The set value display 24 that displays the set value at that time, and the validity / invalidity of the stop function for controlling the stop state at the end of the BB, which will be described later (a state in which the progress of the game is restricted until a reset operation is performed) A check switch 36a for selecting the automatic settlement function that controls automatic settlement at the end of BB, which will be described later (processing to settle (return) medals stored as credits regardless of the player's operation). An automatic settlement switch 36b for selecting invalidity and a flow path of medals inserted from the medal insertion unit 4 are provided in a hopper tank 34a (see FIG. 2) described later provided in the housing 1a. ) Side or the medal payout exit 9 side, a flow path switching solenoid 30 for selectively switching, and a inserted medal sensor 31 for detecting a medal inserted from the medal insertion unit 4 and flowing down to the hopper tank 34a side. A medal selector (not shown) and a door open detection switch 25 (see FIG. 4) for detecting the open state of the front door 1b are provided.

  As shown in FIG. 2, a reel sensor 33L capable of detecting the reel reference positions of the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R, and the reels 2L, 2C, and 2R described above is provided inside the housing 1a. , 33C, 33R (see FIG. 4), an external output board 1000 for outputting an external output signal, a hopper tank 34a for storing medals inserted from the medal insertion section 4, and a hopper tank 34a. A hopper unit 34 including a hopper motor 34b for paying out medals from the medal payout opening 9, a payout sensor 34c for detecting medals paid out by driving the hopper motor 34b, and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, a full sensor 35 a made up of a pair of electrically conductive members spaced apart from each other and provided at a height capable of detecting a predetermined amount of stored medals is provided. It is possible to detect that the medal storage amount stored in the inside when it is conductive by contacting through the medal stored in the inside exceeds a predetermined amount, that is, that the overflow tank is full. It has become.

  The front side of the power supply box 100 functions as a setting key switch 37 for switching to a setting change state or a setting confirmation state, and functions as a reset switch for canceling an error state or a stop state in a normal state. There are provided a reset / setting switch 38 that functions as a setting switch for changing a setting value of a winning probability (outtake rate) of internal lottery to be described later, and a power switch 39 that is operated when the power is turned on / off. .

  When a game is played in the slot machine 1 of the present embodiment, first, a medal is inserted from the medal insertion unit 4 or a bet number is set using a credit. To use the credit, the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the winning line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the state where the game can be started. Become. In the present embodiment, the winning line LN becomes valid when three cards are determined as the specified number of bets regardless of the gaming state and the specified number of bets are set. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In the present embodiment, as shown in FIG. 1, only the winning line LN set across the symbols arranged in the horizontal direction in the middle stage of the reel 2L, the middle stage of the reel 2C, the middle stage of the reel 2R, that is, the middle stage, is the winning line. It is defined as. In the present embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

  In the present embodiment, invalid lines LM1 to LM1-4 are set separately from the winning line LN in order to make it easier to recognize that the winning line LN has a combination of symbols constituting the winning line. The invalid lines LM1 to LM4 are not determined based on the combination of symbols aligned with the invalid lines LM1 to LM4. When the combination of symbols constituting a specific prize is arranged on the winning line LN, When a combination of symbols (for example, bell-bell-bell) is awarded when the winning line LN is aligned with any of the LM1 to LM4, the symbols constituting the particular winning line LN It is easy to recognize that the combination is complete. In the present embodiment, as shown in FIG. 1, the invalid lines LM1 and 2L of the reel 2L, the upper stage of the reel 2C, the upper stage of the reel 2R, that is, the invalid line LM1 and the reel 2L set across the symbols arranged in the horizontal direction on the upper stage. The lower stage, the lower stage of the reel 2C, the lower stage of the reel 2R, that is, the invalid line LM2 set across the symbols arranged horizontally in the lower stage, the upper stage of the reel 2L, the middle stage of the reel 2C, the lower stage of the reel 2R, that is, lower right There are four types of invalid lines LM3 set across straddling symbols: invalid line LM3, lower stage of reel 2L, middle stage of reel 2C, upper stage of reel 2R, that is, invalid line LM4 set across straddling symbols. It is defined as LM.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  Then, when all the reels 2L, 2C and 2R are stopped, one game is finished, and a combination of symbols (hereinafter also referred to as a combination) predetermined on the winning line LN is a display result of each reel 2L, 2C and 2R. In the case of a stop, a winning occurs, and a predetermined number of medals are awarded to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in the present embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, when the combination of symbols accompanying the transition of the gaming state is stopped as a display result of each reel 2L, 2C, 2R on the winning line LN, the gaming state is shifted according to the combination of symbols.

  In the present embodiment, the game starts when the operation of the start switch 7 is detected in a state where the operation of the start switch 7 is valid, and the game ends when all the reels are stopped. Further, one unit of control (game control) for executing a game starts when all the controls associated with the end of the previous game are completed, and when all the controls associated with the end of the game are completed. finish.

  Further, in the slot machine 1 according to the present embodiment, after the game is started and the reels 2L, 2C, and 2R are rotated to start changing the symbols, any of the stop switches 8L, 8C, and 8R is When operated, the reels corresponding to the stop switches 8L, 8C, and 8R stop rotating and the symbols are stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

  The reels 2L, 2C and 2R rotate 80 times per minute, and 80 × 21 (the number of symbols per reel) = 1680 frames, so the maximum of 4 symbols is drawn in 190 ms. Will be able to. In other words, the symbols that can be selected as the stop symbols are the symbols that are displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols that are four frames ahead of them, for a total of five symbols.

  For this reason, for example, when any one of the stop switches 8L, 8C, 8R is operated and the symbol displayed on the lower stage of the reel corresponding to the stop switch is used as a reference, the symbol from the symbol to four frames ahead is used. Since the symbols can be displayed in the lower row, in each of the reels 2L, 2C, 2R, when any one of the stop switches 8L, 8R is operated, the symbol displayed in the middle row of the reel corresponding to the stop switch. Can be displayed on the winning line LN.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and a DC voltage necessary for driving the electrical components constituting the slot machine 1 is generated from the AC100V power supply. The game control board 40 and the game control board 40 It is supplied to the production control board 90 connected through the. In addition, a command transmission line from the main control unit 41 to the sub control unit 91, which will be described later, and a power supply line for supplying power from the game control board 40 to the effect control board 90 are connected via a single cable and connector. Are connected to each other, and all the connectors that connect these cables and the respective boards are connected to each other so that the respective parts on the side of the effect control board 90 can operate and receive commands from the main control part 41. Become. For this reason, unless the command transmission line for transmitting a command from the main control unit 41 is connected to the effect control board 90, power is not supplied to the effect control board 90, and only the effect control board 90 side operates. There is no end to it.

  Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

  On the game control board 40, the above-described MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, stop switch 36a, automatic settlement switch 36b, insertion medal sensor 31, door open The detection switch 25 and reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, setting key switch 37, and reset / setting switch 38 are connected via the power supply board 101. Detection signals from these connected switches are input.

  Further, the game control board 40 includes the credit display 11, the game auxiliary display 12, the payout display 13, 1 to 3 BET LEDs 14 to 16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, and the BET. The switch effective LED 21, left, middle, and right stop effective LEDs 22L, 22C, and 22R, the set value display 24, the flow path switching solenoid 30, and the reel motors 32L, 32C, and 32R are connected to each other, and are described above via the power supply board 101. The hopper motor 34b is connected, and these electric components are driven based on control of a main control unit 41 (described later) mounted on the game control board 40.

  The game control board 40 includes a main control unit 41, a random number generation circuit 42, a sampling circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, a power interruption detection circuit 48, and a reset circuit 49. Is installed.

  The main control unit 41 is constituted by a one-chip microcomputer, and includes a main CPU 41a, a ROM 41b, a RAM 41c, an I / O port 41d, and a random number generation circuit. The main control unit 41 executes a program stored in the ROM 41b to perform processing related to the progress of the game, and directly or indirectly controls each unit of the control circuit mounted on the game control board 40.

  The random number generation circuit 42 is configured by a counter that counts up and updates the value every time a predetermined number of pulses are generated, and the sampling circuit 43 acquires the numerical value counted by the random number generation circuit 42. The random number generation circuit 42 defines a range of numerical values to be counted for each type of random number, and in the present embodiment, 0 to 65535 is defined as the range. The main CPU 41a sends an instruction to the sampling circuit 43 according to the processing to acquire the numerical value indicated by the random number generation circuit 42 as a random value (hereinafter, this function is referred to as a hardware random number function). Random numbers for internal lottery, which will be described later, are processed by software instead of using the random numbers extracted by the hardware random number function as they are. The main CPU 41a also has a function of updating the value of a specific register by the above-described timer interrupt process (main) and acquiring the updated numerical value as a random number (this function is hereinafter referred to as a software random number function). .

  The switch detection circuit 44 takes in detection signals input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits them to the main control unit 41. The motor drive circuit 45 transmits the motor drive signal output from the main control unit 41 to the reel motors 32L, 32C, and 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40. The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1 and outputs a voltage drop signal indicating that to the main control unit 41 when a voltage drop is detected. The reset circuit 49 provides a system reset signal to the main control unit 41 in a state where the power is unstable, such as when the power is turned on or when the power is turned off.

  The CPU 41a of the main control unit 41 executes processing for controlling the progress of the game in the slot machine 1 by executing the program read from the ROM.

  As described above, in the main control unit 41, the CPU 41a executes control according to the program stored in the ROM 41b, so that the main control unit 41 (or CPU 41a) executes (or performs processing) hereinafter. Specifically, the CPU 41a executes control according to a program. The same applies to microcomputers mounted on boards other than the game control board 40.

  The RAM 41c included in the main control unit 41 provides a work area for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power source. That is, even if the power supply to the slot machine is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period. In the present embodiment, all areas of the RAM 41c are backup RAMs, and all the contents of the RAM 41c are stored for a predetermined period even when the power supply to the slot machine is stopped.

  The ROM 41b included in the main control unit 41 stores various selection data and table data used for controlling the progress of the game. For example, the ROM 41b stores data constituting a plurality of determination tables, determination tables, setting tables and the like prepared for the CPU 41a to perform various determinations, determinations, and settings. The ROM 41b stores table data constituting a plurality of command tables used for the CPU 41a to transmit control signals serving as various control commands from the game control board 40.

  The RAM 41c included in the main control unit 41 is provided with a game control data holding area as an area for holding various data used for controlling the progress of the game in the slot machine 1 and the like. For example, a DRAM is used as the RAM 41c, and a refresh operation is required to maintain the stored data contents. The CPU 41a has a built-in refresh register for performing this refresh operation. For example, the refresh register consists of 8 bits, and the lower 7 bits are automatically incremented every time the CPU 41a fetches an instruction from the ROM 41b. Accordingly, the stored value in the refresh register is updated every execution time of one instruction in the CPU 41a.

  The main control unit 41 transmits various commands to the sub control unit 91. A command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and no command is sent from the sub control unit 91 toward the main control unit 41.

  The main control unit 41 receives the detection state of various switches connected to the game control board 40 from the input port. Then, the main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from these input ports.

  Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In the present embodiment, a timer interrupt process (main) described later is executed at regular time intervals (about 0.56 ms in the present embodiment).

  The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process ends, a new interrupt occurs at that point. It will be.

  An effect switch 56 is connected to the effect control board 90, and a detection signal of the effect switch 56 is input.

  The effect control board 90 is connected to effect devices such as a liquid crystal display 51 (see FIG. 1), an effect LED 52, speakers 53 and 54, and the reel LED 55 described above, which are arranged on the front door 1b of the slot machine 1. These effect devices are driven based on control by a later-described sub-control unit 91 mounted on the effect control board 90.

  In the present embodiment, the sub-control unit 91 mounted on the effect control board 90 performs output control of effect devices such as the liquid crystal display 51, effect effect LEDs 52, speakers 53 and 54, and reel LEDs 55. However, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board separately from the sub control part 91, and the sub control part 91 is based on a command from the main control part 41. The output pattern of the effect device may be determined and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output The output control of the effect device is performed by both of the control units.

  Moreover, in this Embodiment, although the liquid crystal display 51, the effect effect LED52, the speakers 53 and 54, and the reel LED55 are illustrated as an effect device, an effect device is not restricted to these, For example, it drives mechanically. A display device or a mechanically driven item may be applied as the rendering device.

  Similar to the main control unit 41, the effect control board 90 includes a sub CPU 91a, ROM 91b, RAM 91c, and a microcomputer provided with an I / O port 91d. The sub control unit 91 controls the effect, and the effect control board 90. A display control circuit 92 that performs display control of the liquid crystal display 51 connected to the LED, an LED driving circuit 93 that performs drive control of the effect LED 52 and the reel LED 55, an audio output circuit 94 that controls audio output from the speakers 53 and 54, When the power is turned on or when an initialization command from the sub CPU 91a is not input for a certain period of time, a reset circuit 95 that gives a reset signal to the sub CPU 91a and a detection signal input from the effect switch 56 connected to the effect control board 90 are detected. Switch detection circuit 96 outputs time information including date information and time information The clock device 97, the power supply voltage supplied to the slot machine 1 is monitored, and when a voltage drop is detected, a power drop detection circuit 98 that outputs a voltage drop signal to that effect to the sub CPU 91a, and other circuits Etc., and the sub CPU 91a receives various commands sent from the game control board 40 to perform various controls for producing effects, and controls each part of the control circuit mounted on the effect control board 90. Control directly or indirectly.

  The reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that gives the system reset signal to the main control unit 41 in the game control board 40. When the power is turned on, the sub control unit 91 It starts at an earlier stage than the unit 41. On the other hand, the power interruption detection circuit 98 has a voltage that outputs a voltage drop signal lower than the power interruption detection circuit 48 that outputs a voltage drop signal to the main control unit 41 in the game control board 40. The sub control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the number of input system clocks reaches a certain number, that is, every certain interval.

  Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time.

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and the data stored in the RAM 91c is held while the backup power is supplied. That is, even if the power supply to the slot machine is stopped, at least a part of the contents of the RAM 91c is stored for a predetermined period. In the present embodiment, all areas of the RAM 91c are backup RAMs, and all the contents of the RAM 91c are stored for a predetermined period even when the power supply to the slot machine is stopped. In the present embodiment, all areas of the RAM 91c are backup RAMs, and all the contents of the RAM 91c are stored for a predetermined period even when the power supply to the slot machine is stopped.

[Settings]
In the slot machine 1 of the present embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to a set value in an internal lottery described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 41c is displayed as a display value on the setting value display 24, and the setting value can be changed by operating the reset / setting switch 38. Transition to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated one by one (when further operation is performed from the setting 6, the display returns to the setting 1). . When the start switch 7 is operated, the display value is determined as the set value. When the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 41c of the main control unit 41, and the state shifts to a state in which the game can proceed.

  In order to check the set value, after the game is over, the setting key switch 37 may be turned on in a state where the bet amount is not set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 41c is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by setting the setting key switch 37 to the off state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not a voltage drop signal from the power interruption detection circuit 48 is detected every time the timer interrupt process (main) is executed. When a power failure determination process is performed and it is determined that a voltage drop signal is detected in the power failure determination process, a power interruption process (main) is executed. In the power interruption process (main), the RAM 41c stores destructive diagnosis data (5AH in the present embodiment) in which any bit is 1, that is, specific data other than 0 is stored, and all areas of the RAM 41c are stored. The RAM parity adjustment data is calculated so that the RAM parity based on the stored data becomes 0, and stored in the RAM 41c. Note that the RAM parity is a value calculated as an exclusive OR of values stored in each bit of the corresponding area (all areas in the present embodiment) of the RAM 41c. Therefore, if the RAM parity based on the data stored in all areas of the RAM 41c is 0, the RAM parity adjustment data is 0, and the RAM parity based on the data stored in all areas of the RAM 41c is 1. In this case, the RAM parity adjustment data is 1.

  The main control unit 41 calculates the RAM parity based on the data stored in all areas of the RAM 41c at the time of activation regardless of whether the system reset or the user reset, and the value of the data for destructive diagnosis And the processing state of the main control unit 41 is restored to the state before the power interruption based on the data stored in the RAM 41c on the condition that the RAM parity is 0 and the value of the data for destructive diagnosis is also correct. However, if the RAM parity is not 0 (in the case of 1) or the value of the destruction diagnosis data is not correct, it is determined that the RAM is abnormal, and the RAM abnormal error code is set in the register to control the RAM abnormal error state. However, the progress of the game is disabled. Unlike the normal error state, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the setting change state described above. It will not be released until

  In the present embodiment, all data stored in the RAM 41c is retained by the backup power source even during a power failure, and the main control unit 41 determines that the data in the RAM 41c is normal when the power is turned on. In this case, the control state is restored to the control state before the power interruption based on the data stored in the RAM 41c, but only the data necessary for the return of the control state in the event of a power failure is backed up among the data stored in the RAM 41c. It may be configured to return to the control state before power interruption based on the data backed up at the time of input.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player For example, it is not necessary to restore the state of all input ports to the state before power interruption.

[About initialization]
Next, initialization of the RAM 41c of the main control unit 41 will be described. The storage area of the RAM 41c of the main control unit 41 is divided into an important work, a non-saved work, a general work, a special work, an unused area, and a stack area.

  Important work items include various indicators, LED display data, I / O input / output data, game time counters, and other data that can be inconvenient to initialize, as well as the RT flag and RT remaining game count described below. Work to be done. The unsaved work is a work that holds the state of various switches, and a value is always set regardless of whether or not the data in the RAM 41c is destroyed at the time of activation. The general work is a work that stores data that can be initialized at the end of the BB, such as a stop control table, a stop symbol, the number of medals paid out, the total number of medals paid out in the BB, and a game state flag described later. The special work is a work that stores data such as various software random numbers that are initialized only before the setting is started. The unused area is an unused area in the storage area of the RAM 41c, and is initialized if any one of a plurality of initialization conditions described later is satisfied. The stack area is an area in which data saved from the register of the main control unit 41 is stored, and the unused stack area is one of a plurality of initialization conditions to be described later, like the unused area. However, if it is established, it will be initialized, but the in-use stack area is not initialized because the program continues.

  In the present embodiment, the main control unit 41 stores the data in the RAM 41c at startup when the setting key switch 37 is on, when a RAM error occurs, at the end of the BB, and at startup when the setting key switch 37 is off. When is not destroyed, when the five initialization conditions at the end of one game are satisfied, four types of initializations that are initialized in accordance with each initialization condition are performed.

  Initialization 1 is an initialization performed when the setting key switch 37 is turned on at the time of startup and transitions to a setting change state, or initialization performed when a RAM abnormality error occurs. In the storage area of the RAM 41c, all areas (including the unused area and the unused stack area) except the important work and the used stack area, that is, the area from the unsaved work to the unused stack area are initialized. The Initialization 2 is an initialization performed at the end of the BB. In the initialization 2, there are general work, unused area, and unused stack area in the storage area of the RAM 41c, that is, areas from the general work to the unused stack area. It is initialized. Initialization 3 is initialization that is performed when the setting key switch 37 is off at the time of startup and the data in the RAM 41c is not destroyed. In initialization 3, non-saved work, unused areas, and The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area are initialized in the storage area of the RAM 41c.

  In the present embodiment, interrupts are prohibited before initialization 1 and initialization 3 in the initial setting process (see FIGS. 5 and 6) described later. However, when initialization 2 is performed, BB is prohibited. Initialization 2 is performed after prohibiting interrupts at the end, and initialization 1 is performed after prohibiting interrupts at the end of one game. In this embodiment, the initialization 1 is performed before the setting change state is transferred. However, the initialization 1 is performed at the end of the setting change state, or both before the setting change state and at the end of the setting change state. May be.

  As described above, in this embodiment, when a RAM abnormality error occurs at the time of power-on or the like, initialization 1 is executed, and the control state before that is initialized. The RT flag and the RT remaining game number assigned to the work are held without being initialized. On the other hand, the gaming state flag assigned to the general work is initialized as initialization 1 is executed.

[About internal lottery]
In the slot machine 1 of the present embodiment, as described above, the prescribed number of bets that can be set is determined according to the gaming state (usually inside, BB (RB)), and is determined according to the gaming state. The game can be started on condition that the specified number of bets is set. In the present embodiment, the winning line LN is activated when a prescribed number of bets corresponding to the gaming state is set.

  In the slot machine 1 of the present embodiment, when all the reels 2L, 2C, and 2R are stopped, the winning line LN that is activated (hereinafter, the activated winning line LN is simply referred to as the winning line LN). A winning combination will be awarded when a combination of symbols called “comb” is complete. The combination may be a combination of the same symbols or a combination including different symbols. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination (hereinafter also referred to as “replay”) and a special combination (hereinafter also referred to as “bonus”) accompanied by a transition to a game state advantageous to the player. Below, a small role and a re-playing role are collectively called a general role. In order to win each winning combination determined according to the gaming state, it is necessary to win an internal lottery to be described later and set a winning flag for the winning combination in the RAM.

  Of the winning flags for each of these roles, the winning flags for the small role and the replaying role are valid only in the game in which the flag is set, and are invalid in the next game. It is valid until a combination of combinations permitted by the flag is completed, and is invalid in a game having a combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combination permitted by the flag cannot be made, the winning flag is not invalidated and carried over to the next game. It becomes.

  In the internal lottery, it is determined whether or not the above winning combination is permitted before the display results of all the reels 2L, 2C, and 2R are derived and displayed (actually, when the start switch 7 is detected). To do. In the internal lottery, first, a random value for internal lottery (an integer from 0 to 65535) is acquired when the start switch 7 is detected. Specifically, the value of the random number value storage work assigned to the RAM 41c is set to the lottery work assigned to the RAM 41c. Then, for each combination determined according to the gaming state and whether or not the special combination is carried over, the numerical data stored in the lottery work, the value of the gaming state flag for specifying the gaming state, and the RT described later are specified. The determination is made according to the number of determination values for each combination determined according to the value of the RT flag, the number of bets, and the set value. Note that the special role carryover means that if the special role is not won in the internal lottery game and the special role is not won, the special role will be carried over from the next game until the special role is won. It is to maintain the winning state.

  In the internal lottery, an internal lottery target, the current gaming state flag value, the RT flag value, and the number of determination values determined corresponding to the set value are stored in a random number for internal lottery (a lottery work). When the result of addition overflows, it is determined that the winning combination is won. For this reason, a winning combination will be won with a probability (number of determination values / 65536) according to the number of determination values.

  If a winning combination of any combination is determined, a winning flag corresponding to the combination determined to be winning is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination or winning combination is won, only the general winning combination work is cleared.

[Reel stop control]
Next, stop control of the reels 2L, 2C, and 2R executed in the reel rotation process in Sd3 of FIG. 7 will be described.

  The main control unit 41 refers to the table index and the table creation data stored in the ROM 41b when the reel starts rotating and when the reel stops and the reel that is still rotating still remains. A stop control table is created for each reel that is rotating. When any of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the referred stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the table index, an index that indicates the start address of the area in which the data for table creation is stored, from the reference address when referring to the table index, according to the setting state of the winning flag by internal lottery (hereinafter referred to as the internal winning state) Differences up to the address where the data is stored are registered. As a result, a difference corresponding to the internal winning state is acquired, and the corresponding index data can be acquired by adding the difference to the reference address. Even if the winning status of the combination is different, when the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes a stop control table indicating the number of sliding frames according to the stop operation position, and an address of the stop control table to be referred to according to the reel stop status.

  The stop control table referred to according to the reel stop status is whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, only the right reel is stopped, It may vary depending on whether the middle reel is stopped, the left and right reels are stopped, the middle and right reels are stopped, and if any reel is stopped, stop Since there may be differences depending on the stop position of the reels already completed, the address of the stop control table to be referenced for each situation is registered for each rotating reel, and based on the top address of the table creation data, It is possible to specify the address of the stop control table that should be referred to according to the status of each, and it is necessary according to each status from this specified address. And to be able to identify the stop control table. Even when the stop status of the reels and the stop position of the stopped reels are different, when the same stop control table is applied, the same address may be registered as the address of the stop control table. In such a case, the same stop control table is referred to.

  The stop control table is data that can specify the number of sliding frames for each timing when the stop operation is performed. In the present embodiment, stepping motors that make one turn at a cycle of 168 steps (0 to 167) are used for the reel motors 32L, 32C, and 32R. That is, when the reel motors 32L, 32C, and 32R are driven for 168 steps, the reels 2L, 2C, and 2R make one round. Then, 21 areas (frames) divided every 16 steps (the number of steps that one symbol moves) are defined for one reel, and these areas are areas 0 to 20 from the reel reference position. A number is assigned. On the other hand, the number of symbols arranged on one reel is 21, and symbol numbers 0 to 20 from the reel reference position are assigned to symbols on each reel, so symbols 0 to 20 are assigned to each reel. , Area numbers 0 to 20 are assigned in order. In the stop control table, the number of sliding symbols for each area number is compressed and stored according to a predetermined rule, and the number of sliding symbols for each area number can be acquired by expanding the stop control table. Yes.

  As described above, the stop control table created by referring to the table index and the table creation data corresponds to the area number, and the area corresponding to each area number has a stop reference position (in this embodiment, a perspective window). 3 when the operation of the stop switches 8L, 8C, 8R is detected at the timing (the timing in which the number of steps from the reel reference position is included in the range of the number of steps). This is a table in which the number of frames is set.

  Next, the procedure for creating the stop control table will be described. First, at the start of reel rotation, the top address of the table creation data corresponding to the internal winning state of the game is acquired. Specifically, the table index is first referred to, index data corresponding to the internal winning state is obtained, table creation data is identified based on the obtained index data, and all reels are identified from the identified table creation data. The address of the stop control table for each reel corresponding to the state of rotation is acquired, and the stop control table for each reel stored at the acquired address is expanded to generate a stop control table for all reels.

  Further, when any one reel stops or any two reels stop, the index data acquired at the start of reel rotation, that is, the top address of the table creation data corresponding to the internal winning state of the game The table creation data is identified based on the obtained table creation data, and the address of the stop control table for the unreacted reel corresponding to the stop reel and the area number of the stop position of the reel is obtained from the identified table creation data. The stop control table for each stored reel is expanded to create a stop control table for the unstopped reels.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel, the control when the display result is derived to the corresponding reel is described. To explain, when any operation corresponding to the rotating reel is detected effectively among the stop switches 8L, 8C, 8R, the stop operation position is based on the number of steps from the reel reference position when the stop operation is detected. The number of sliding symbols corresponding to the area number of the specified stop operation position is acquired by referring to the stop control table of the reel where the stop operation is detected. Then, control is performed to rotate and stop the reel by the number of acquired sliding frames. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the acquired number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. Thus, the region corresponding to the region number that is the stop position ahead of the number of sliding frames from the region corresponding to the region number of the stop operation position where the stop operation is detected is the stop reference position (in this embodiment, the fluoroscopic window 3 The lower symbol area).

  In the table index of the present embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state, and one table creation data includes one reel. Only one address is stored as the address of the storage area of the stop control table corresponding to the stop status (and the stop position of the stopped reel). That is, the table creation data corresponding to one internal winning state in one gaming state and the stop control table corresponding to the reel stop status (and the stop position of the stopped reel) are uniquely determined. The stop control table created with reference to is unique for one internal winning state in one gaming state and the reel stop status (and the stop position of the stopped reel). Therefore, when all of the gaming state, the internal winning state, and the reel stop status (and the stop position of the stopped reel) are the same, the reel is based on the same stop control table, that is, the same control pattern. The stop control is performed.

  Further, in the present embodiment, a value of 0 to 4 is determined as the number of sliding frames, and it is possible to stop the reel by drawing a maximum of 4 frames after detecting a stop operation. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In the present embodiment, when any of the winning combinations is won, the winning combination is drawn into the winning line LN to the maximum in the range of 4 frames, and the winning combination is drawn so that it does not align with the winning line LN. Create a stop control table with the number of sliding symbols and perform reel stop control. On the other hand, if you do not win any of the roles, stop control with the number of sliding symbols that does not match any of the roles Create a table and perform reel stop control. As a result, when a stop operation is performed, if the winning combination can be stopped in the winning line LN within the drawing range of a maximum of 4 frames, the control is performed so that the winning combination is stopped. The combination that has not been performed will be controlled to be stopped in a drawing range of a maximum of 4 frames.

  If a special role and a small role are elected at the same time, such as when a special role is elected while the special role has been carried over from before the previous game, the elected small role will be placed in the winning line LN within 4 frames. The number of sliding symbols is set so as to be pulled in as much as possible, and for the stop operation position where the selected small role cannot be drawn into the winning line LN within the range of up to 4 frames, the winning special role is set to 4 in the winning line LN. A stop control table in which the number of sliding frames is determined so as to be pulled in as much as possible within the range of frames is created, and reel stop control is performed. As a result, when a stop operation is performed, if it is possible to stop all the small roles that have been selected in the winning line LN within a drawing range of a maximum of 4 frames, the control is performed so that the winning combination is stopped. If it is not possible to withdraw a small role that has been won in the draw range of up to 4 frames to the line LN, if the special role that has been won in the draw range of up to 4 frames can be aligned and stopped on the winning line LN, A control is performed to stop them in a uniform manner, and a winning combination that has not been won will be controlled to be stopped within a 4-frame pull-in range. That is, in such a case, priority is given to the control for aligning the small role with the winning line LN over the special role, and the special role can be won only when the small role cannot be drawn. When a special combination and a small combination can be drawn at the same time, only the small combination is drawn and the small combination is not aligned with the winning line LN at the same time as the special combination.

  In this embodiment, when a special role is elected while the special role has been carried over from before the previous game, or when a special role and a small role are won simultaneously, the special role and the small role are won simultaneously. If the winning combination is prioritized over the winning special role, the special role is controlled to align with the winning line LN only when the winning combination cannot be drawn. When the two are simultaneously elected, the control for aligning the special role with the winning line LN has priority over the small role, and the control for aligning the small role with the winning line LN may be performed only when the special role cannot be drawn. .

  When a special role and replay are won at the same time, such as when a re-playing role is won in a state where the special role has been carried over from before the previous game, when the stop operation is performed, the maximum is shown in the winning line LN. Control is performed so that the symbols of the re-gamer are aligned and stopped within the 4-frame pull-in range. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer elected at the same time are arranged within 5 symbols for each of the reels 2L, 2C and 2R, that is, at intervals of 4 frames or less. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games with the winning line LN has priority over the special game, and the re-games will always win. In the case where the special combination and the re-playing combination can be withdrawn at the same time, only the re-playing combination is drawn in and the special combination is not aligned with the winning line LN simultaneously with the re-playing combination.

  In the present embodiment, the main control unit 41 rotates the reels for which the stop operation has not yet been detected until the operation of the stop switches 8L, 8C, 8R is detected after the rotation of the reels 2L, 2C, 2R is started. And the control for stopping the display result on the corresponding reel is performed on condition that the operation of the stop switches 8L, 8C, 8R is detected. Even if the reel rotation temporarily stops due to the occurrence of a reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is restarted. Control is performed to stop the display result of the corresponding reels on the condition that the rotation of the reels that have not been continued is continued and the operation of the stop switches 8L, 8C, and 8R is detected.

  In the present embodiment, the control for stopping the display result on the corresponding reel is performed on the condition that the operation of the stop switches 8L, 8C, and 8R is detected, but the rotation of the reel is started. Then, when a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is assumed that the stop operation has been performed, and automatic stop control is performed to automatically stop each reel. Anyway. In this case, since the reels are stopped without the player's operation, it is preferable to derive a display result that does not constitute any combination even if any combination is won.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described.

[Initial setting processing]
When the system reset signal is input from the reset circuit 49, the main control unit 41 generates a system reset, and the microcomputer performs various settings at the time of startup such as function settings referring to HW parameters described later. Thereafter, the initial setting process shown in the flowcharts of FIGS. 5 and 6 is performed according to the program stored in the ROM 41b as the user program.

  As shown in FIGS. 5 and 6, the main control unit 41 first performs a timer interrupt process (main) executed by the main control unit 41 described in FIGS. 8 and 9 at regular intervals (interval of 0.56 ms). Is interrupted (Sa1). Next, the built-in device, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sa2).

  Next, access to the RAM 41c is permitted (Sa4), and RAM parities of all storage areas (including unused areas and unused stack areas) of the RAM 41c are calculated (Sa5).

  In step Sa6, it is determined whether or not the RAM parity calculated in step Sa5 is zero. If the power interruption interrupt processing (main) is normally performed, the RAM parity should be 0. If the RAM parity is not 0 in the step of Sa6, the data stored in the RAM 41c is not normal. In this case, after executing the initialization 1 for initializing all the storage areas except the used stack area and the important work among the storage areas of the RAM 41c (Sa22), whether or not the setting key switch 37 is turned on. If the setting key switch 37 is on, a setting change start command indicating that the setting is being changed is generated (Sa19), and the generated setting change start command is stored in the command buffer (Sa20). ).

  Then, the main control unit 41 sets a register of a timer circuit built in the main control unit 41 so that a timer interrupt is periodically generated every predetermined time (Sa20a). For example, a value corresponding to 0.56 ms is set in a predetermined register (time constant register). In this embodiment, it is assumed that a timer interrupt is periodically taken every 0.56 ms. In the timer circuit, the timer is initialized by setting the register, and time measurement is started from the initial value.

  Next, the main control unit 41 sets the random number generation circuit 42 (Sa20b). In the setting of the random number circuit, the main control unit 41 writes the random number maximum value setting data for specifying the random number maximum value preset by the user in the built-in register. In addition, the main control unit 41 checks whether the maximum random number set in the built-in register is not less than a predetermined lower limit value. If the random number maximum value is less than the lower limit value, the main control unit 41 is set in the random number maximum value setting register. Execute random number maximum value reset processing to reset the random number maximum value. Further, the main control unit 41 executes an initial value changing process for changing the initial value of the count value updated by the counter of the random number generation circuit 42. Further, the main control unit 41 writes the random number update method selection data in the random number update method selection register. Further, the main control unit 41 writes period setting data (data for setting how many times the reference clock signal is to be divided) for designating the period of the random number generating clock signal preset by the user. The main control unit 41 sets whether or not to update the initial value input to the counter when the count value is updated to a predetermined final value by the counter of the random number generation circuit 42. Further, the CPU 56 sets whether or not to change the permutation of the count values updated by the counter when the count value is updated to a predetermined final value by the counter of the random number generation circuit 42. Then, the main control unit 41 writes random circuit activation data. By doing so, the game control microcomputer 560 activates the random number generation circuit 42.

  Next, the main control unit 41 permits the interruption of the timer interrupt process (main) executed by the main control unit 41 described in FIG. 8 and FIG. 9 at regular intervals (interval of 0.56 ms) (Sa21). Then, the setting change processing for changing the winning probability of the winning combination, that is, the setting changing state is entered. Then, when the setting change process ends, the process proceeds to the game process shown in FIG.

  If the setting key switch 37 is off in step Sa23, an error code indicating a RAM abnormality is set in the register (Sa24), an error start command indicating a RAM abnormality is generated (Sa25), and the generated error start command is used as a command. The data is stored in the buffer (Sa26). Then, the timer interrupt is set in the same manner as Sa20a (Sa26a), the random number generation circuit 42 is set in the same manner as Sa20b (Sa26b), and the main control unit 41 described in FIG. 8 and FIG. The interrupt of the timer interrupt process (main) executed at an interval of 0.56 ms is permitted (Sa27), and the process proceeds to an error process, that is, a RAM abnormal error state. Then, for example, when the RAM abnormality error state is canceled by operating the reset / setting switch 38 by a game store clerk, the game processing shown in FIG. 7 is started.

  If the RAM parity is 0 in step Sa6, it is further determined whether or not the destructive diagnosis data is normal (Sa7). If the power interruption process (main) is performed normally, the data for destruction diagnosis should be set, and if the data for destruction diagnosis is not normal in step Sa7 (the data for destruction diagnosis is stored when power is interrupted) In the case other than 5A (H), the data in the RAM 41c is not normal, so the process proceeds to step Sa22 to execute initialization 1, and then the setting key switch 37 is turned on in step Sa23. For example, the processing of Sa19 to Sa21 described above is performed, and the setting change processing, that is, the setting change state is entered. If the setting key switch 37 is off in the step of Sa27, the above-described processing of Sa24 to Sa27 is performed, and the process proceeds to error processing, that is, a RAM abnormal error state. Then, when the RAM abnormal error state is canceled, the game processing shown in FIG. 7 is performed.

  If it is determined in step Sa7 that the destructive diagnosis data is normal, the data in the RAM 41c is normal. Therefore, the destructive diagnosis data is cleared (Sa8), and the unsaved work, unused area, and unreserved area in the RAM 41c are cleared. After performing initialization 3 to initialize the used stack area (Sa9), it is determined whether or not the setting key switch 37 is on (Sa10). If the setting key switch 37 is on, initialization 1 is executed. (Sa15), the processing of Sa19 to Sa21 described above is performed, and the process shifts to the setting change process, that is, the setting change state. Then, when the setting change process ends, the process proceeds to the game process shown in FIG.

  If the setting key switch 37 is OFF in the step of Sa10, each register is restored to the state before power interruption, that is, stored in the stack (Sa11), and the power interruption return 1 command (see FIG. 8) is generated. And stored in the command buffer (Sa12). Next, a power interruption return 2 command (see FIG. 8) is generated and stored in the command buffer (Sa13). Next, the power interruption recovery 3 command (see FIG. 8) is generated and stored in the command buffer (Sa14). Next, the power interruption return 4 command (see FIG. 8) is generated and stored in the command buffer (Sa15). Next, a hot start command (see FIG. 8) is generated and stored in the command buffer (Sa16). Then, the timer interrupt is set in the same manner as Sa20a (Sa16a), the random number generation circuit 42 is set in the same manner as Sa20b (Sa16b), and the main control unit 41 described in FIG. 8 and FIG. The interrupt of the timer interrupt process (main) executed at an interval of 0.56 ms is permitted (Sa17), and the process returns to the last executed before power interruption. If any of the processes in the game process shown in FIG. 7 has been performed before the power interruption, the process of Sd1 to Sd6 of the game process is performed based on the value of the program counter (PC) returned in Sa11. Returning to the processing that was performed before the power interruption. Also, for example, if any of the timer interrupt processing shown in FIG. 8 and FIG. 9 has been performed before power interruption, based on the value of the program counter (PC) restored in Sa11, Of the processes of the timer interrupt process Sk1 to Sk26, the process returns to the process performed before power interruption.

[About various commands]
Next, commands that the main control unit 41 transmits to the sub control unit 91 will be described. The command transmitted from the main control unit 41 to the sub-control unit 91 is composed of 1-byte mode data indicating the type of command and 1-byte EXT data indicating the content of the command. The sub-control unit 91 determines the type of command from the mode data, and determines the content of the command from the EXT data.

  Each command is temporarily stored in a command transmission buffer provided in a special work in the RAM 41c of the main control unit 41, and a command transmission process (main) executed in the timer interrupt process (main) shown in FIGS. In Sk16), it is transmitted to the sub-control unit 91.

  When the sub-control unit 91 receives a command from the main control unit 41, the sub-control unit 91 displays the image displayed from the liquid crystal display 51, the sound output from the speakers 53 and 54, and the front door according to the type of the received command. Control of the lamp etc. provided in 1b is performed.

  The setting change start command is a command indicating that setting change has been started. The setting change start command is transmitted at the start of setting change. In the EXT data, a value indicating that the setting change has been started is set.

  The setting change end command is a command indicating that the setting change has been completed and the setting value selected by the setting change. The setting change end command is transmitted when the setting change ends. In the EXT data, any one of six types of setting values selected by changing the setting is set.

  The error start command is a command indicating that an error has occurred. One of eight types of errors is set in the EXT data. The error start command is transmitted at the start of error processing. The eight types of errors include overflow tank overflow error indicating that the medal in the overflow tank 35 is full, no payout medal error indicating that there are no medals in the hopper tank 34a, and the payout medal is the hopper tank. 34a, a payout medal clogging error indicating that it is clogged, a medal selector abnormal error indicating that a medal detection error has occurred, a reel rotation error error indicating that the reel is not rotating normally, An illegal winning error indicating that the winning prediction flag expected to win based on the result of the internal lottery and the actual winning result does not coincide with each other, and an RWM content error indicating RAM abnormality are set.

  The error release command is a command indicating that the error has been released. The error cancel command is sent when error processing is cancelled. In the EXT data, a value indicating that the error has been canceled is set.

  The settlement start command is a command indicating that the medal settlement has started. The checkout start command is transmitted at the start of the checkout process. In the EXT data, either data indicating that the inserted medal has been settled or data indicating that the credited medal has been settled is set.

  The settlement end command is a command indicating that the medal settlement has ended. The settlement end command is transmitted at the end of the settlement process. In the EXT data, a value indicating that the settlement has been completed is set.

  The medal insertion command is a command indicating that a medal has been inserted. The medal insertion command is transmitted when a medal is inserted without credit addition. In the EXT data, a value indicating the number of inserted medals (one to three) is set.

  The credit increase command is a command indicating that the number of credited medals has increased. The credit increase command is transmitted when a medal with credit addition is inserted. In the EXT data, a value indicating that the credit has increased is set.

  The game counter 1 command is a command indicating a count value of 0 to 127 that is counted every time a game is played. The game counter 1 command is transmitted when the operation of the start switch is accepted. In the EXT data, a value indicating any one of the count values from 0 to 127 is set.

  The reel acceleration information command is a command indicating that reel rotation has started. The reel acceleration information command is transmitted when the start switch operation is accepted. In the EXT data, a value indicating one of nine types of reel rotation start patterns is set.

  The internal winning command is a command indicating whether or not BB is won and the state of RT. The internal winning command is transmitted when the start switch operation is accepted. In the EXT data, a value indicating whether or not BB is won and a state of RT is set.

  The winning number command is a command indicating the result of the internal lottery. The winning number command is transmitted when the start switch operation is accepted. A value indicating the result of the internal lottery is set in the EXT data.

  The BB inserted number 1 command is a command indicating the number of medals inserted in the BB game. The BB inserted number 1 command is transmitted at the start of reel rotation. A value indicating the number of inserted medals is set in the EXT data.

  The reel stop acceptance 1 command is a command indicating that the first stop has been performed. The reel stop acceptance 1 command is transmitted when a stop switch operation is accepted. In the EXT data, a value indicating the reception state of each stop switch (that is, whether or not it has been operated) and the lighting state of the LED incorporated in each stop switch (whether or not it is lit) are set.

  The reel sliding frame number 1 command is a command indicating the number of frames until the reel stops when the first stop is performed. The reel sliding frame number 1 command is transmitted when a stop switch operation is accepted. In the EXT data, a value indicating the number of frames (0 to 4 frames) until the reel stops is set.

  The reel stop position 1 command is a command indicating a position where the reel stops when the first stop is performed. The reel stop position 1 command is transmitted when a stop switch operation is accepted. A value indicating the reel stop position (frame number 0 to 20) is set in the EXT data.

  The reel stop acceptance 2 command is a command indicating that the second stop has been performed. The reel stop acceptance 2 command is transmitted when a stop switch operation is accepted. In the EXT data, a value indicating the reception state of each stop switch (that is, whether or not it has been operated) and the lighting state of the LED incorporated in each stop switch (whether or not it is lit) are set.

  The reel sliding frame number 2 command is a command indicating the number of frames until the reel stops when the second stop is performed. The reel sliding frame number 2 command is transmitted when the operation of the stop switch is accepted. In the EXT data, a value indicating the number of frames (0 to 4 frames) until the reel stops is set.

  The reel stop position 2 command is a command indicating a position where the reel stops when the second stop is performed. The reel stop position 2 command is transmitted when a stop switch operation is accepted. A value indicating the reel stop position (frame number 0 to 20) is set in the EXT data.

  The reel stop acceptance 3 command is a command indicating that the third stop has been performed. The reel stop acceptance 3 command is transmitted when a stop switch operation is accepted. In the EXT data, a value indicating the reception state of each stop switch (that is, whether or not it has been operated) and the lighting state of the LED incorporated in each stop switch (whether or not it is lit) are set.

  The reel sliding frame number 3 command is a command indicating the number of frames until the reel stops when the third stop is performed. The reel sliding frame number 3 command is transmitted when the operation of the stop switch is accepted. In the EXT data, a value indicating the number of frames (0 to 4 frames) until the reel stops is set.

  The reel stop position 3 command is a command indicating a position where the reel stops when the third stop is performed. The reel stop position 3 command is transmitted when a stop switch operation is accepted. A value indicating the reel stop position (frame number 0 to 20) is set in the EXT data.

  The game counter 2 command is a command indicating a count value of 0 to 127 that is counted each time a game is played. The game counter 2 command is transmitted after all reels are stopped. In the EXT data, a value indicating any one of the count values from 0 to 127 is set.

  The RT information 2 command is a command indicating whether or not BB has been won, whether or not RB has been won, and the state of RT. The RT information 2 command is transmitted when the start switch operation is accepted. In the EXT data, a value indicating whether or not BB is won or not or whether or not RB is won and the state of RT is set.

  The winning number 1 command is a command indicating the type of winning. The winning number 1 command is transmitted at the start of the medal payout process. In the EXT data, a value indicating the operating state of the BB (whether or not BB is in progress) and the type of winning is set.

  The winning number 2 command is a command indicating the type of winning. The winning number 1 command is transmitted at the start of the medal payout process. In the EXT data, a value indicating the operating state of the BB (whether or not BB is in progress) and the type of winning is set.

  The winning number command is a command indicating the number of medals to be paid out by winning. The winning number command is transmitted at the start of the medal payout process. A value indicating the number of medals paid out is set in the EXT data.

  The BB payout number 1 command is a command indicating the payout number of medals during BB. The BB payout number 1 command is transmitted at the start of the medal payout process during BB. In the EXT data, a value (upper 7 bits) indicating a payout number of medals in BB is set.

  The BB payout number 2 command is a command indicating the payout number of medals during BB. The BB payout number 2 command is transmitted at the start of the medal payout process during BB. In the EXT data, a value (lower 7 bits) indicating the number of medals paid out in BB is set.

  The BB end wait command is a command indicating that BB end is waiting. The BB end wait command is transmitted when the BB ends. In the EXT data, a value indicating the type of BB waiting for termination (one type in this embodiment) is set.

  The BB end command is a command indicating that BB ends. The BB end command is transmitted at the end of BB, at the start of automatic checkout, and at the start of stop processing. In the EXT data, a value indicating the type of BB to be terminated (one type in the present embodiment) is set.

  The RT information 1 command is a command indicating an RT state. The RT information 1 command is transmitted at the end of the game. A value indicating the state of RT is set in the EXT data.

  The BB operation type command is a command indicating whether or not BB is in progress. The BB operation type command is transmitted at the end of the game. In the EXT data, a value indicating whether or not BB is in progress is set.

  The game end command is a command indicating a game state (BB, RB, replay winning) when the game is ended. The game end command is transmitted at the end of the game. In the EXT data, a value indicating a gaming state (BB, RB, replay winning) when the game is finished is set.

  The door command is a command indicating whether or not the front door 1b is opened. The door command is transmitted when the power is turned on, when the setting change starts, when the RWM content error starts, when the game ends, or when the door is opened or closed. In the EXT data, a value indicating the door open state (whether open or closed) is set.

  The power interruption return 1 command is a command indicating a count value of 0 to 127 that is counted every time the game is played. The power interruption return 1 command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating any one of the count values from 0 to 127 is set.

  The power interruption return 2 command is a command indicating whether or not BB has been won and the state of RT. The power interruption recovery 2 command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating whether or not BB is won and a state of RT is set.

  The power interruption return 3 command is a command indicating whether or not BB is in progress and the number of inserted medals. The power failure recovery 3 command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating whether the BB is in progress and the number of inserted medals is set.

  The power interruption return 4 command is a command indicating a gaming state (BB, RB, replay winning) when the game is finished. The power interruption recovery 4 command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating a gaming state (BB, RB, replay winning) when the game is finished is set.

  The hot start command is a command indicating that restart is performed without turning off the power. The hot start command is transmitted when the backup is normal after the power is turned on. In the EXT data, a value indicating that restart is performed without turning off the power is set.

[Game processing]
FIG. 7 is a flowchart showing the control contents of the game process executed by the main control unit 41.

  As shown in FIG. 7, in the game process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a winning determination process (Sd4), a payout process (Sd5), and a game end process (Sd6). ) Are executed in order, and when the game end process is completed, the process returns to the BET process.

  In the BET process in the step of Sd1, the process waits in a state where a bet number can be set, and a process for starting a game when a specified number of bets is set according to the gaming state and the start switch 7 is operated is executed. .

  In the internal lottery process in the step of Sd2, whether or not winning is awarded to each of the above-described winning combinations based on the internal lottery random value latched simultaneously with the start of the game by the detection of the start switch 7 in the step of Sd1 (ie, display) A process for determining whether or not to permit the derivation of the result is performed. In this internal lottery process, a winning flag is set in the RAM 41c based on the respective lottery results. When a special combination (BB or RB) is won by internal lottery, a special combination carry-over flag is set. Then, as described above, the presence / absence of the special role carry-over flag is determined to determine whether or not the special role is carried over. Determination processing is performed.

  In the reel rotation process in the step Sd3, the process of rotating the reels 2L, 2C, 2R in response to the operation of the start switch 7, the result of the internal lottery in the step Sd2, and the stop switches 8L, 8C, 8R by the player Processing for stopping the rotation of the corresponding reels 2L, 2C, 2R is executed in response to the detected operation.

  In the winning determination process in step Sd4, when it is determined in step Sd3 that the rotation of all the reels 2L, 2C, 2R has stopped, a winning is determined according to the display result derived for each reel 2L, 2C, 2R. A process of determining whether or not it has occurred is executed. If the special combination wins, the special combination carry-over flag is cleared in this process.

  In the payout process in step Sd5, when it is determined that a prize is generated in step Sd4, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd6, a process of setting a gaming state in preparation for the next game is executed.

  In the game process, a command is generated according to the progress control of the game, set in the command buffer, and transmitted to the sub-control unit 91.

[Timer interrupt processing (main)]
8 and 9 are flowcharts showing the control contents of the timer interrupt process (main) executed by the main control unit 41 by interrupting and executing the initial setting process and the game process at a constant interval (0.56 ms interval). Note that other interrupts are automatically prohibited during the execution period of the timer interrupt process (main).

  As shown in FIGS. 8 and 9, in the timer interrupt process (main), first, the register in use is saved in the stack area (Sk1).

  Next, a power failure determination process is performed (Sk2). In the power failure determination process, it is determined whether or not a voltage drop signal is input from the power failure detection circuit 48. If a voltage drop signal is input, whether or not the voltage drop signal is input in the previous power failure determination process as well. If a voltage drop signal has been input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that is set.

  After the power failure determination process in the step of Sk2, it is determined whether or not the power interruption flag is set (Sk3). If the power interruption flag is not set, the process proceeds to Sk4 and the power interruption flag is set In this case, the process proceeds to a power interruption process (main).

  In step Sk4, port input processing for inputting detection data of various switches from the input port is performed.

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sk5). In this embodiment, the timer interrupt 1 is a branch process during a timer interrupt that controls the motor to control the start of the reel. Specifically, the processes from Sk9 to Sk11, such as a reel start process described later. Is done. Timer interrupt 2 is branch processing during timer interrupt that performs LED display control, time counter update, door open / close status monitoring, control signal output control, command and external output signal update, etc. Specifically, the processes of Sk12 to Sk17 such as the LED dynamic display process described later are performed. The timer interrupt 3 is a branching process during timer interrupt that detects the origin passage of the reel, monitors the switch input, and reads out the random number value. Processing of Sk20 to Sk22 such as time processing is performed. The timer interrupt 4 is a branching process during a timer interrupt that detects the input of a stop switch and performs reel stop control. Specifically, the processes of Sk23 to Sk25, such as a stop switch process described later. Is done. In the step of Sk5, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process (main) is executed.

  Next, the branch counter value is referenced to determine whether it is 2 or 3, that is, timer interrupt 3 or timer interrupt 4 (Sk6). If it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interrupt 2, it is checked whether the reel motors 32L, 32C, 32R are started or whether they are rotating at a constant speed, and whether the reel motors 32L, 32C, 32R are started or are rotating at a constant speed. For example, the motor phase signal output process for outputting the phase signal data changed in the motor step process of Sk10 described later and the phase signal data changed in the final stop process of Sk24 described later is executed (Sk7).

  Next, referring to the counter value for branching, it is determined whether or not it is 1, that is, timer interrupt 2 (Sk8). If it is not timer interrupt 2, that is, timer interrupt 1, the reel motor Reel starting process (Sk9) for controlling the step time interval when starting 32L, 32C, 32R, motor step process (Sk10) for changing phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C After the stop of 32R, motor phase signal standby processing (Sk11) for changing the phase signal to one-phase excitation after a predetermined time has been sequentially executed, and then the process proceeds to step Sk25.

  In the case of timer interrupt 2 in the step of Sk8, LED dynamic display processing (Sk12) for dynamically lighting various indicators, and output processing of control signals and the like for outputting data such as lighting signals of various LEDs to the output port (Sk13), a time counter update process (Sk14) for updating various time counters, a door monitoring process (Sk15) for monitoring the detection state of the door open detection switch 25, a door command transmission request, etc., set in the command buffer A command transmission process (Sk16) for transmitting various commands such as a setting change command, a return command, and an error command to the sub-control unit 91 and an external output signal update process (Sk17) for updating the external output signal are sequentially executed, and then Sk25. Go to step.

  If it is timer interrupt 3 or timer interrupt 4 in the step of Sk6, it is further determined by referring to the counter value for branching whether it is 3, that is, timer interrupt 4 (Sk18). If it is not interrupt 4, that is, if it is timer interrupt 3, the passing of the origin of the rotating reels 2L, 2C, 2R (pass of the reel reference position) is checked, and the occurrence of a reel rotation error is detected and stopped. Check if the preparation is complete (whether the stop preparation completion code is set). If the stop preparation is complete and the motor is rotating at a constant speed, operate the stop switch corresponding to the rotating reel. Whether or not there has been a change in the detection state of switches such as pass-through origin processing (Sk20) to be validated, MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R First, switch input determination processing (Sk21) for making a transmission request for an operation detection command, etc., and random number reading processing (Sk22) for reading numerical data from the random value register R1D and storing it in the random value storage work are sequentially executed. Go to step.

  If the timer interrupt is 4 in the step of Sk18, the stop stored in the work on the stop reel is stored when the stop operation position is stored in the work on the stop reel in accordance with the detection of the stop switches 8L, 8C, 8R. The stop position is determined from the operation position, the stop switch process (Sk23) for calculating the number of steps after which the stop should be performed, and the number of steps until the stop calculated in the stop switch process is counted. A stop process (Sk24) for starting braking by two-phase excitation and a final stop process (Sk25) for three-phase excitation after a certain time from the start of braking in the stop process are sequentially executed, and then the process proceeds to step Sk26.

  In the step of Sk26, the register saved in the stack area in Sk1 is restored, and the processing before the interruption is returned.

[Power interruption (main)]
FIG. 10 is a flowchart showing the control contents of the power interruption process (main) executed when the main control unit 41 determines that the power interruption flag is set in the timer interrupt process (main) described above.

  In the power interruption process (main), first, all registers that may be in use are saved in the stack area (Sm1). Although the values of the I register and IY register described above are used, they are not saved here because the same fixed value is always set with the initialization at the time of startup.

  Next, destruction diagnosis data (in this embodiment, 5A (H)) is set (Sm2). Then, the main control unit 41 described in FIGS. 8 and 9 prohibits the interruption of the timer interruption process (main) executed at a constant interval (interval of 0.56 ms), and initializes all output ports ( Sm3). Next, RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including unused areas and unused stack areas) of the RAM 41c becomes 0 (Sm4), and access to the RAM 41c is performed. Prohibited (Sm5).

  Thereafter, the voltage decreases, and the CPU 41a of the main control unit 41 stops and shifts to a standby state. And if a voltage falls in this standby state, it will be in an operation stop state internally. Therefore, the main control unit 41 reliably stops operation when power is interrupted.

  In this embodiment, interrupts are disabled before the output port is initialized. However, the sub-control board 90, the external output board 1000, and the output port for outputting data to the reel motor and reel sensor. Interrupt writing may be set before data is written or data is written to the serial communication circuit.

[About microcomputer configuration]
As shown in FIG. 11, the microcomputer used as the main control unit 41 or the sub control unit 91 includes a clock generation circuit 200, a reset controller 201, an interrupt controller 202, a WDT (watchdog timer) 203, a CTC (counter timer). ) 204, arithmetic circuit 205, address decoder 206, CPU 207 used as the main CPU 41 a and sub CPU 91 a, ROM 208 used as the ROM 41 b and ROM 91 b, RAM 209 used as the ROM 41 c and RAM 91 c, M1 counter 210, inspection port 211, random number generation circuit 42 Random number circuit 212, general-purpose initial value random number circuit 212, serial communication circuit 214, PWM (pulse width modulation) output circuit 215, interrupt / general-purpose output circuit 216, random number And a part latch input circuit 217.

  The microcomputer shown in FIG. 11 includes individual IDs, ROM read restrictions, 64-pin SZIP encapsulation, and an inspection port 211 as security functions.

  The CPU 207 operates at a frequency of 10 MHz (minimum instruction execution time: 100 msec).

  The ROM 208 has a capacity of 10,240 bytes, and the RAM 209 has a capacity of 512 bytes.

  In addition, the reset function has four functions of system reset, WDT (watchdog timer) reset, periodic reset, and illegal access reset.

  In addition, as an interrupt function, two functions of an external terminal interrupt (INT / NMI) and a CTC interrupt (CTC0, CTC1, CTC2) are provided.

  Further, 16 chip select terminals are used in the CS mode and 23 chips in the ECS mode. The CTC 204 has 16 bits × 3 channels.

  The random number circuit 212 includes a total of 16 channels of 8 bits fixed length random number × 8 channels, 16 bits fixed length random number × 2 channels, 8 bits variable length random number × 4 channels, and 16 variable length random numbers × 2 channels. Further, the general-purpose initial value random number circuit 212 has one channel.

  The serial communication circuit 214 includes transmission × 3 channels and reception × 1 channel.

  The arithmetic circuit 205 calculates CRC16, checksum, and horizontal parity.

  The PWM output circuit 217 includes four channels. The general purpose external latch input circuit has three inputs.

  Also, four general-purpose input / output terminals are provided on the input side and three on the output side. The address decoder 207 is used for the output of CS0 to CS15.

[Address map of memory space]
Next, an address map of the memory space in the ROM 208 and RAM 209 of the microcomputer shown in FIG. 11 will be described with reference to FIG. The memory space shown in FIG. 12 is a memory space accessed with a 16-bit address. The memory space is accessed with a memory instruction. In FIG. 12, 0000h to 7FFFh is a RAM memory space, and 8000h to FFFFh is a ROM memory space.

  The memory space of the RAM 209 is a usable area where the memory space addresses 0000h to 01FFh can be accessed. Memory space addresses 0200h to 0FFFh are unused areas where access is prohibited. Internal registers are allocated to memory space addresses 1000h to 1080h. Memory space addresses 1081h to 7FFFh are unused areas where access is prohibited. ROM is allocated to memory space addresses 8000h to A7FFh. Memory space addresses A800h to FFFFh are unused areas where access is prohibited.

  In the memory space of the ROM 208, programs / data are allocated to addresses 8000h to A6FFh. A ROM comment is assigned to addresses A700h to A7FFh. A vector table is assigned to addresses A780h to A7A7h. Also, HW parameters are assigned to addresses A7A8h to A7FFh.

  As described above, the 512-byte RAM is arranged in 0000h to 01FFh. When a system reset or WDT reset occurs, the RAM protection state is entered. In the RAM protected state, the RAM can be read but not written. To release the RAM protection state, 00h or 80h is set in the RAM protection register (RAMPT).

  The internal function registers are a group of registers for controlling each function installed in the microcomputer of FIG. If 1 is set in the internal function register arrangement (HRGACS) of the system setting of the HW parameter (HSYSCNT), it can also be arranged in the I / O space.

  A 10,240-byte ROM is arranged in 8000h to A7FFh. In the ROM area, programs / data, ROM comments, vector tables, and HW parameters are arranged.

  The microcomputer executes the program from 8000h after the system reset, WDT reset, periodic reset, and illegal access reset. The program cannot be executed outside this area.

  The ROM comment is an area for setting the title, version, etc. of the program, and arbitrary data can be set. The data set here can be read from the inspection ports (TXD, RXD, STB, DIR).

  The vector table is a table for setting the start address of the subroutine of the CALLV instruction and the start address of the interrupt process. 0000h is set for the unused vector table. If the values set in the vector table are other than 0000h and 8000h to HPRGEND, the microcomputer does not start. HPRGEND is set by the program end address of the HW parameter.

  The HW parameter is a parameter for setting the internal function of the microcomputer by hardware. The setting is described as a constant table. It cannot be written by a program.

[Vector table address map]
Next, an address map of the vector table in the memory space of the ROM 208 shown in FIG. 12 will be described with reference to FIG.

  As shown in FIG. 13, in the vector table, memory space addresses A780h to A79Fh are vector tables for CALLV instructions, and memory space addresses A7A0h to A7A7h are vector tables for interrupt processing.

  In the memory space addresses A780h to A781h of the CALLV instruction vector table, (lower) and (upper) values of CALLV0 are set. In the memory space addresses A782h to A783h, (lower) and (upper) values of CALLV1 are set. In the memory space addresses A784h to A785h, (lower) and (upper) values of CALLV2 are set. In the memory space addresses A786h to A787h, (lower) and (upper) values of CALLV3 are set. In the memory space addresses A788h to A789h, (lower) and (upper) values of CALLV4 are set. In the memory space addresses A78Ah to A78Bh, (lower) and (upper) values of CALLV5 are set. In the memory space addresses A78Ch to A78Dh, (lower) and (upper) values of CALLV6 are set. In memory space addresses A78Eh to A78Fh, (lower) and (upper) values of CALLV7 are set. In the memory space addresses A790h to A791h, (lower) and (upper) values of CALLV8 are set. In the memory space addresses A792h to A793h, (lower) and (upper) values of CALLV9 are set. In the memory space addresses A794h to A795h, (lower) and (upper) values of CALLV10 are set. In the memory space addresses A796h to A797h, (lower) and (upper) values of CALLV11 are set. In the memory space addresses A798h to A799h, (lower) and (upper) values of CALLV12 are set. In the memory space addresses A79Ah to A79Bh, (lower) and (upper) values of CALLV13 are set. In the memory space addresses A79Ch to A79Dh, (lower) and (upper) values of CALLV14 are set. In the memory space addresses A79Eh to A79Fh, (lower) and (upper) values of CALLV15 are set.

  INT / NMI (lower) and (upper) values are set in the memory space addresses A7A0h to A7A1h of the interrupt processing vector table. In memory space addresses A7A2h to A7A3h, (lower) and (upper) values of CTC0 are set. In memory space addresses A7A4h to A7A5h, (lower) and (upper) values of CTC1 are set. In memory space addresses A7A6h to A7A7h, (lower) and (upper) values of CTC2 are set.

[HW parameter list]
Next, HW parameters in the memory space of the ROM 208 shown in FIG. 12 will be described with reference to FIG.

  As shown in FIG. 14, the memory space address A7A8h is associated with the symbol HCSATRO and used for CS / PWM setting. The memory space address A7A9h is associated with the symbol HCSATR1 and is used for CS / PWM setting. The memory space address A7AAh is associated with the symbol HCSATR2 and is used for CS / PWM setting. The memory space address A7ABh is associated with the symbol HCSATR3 and is used for CS / PWM setting. The memory space address A7ACh is associated with the symbol HCSATR4 and used for CS / PWM setting. The memory space address A7ADh is associated with the symbol HCSATR5 and is used for CS / PWM setting. The memory space address A7AEh is associated with the symbol HCSATRD and used for CS / PWM setting.

  The memory space address A7AFh is associated with the symbol HPRST and is used for periodic reset setting.

  The memory space address A7B0h is associated with the symbol HRDMD and is used for setting the random number circuit operation mode.

  The memory space address A7B1h is associated with the symbol HSYSCNT and is used for system setting.

  The memory space address A7B2h is associated with the symbol HSYSCNT and is used for setting the reset period / INP terminal.

  The memory space addresses A7B3h to A7B4h are associated with a symbol HRPGEND and are used for setting a program end address.

  The memory space addresses A7B5h to A7B6h are associated with the symbol HRAMSTAT and are used for setting a RAM access prohibited address.

  The memory space addresses A7B7h to A7B8h are associated with the symbol HRAMEND and are used as RAM access prohibited addresses.

  The memory space addresses A7B9h to A7CCh are associated with the symbol HSWSTS and are used for setting the SW status.

  Memory space addresses A7CDh to A7CFh are used for setting a manufacturer code.

  Memory space addresses A7D0h to A7D7h are used for setting a product code.

  Memory space addresses A7D8h to A7FFh are used for setting a security code.

[Reset period / INP pin setting]
Next, the reset period / INP terminal setting in the HW parameter shown in FIG. 14 will be described with reference to FIG.

  As shown in FIG. 15, the symbol HPORTEN is associated with bit 7 of the memory space address A7B2h. In HPPORTEN, the INP terminal function setting is set. When it is set to 0, it is not used as an interrupt input terminal, and when it is set to 1, it is set to be used as an interrupt input terminal.

  Further, the symbol HPARTMD is associated with bit 6 of the memory space address A7B2h. In HPPORTMD, interrupt input settings and automatic mutual authentication settings are performed. When it is set to 0, it is set to be an INT interrupt input, and when it is set to 1, it is set to be an NMI interrupt input.

  Further, symbol HRTMEN is associated with bit 5 of memory space address A7B2h. In HRTMEN, a reset period extension setting is set. Then, the setting is made so as not to extend when set to 0, but to extend when set to 1. The extension time is fixed time + fluctuation time.

  Further, symbol HRRDEN is associated with bit 4 of memory space address A7B2h. In HRRDEN, the reset period extension setting is set. When bit 4 of A7B2h is set to 0, it always does not fluctuate at 0 msec. When MCLK (system clock) = 20 MHz, when it is set to 1, it is 0 to 1275 msec (5 msec, 256 types). Set to vary. Each time the system is reset, the time is different from the previous time.

  Further, the symbol HRSTM is associated with bits 3 to 0 of the memory space address A7B2h. In HRSTM, a fixed time is set. And in the case of MCLK = 20 MHz, it is set to be 1.0 sec when set to 0h. When set to 1h, it is set to 2.0 sec. Thereafter, the length is increased by 1.0 sec according to the set value, and is set to 30.0 sec at the maximum.

  As described above, whether or not to start interrupt processing when an L level signal is input to the interrupt input / general-purpose input terminal (INP) with the settings of HPPORTEN and HPARTMD, and whether the interrupt request is INT Interrupt or NMI interrupt can be selected.

  In addition, since the input level of the INP terminal can be read from the external signal input / reset factor register (PINSTS) regardless of the setting state of HORTEN, it can also be used as a general-purpose input.

  If HETMEN is set to 0, the reset period is not extended regardless of the settings of HRRDEN and HRSTM.

  When HRTMEN is set to 1, it is possible to extend the period until the program starts after the system reset period of 400.5 msec (in the case of MCLK = 20 MHz). The extended time is the sum of the fixed time set by HRSTM and the variable time set by HRRDEN.

For example, the system reset time when HRTMEN = 1, HRRDEN = 1, and HRSTM4h is set is as follows.
400.5 msec + 5.0 msec + (0-1275 msec) = 5.4005 sec-6.6755 sec (when MCLK = 20 MHz)

[Program end address]
Next, the program end address in the HW parameter shown in FIG. 14 will be described with reference to FIG.

  “8000h to A6FFh” in the memory space address is defined as an area for storing “program / data” as shown in FIG. However, the capacity of the “program / data” varies depending on the content of control of the gaming machine and is not stored in all of these areas. In this microcomputer, by setting the program end address, the range of the area where “program / data” is stored is set. If an area where “program / data” is not stored is accessed, illegal It can be set to generate an access reset. In addition, although the setting is performed by designating the end address (final address) for the range of the area where “program / data” is stored, the start address (start address) may be designated. Further, a plurality of separated areas may be set.

  As shown in FIG. 16, symbol HPRGEND (lower order) is associated with bits 7-0 of memory space address A7B3h, and symbol HPRGEND (upper order) is associated with bits 7-0 of memory space address A7B4h. In HPRGEND, a program end address is set. Then, the final address of the ROM area used in 8000h to A6FFh is set.

  If HPRGEND is set to a value other than 8000h to A6FFh, an error occurs and the microcomputer does not start. The last address is set in HPRGEND. If the entire ROM area is accessible, HPRGEND = A6FFh is set. When an area from address +1 set by HPRGEND to A6FFh is accessed, an illegal access reset occurs.

  As shown in FIG. 17, for example, when HPRGEND = 8852h is set, an illegal access reset occurs when 8852h is accessed.

[RAM access prohibited address]
Next, the RAM access prohibition address in the HW parameter shown in FIG. 14 will be described with reference to FIG.

  As shown in FIG. 18, the symbol HRAMSTAT (lower) is associated with bits 7-0 of the memory space address A7B5h, and the symbol HRAMSTAT (upper) is associated with bits 7-0 of the memory space address A7B5h. In HRAMSTAT, a RAM access prohibited start address is set. Then, the start address of the RAM area for which access is prohibited is set to 0000h to 01FFh.

  Symbols HRAMEND (lower) are associated with bits 7-0 of memory space address A7B7h, and symbols HRAMEND (upper) are associated with bits 7-0 of memory space address A7B8h. In HRAMEND, a RAM access prohibited end address is set. Then, the final address of the RAM area for which access is prohibited is set to 0000h to 01FFh.

If the values set in HRAMSTAT and HRAMEND do not satisfy the following relationship, the microcomputer does not start as an error state.
0000h ≦ HRAMSTAT ≦ HRAMEND ≦ 01FFh

  Further, the start address of the RAM area for which access is prohibited is set to HRAMSTAT, and the final address of the RAM area for which access is prohibited is set to HRAMEND.

  When accessing the entire RAM area, HRAMSTAT = 0000h and HRAMEND = 0000h are set.

  In addition, when an access prohibited area set by HRAMSTAT and HRAMEND is accessed, an illegal access reset occurs.

  As shown in FIG. 19, for example, when HRAMSTAT = 00F2h and HRAMEND = 01A7h are set, an illegal access reset occurs when 002Fh to 01A7h are accessed. Also, the settings of HRAMSTAT and HRAMEND can be invalidated by setting the RAM protect register (RAMPT).

[SW status]
Next, the SW status in the HW parameter shown in FIG. 14 will be described with reference to FIG.

  As shown in FIG. 20, the symbol HSWSTS0 (lower order) is associated with bits 7-0 of the memory space address A7B9h, and the symbol HSWSTS0 (upper order) is associated with bits 7-0 of the memory space address A7B8h. The same applies to HSWSTS1-9. In HSWSTS0 to 9, settings of SW status 0 to 9 are performed. The address of the RAM monitored by the inspection apparatus is set to 0000h to 01FFh.

  Note that if a value other than 0000h to 01FFh is set in HSWSTS0 to 9, the microcomputer does not start as an error state.

  If the address of the RAM access prohibition area set by the RAM access prohibition address (HRAMSTAT, HRAMEND) of the HW parameter is set in HSWSTS0 to 9, the microcomputer does not start as an error state.

  In addition, addresses to be monitored by the inspection apparatus are set to HSWSTS 0 to 9.

  If the SW status is not used, 0000h is set. However, if 0000h is set in the RAM access prohibited area, the microcomputer does not start as an error state, so it is preferable not to include 0000h in the RAM access prohibited area.

[Conditions for illegal access reset]
Next, conditions for causing an illegal access reset in the microcomputer shown in FIG. 11 will be described with reference to FIG. In the case shown in FIG. 21, it is determined that the access is illegal and an illegal access reset occurs. When an illegal access reset occurs, only the CPU core is reset and the internal functions are not reset.

  As shown in FIG. 21, in the CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting content is HCSRW0 = 00; the CS function is invalid (the same applies to HCSRW1 to HCSRW23), CS0 (C0h in the I / O space) ) (The same applies to CS1 to CS23) is a condition for generating an illegal access reset.

  In CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting content is HCSRW0 = 01; synchronized with the R0 signal (the same applies to HCSRW1 to HCSRW23), writing to CS0 (C0h in the I / O space) (The same applies to CS1 to CS23) is a condition for generating an illegal access reset.

  In CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting contents are HCSRW0 = 10; synchronized with the W0 signal (the same applies to HCSRW1 to HCSRW23), reading from CS0 (C0h in the I / O space) is performed. (The same applies to CS1 to CS23) is a condition for generating an illegal access reset.

  In CS / PWM setting (symbol name: HSMMOD), when the setting content is HCSMD = 0; CS mode, the access to the ECS area (D0h to D7h in the I / O space) has been illegally reset. It becomes the generation condition of.

  In CS / PWM setting (symbol name: HSMMOD), when the setting content is HCSMD = 1; in the ECS mode, the access condition to CS15 (CFh in the I / O space) is an occurrence condition of the illegal access reset. It becomes.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 0; memory space, an I / O access to the internal register is a condition for generating an illegal access reset.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 1; I / O space, the occurrence of the illegal access reset is that the memory has been accessed to the internal register.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 1; I / O space, the occurrence of the illegal access reset is that the memory has been accessed to the internal register.

  Next, regarding the setting of the program end address (symbol name: HPRGEND), the access condition to the area between the address next to the address set as the program end address and A6FFh is an illegal access reset generation condition. .

  Next, regarding the RAM access prohibition address (symbol name: HRAMSTAT, HRAMEND), an illegal access reset occurs because there is an access to the area between the start address and the final address of the RAM area set as the RAM access prohibition address It becomes a condition.

  Next, regarding the internal function register (symbol name: MKCODE), writing to MKCODE is a condition for generating an illegal access reset.

  Next, regarding the internal function register (symbol name: PRCODE), writing to PRCODE is a condition for generating an illegal access reset.

  Next, regarding the internal function register (symbol name: CPCODE), writing to CPCODE is a condition for generating an illegal access reset.

  Next, there was a write to the area (8000h to A7FFh) set as the ROM area, an access to the ROM comment area (A700h to A77Fh), and the access to the HW parameter area (A7A8h to A77Fh) The occurrence of an illegal access reset is an access condition.

  Next, an access condition to an unused area (200h to FFFh, 10B1h to 7FFFh, A800h to FFFh) in the memory space is a condition for generating an illegal access reset.

  Next, the occurrence condition of the illegal access reset is that the unused area (B1h to BFh) in the I / O space is accessed.

  Next, the occurrence condition of the illegal access reset is that the CPU core fetches the undefined instruction.

[Condition that does not start]
Next, the conditions under which the microcomputer shown in FIG. 11 does not start will be described with reference to FIG. If the condition shown in FIG. 22 is satisfied, it is determined that the error has occurred, and the microcomputer does not start.

  As shown in FIG. 22, in the setting of the vector table (related symbol name: HPRGEND), the condition that the microcomputer does not start is satisfied when values other than 0000h and 8000h to HPRGEND are set.

  In the CS / PWM setting (related symbol names: HCSMD, HCSRW16 to HCSRW23), the microcomputer does not start when the value set in the CS / PWM setting is HCSMD = 0 and the HCSRW16 is set to a value other than 00. Is satisfied. The same applies to HCSRW17 to HCSRW23.

  In the CS / PWM setting (related symbol names: HCSMD, HCSRW15), if HCSMD = 1 and HSCRW15 is set to a value other than 00, the condition that the microcomputer does not start is satisfied.

  In the CS / PWM setting (related symbol names: HPW0MD to HPW3MD, HCSRW11 to HCSRW14), the condition that the microcomputer does not start is satisfied when HPW0MD = 1 and a value other than 00 is set for HCSRW11. If HPW1MD = 1 and HCSRW12 is set to a value other than 00, the condition that the microcomputer does not start is satisfied. When HPW2MD = 1 and HCSRW13 is set to a value other than 00, the condition that the microcomputer does not start is satisfied. When HPW3MD = 1 and HCSRW 14 is set to a value other than 00, the condition that the microcomputer does not start is satisfied.

  In the CS / PWM setting (related symbol name: HSMMOD), when bit 4 = 1 of HCSMOD is set, the condition that the microcomputer does not start is satisfied. When bit 5 = 1 of HSMMOD is set, the condition that the microcomputer does not start is satisfied. When bit 6 = 1 of HSMMOD is set, the condition that the microcomputer does not start is satisfied.

  In the random number circuit operation mode setting (related symbol name: HRDMD), when bit 3 = 1 of HEDMD is set, the condition that the microcomputer does not start is satisfied.

  In the random number circuit operation mode setting (related symbol name: HFRCLK), the condition that the microcomputer does not start when HFRCLK = 1 is set and no random number external clock (EXCLK) is input is satisfied.

  In the random number circuit operation mode setting (relevant symbol name: HRDMYE), the condition that the microcomputer does not start when HRDMYE = 1 is satisfied.

  In the system setting (related symbol name: HSYSCNT), when bit 5 = 1 of HSYSCNT is set, the condition that the microcomputer does not start is satisfied. When bit 6 = 1 of HSYSCNT is set, the condition that the microcomputer does not start is satisfied. Further, when bit 7 = 1 of HSYSCNT is set, the condition that the microcomputer does not start is satisfied. Note that bits 5 to 7 of HSYSCNT are unused bits that are not used for setting any function, and are normally set to 0.

  In the system setting (related symbol names: HLNKMD, HAUTLK), when HLNKMD = 0 and HAUTLK = 1 are set, the condition that the microcomputer does not start is satisfied.

  In the program end address (related symbol name: HPRGEND), if a value other than 8000h to A6FF is set in HPRGEND, the condition that the microcomputer does not start is satisfied.

  In the RAM access prohibition address (related symbol names: HRAMSTAT, HRAMEND), if 0000h ≦ HRAMSTAT ≦ HRAMEND ≦ 01FFh is not satisfied, the condition that the microcomputer does not start is satisfied.

  In the SW status (related symbol names: HSWSTS0 to HSWSTS9), if HSWSTS0 is set to a value other than 0000h to 01FFh, the condition that the microcomputer does not start is satisfied. The same applies to HSWSTS1 to HSWSTS9.

  In the SW status (related symbol names: HSWSTS0 to HSWSTS9, HRAMSTAT, HRAMEND), the condition that the microcomputer is not started is satisfied when the value of the access prohibition right area set by HRAMSTAT and HRAMEND is set in HSWSTS0. The same applies to HSWSTS1 to HSWSTS9.

[Change in operation due to reset factor]
Next, a change in operation due to a reset factor in the microcomputer shown in FIG. 11 will be described with reference to FIG. As shown in FIG. 23, the operation varies depending on four types of reset factors.

  When the system reset is performed, the system reset period is set. When the reset factor is any of WDT reset, periodic reset, and illegal access reset, the system reset period is not set.

  If the reset period is extended by a system reset, the reset period extension is set when the reset period extension is set to be effective by the HW parameter, and it is set by any of WDT reset, periodic reset, and illegal access reset. If the reset period is not extended, no extension of the reset period is set.

  When any one of system reset, WDT reset, periodic reset, and illegal access reset is performed, the CPU core is initialized.

  Also, the input / output terminals are initialized when a system reset is performed, and the input / output terminals are not initialized when any of WDT reset, periodic reset, and illegal access reset is performed.

  Further, the contents of the RAM do not change even when any one of system reset, WDT reset, periodic reset, and illegal access reset is performed.

  The RAM is set in the protected state when either a system reset or a WDT reset is performed, and the RAM is not set in a protected state when either a periodic reset or illegal access reset is performed.

  The CTC is initialized when either a system reset or WDT reset is performed, and the CTC is not initialized when either a periodic reset or illegal access reset is performed.

  Further, WDT is initialized when a system reset is performed, and WDT is not initialized when any of WDT reset, periodic reset, and illegal access reset is performed.

  In addition, the order of clear values in the WDT cyclic clear mode is initialized when a system reset is performed, and the WDT cyclic clear mode is cleared when any of WDT reset, periodic reset, and illegal access reset is performed. The order of values is not initialized.

  In addition, serial communication is initialized by interrupting transmission / reception when a system reset is performed, and is not initialized when any of WDT reset, periodic reset, and illegal access reset is performed.

  Further, the interrupt controller is initialized when either system reset or WDT reset is performed, and the interrupt controller is not initialized when either periodic reset or illegal access reset is performed.

  In addition, when a system reset is performed, external signal input / reset factors, register reset factors, and bits 5 to 7 of PINSTS are initialized, and any of WDT reset, periodic reset, and illegal access reset is performed. It will not be initialized if

  Further, the random number circuit is initialized when either the system reset or the WDT reset is performed, and the random number circuit is not initialized when either the periodic reset or the illegal access reset is performed.

  In addition, the initial value of the random number is different each time when either system reset or WDT reset is performed, and the initial value of random number is the start before resetting when either periodic reset or illegal access reset is performed. Set to a value.

  Further, the random number error status register is initialized when the system reset is performed, and is not initialized when any of the WDT reset, the periodic reset, and the illegal access reset is performed.

  Further, when the system reset is performed, the general-purpose initial value random number is different every time. When any of the WDT reset, the periodic reset, and the illegal access reset is performed, the general-purpose initial value random number does not change.

  Further, the M1 counter is initialized when either system reset or WDT reset is performed, and the M1 counter is not initialized when either periodic reset or illegal access reset is performed.

  Further, the periodic reset monitor is initialized when either the system reset or the WDT reset is performed, and the periodic reset monitor is not initialized when either the periodic reset or the illegal access reset is performed.

  The arithmetic function is initialized when either a system reset or a WDT reset is performed, and the arithmetic function is not initialized when either a periodic reset or illegal access reset is performed.

  Also, the PWM output is initialized when either system reset or WDT reset is performed, and the PWM output is not initialized when either periodic reset or illegal access reset is performed.

[Internal function register]
Next, the internal function register shown in FIG. 12 will be specifically described with reference to FIG. In the figure, S indicates “system reset” and W indicates “WDT reset”. Further, R / W (Read / Write) indicates that R / W can read and write, R can only read, and W can only write. In addition, a description will be given with some functions omitted.

  The functions not shown in the figure include a random number maximum value register that determines the maximum value of the random number value to be updated by the random number circuit, an external latch signal permission register that determines the operation when acquiring the random value, an external latch signal mode register, The registers related to the random number circuit are included, and these initialization factors are system reset and WDT reset (see FIG. 23).

  As shown in FIG. 24, a RAM protect register (RAMPT) is assigned to the I / O space address 00h and the memory space address 1000h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT0) is assigned to the I / O space address 01h and the memory space address 1001h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT1) is assigned to the I / O space address 02h and the memory space address 1002h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT2) is assigned to the I / O space address 03h and the memory space address 1003h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC0) is allocated to the I / O space addresses 04h and 05h and the memory space addresses 1004h and 1005h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC1) is allocated to the I / O space addresses 06h and 07h and the memory space addresses 1006h and 1007h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC2) is allocated to the I / O space addresses 08h and 09h and the memory space addresses 1008h and 1009h. R / W is R / W, and initialization factors are S and W.

  A WDT control register (WDTCNT) is assigned to the I / O space address 0Ah and the memory space address 100Ah. R / W is R / W, and initialization factors are S and W.

  A WDT clear register (WDTCLLR0) is assigned to the I / O space address 0Bh and the memory space address 100Bh. R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR1) is assigned to the I / O space address 0Ch and the memory space address 100Ch. R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR2) is assigned to the I / O space address 0Dh and the memory space address 100Dh. R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR3) is assigned to the I / O space address 0Eh and the memory space address 100Eh. R / W is W. There is no initialization factor.

  An interrupt request register (IRR) is assigned to the I / O space address 23h and the memory space address 1023h. R / W is R / W, and initialization factors are S and W.

  An interrupt permission register (IRR) is assigned to the I / O space address 24h and the memory space address 1024h. R / W is R / W, and initialization factors are S and W.

  An interrupt priority register (IPR) is assigned to the I / O space address 25h and the memory space address 1025h. R / W is R / W, and initialization factors are S and W.

  An external signal input / reset factor register (PINSTS) is assigned to the I / O space address 26h and the memory space address 1026h. R / W is R / W, and the initialization factor is S.

  A periodic reset monitor register (ITRMN) is assigned to the I / O space address 94h and the memory space address 1094h. R / W is R, and initialization factors are S and W.

  An arithmetic data register (CDAT) is assigned to the I / O space address 95h and the memory space address 1095h. R / W is R / W, and initialization factors are S and W.

  A horizontal parity calculation result register (CPTY) is assigned to the I / O space address 96h and the memory space address 1096h. R / W is R / W, and initialization factors are S and W.

  A checksum operation result register (CSUM) is allocated to the I / O space addresses 97h and 98h and the memory space addresses 1097h and 1098h. R / W is R / W, and initialization factors are S and W.

  A CRC16 operation result register (CCRC) is assigned to the I / O space addresses 99h and 9Ah and the memory space addresses 1099h and 109Ah. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC0) is assigned to the I / O space address 9Bh and the memory space address 109Bh. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC1) is assigned to the I / O space address 9Ch and the memory space address 109Ch. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC2) is assigned to the I / O space address 9Dh and the memory space address 109Dh. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC3) is assigned to the I / O space address 9Eh and the memory space address 109Eh. R / W is R / W, and initialization factors are S and W.

  A manufacturer code register (MKCODE) is assigned to the I / O space addresses A2h, A3h, and A4h and the memory space addresses 10A2h, 10A3h, and 10A4h. R / W is R. There is no initialization factor.

  Product code registers (PRCODE) are assigned to the I / O space addresses A5h to ACh and the memory space addresses 10A5h to 10ACh. R / W is R. There is no initialization factor.

  A chip code register (CPCODE) is assigned to the I / O space addresses ADh to B0h and the memory space addresses 10ADh to 10B0h. R / W is R. There is no initialization factor.

[RAM protection]
Next, RAM protection will be described. The RAM protect is a function for preventing the RAM from being rewritten by an incorrect operation.

  The operation of RAM protection is as follows. After a system reset or WDT reset occurs, the RAM is protected. In the RAM protected state, data can be read from the RAM, but data cannot be written to the RAM. When writing data to the RAM, the RAM protection is set to invalid in the RAM protection register (RAMPT). If the RAM access prohibition area setting of the RAMPT is set to invalid, the RAM access prohibition area exists if HRAMSTAT = 0000h and HRAMEND = 0000h are set even if the RAM access prohibition area of the HW parameter is enabled. No illegal access reset occurs.

[RAM protect register]
Next, the RAM protector register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 25, in the RAM protect register, the symbol RAMPT is associated with bits 7 to 0 of the memory space address 1000h (I / O space address 00h). In RAMPT, RAM protection is set and RAM access prohibited area is controlled. At 00h, the RAM access prohibition area is set to invalid, and RAM protection is set to invalid. In 01h, the RAM access prohibited area is set to be invalid, and the RAM protect is set to be valid. In 80h, the RAM access prohibition area is set to be valid, and the RAM protect is set to be invalid. In 81h, the RAM access prohibition area is set valid, and the RAM protect is set valid. Other than these values, the state is retained. Note that R / W is R / W, and the initial value is 81h.

[Counter timer (CTC)]
Next, CTC will be described with reference to FIG. The microcomputer shown in FIG. 11 has 3 channels of 16-bit CTC.

  The operation of CTC is as follows. The CTC counts down the set timer value, and outputs an interrupt request signal to the interrupt controller when it reaches 0000h. 0000h at this time is referred to as a terminal count. Since each CTC channel (CTC0-2) can be operated independently, an interrupt can be generated at three different time intervals.

  As shown in FIG. 26, since CTC0 and CTC1 can use the terminal count of CTC2 as a clock source, a long time interval can be easily created. For example, when the terminal count of CTC2 is set to the clock source of CTC0, the timer value of CTC2 is set to 2 msec, and CTC0 is set to 65,000 count, 2 msec × 65,000 = 130 sec can be counted. The CTC is initialized when a system reset or a WDT reset occurs.

The operation mode of CTC is as follows. The CTC has two operation modes: a one-shot timer mode that operates only once and an interval timer mode that operates repeatedly. In the one-shot timer mode, down-counting starts from the set timer value and stops when the terminal count is reached. An interrupt request is generated once when the terminal count is reached.
When the timer value is set to 5: 5 → 4 → 3 → 2 → 1 → 0 (stop)

In the interval timer mode, the countdown is performed from the set timer value, and when the terminal count is reached, the countdown is performed again from the set timer value. Each time the terminal count is reached, an interrupt request is repeatedly generated.
When the timer value is set to 5: 5 → 4 → 3 → 2 → 1 → 5 → 4 → ・ ・ ・ (repeated)

  Regarding the setting of the timer value, an arbitrary value or four types of fixed values (1 msec, 2 msec, 4 msec, and 1.4890 msec) can be set as the CTC timer value.

As an arbitrary value setting method, a timer value is set in the CTC data registers (CTC0 to CTC2), a timer value setting method, an operation mode, a clock frequency division, and a clock source in the CTC control registers (TMCNT0 to TMCNT2) are set.
Setting example for generating an interrupt every 3 msec in CTC0 1. CTC0 = 012 Ch Timer value = 300
2. TMCNT = 02h Timer value setting method = arbitrary value, operation mode = interval timer mode, clock division = 10 μsec, clock source = MLCK division

The fixed value setting method sets the timer value setting method, operation mode, and fixed value of the CTC control registers (TMCNT0 to TMCNT2).
Setting example for generating an interrupt every 4 msec in CTC0 1. TMCNT = 0Bh Timer value setting method = fixed value, operation mode = interval timer mode, fixed value setting = 4 msec
Setting of CTC0 (CTC0 data register) is unnecessary.

In CTC activation, the CTC count operation is stopped after the system reset and the WDT reset.
The activation of CTC is set in the following order.
1. A timer value is set in the CTC data registers (CTC0 to CTC2).
2. Set the CTC control registers (TMCNT0 to TMCNT2).
When setting a fixed value to the timer value setting method, The CTC data registers (CTC0 to CTC2) need not be set. Just set TMCNT0-2 to start. Even if CTC is counting, if TMCNT0-2 is set, it is updated with the setting contents of CTC0-2 and TMCNT0-2. The timer value being counted is counted down again from the set value of CTC0-2.

[CTC control register]
Next, the CTC control register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 27, in the CTC control register, bit 7 of the memory space address 1001h (I / O space address 01h) is unused and is always 0. Note that R / W is R and the initial value is 0.

  Symbol C0CKCEL is associated with bit 6 of memory space address 1001h (I / O space address 01h), and symbol C1CKCEL is associated with bit 6 of memory space address 1002h (I / O space address 02h). In C0CKCEL and C1CKCEL, the clock sources CTC0 to CTC1 are set. Then, 0 is set to the frequency division of MCLK, and 1 is set to the terminal count of CTC2. Note that R / W is R / W, and the initial value is 0.

  When C0CKCEL is set to 0, CTC0 is counted down with the clock set to C0CKCEL. When C0CKCEL is set to 1, CTC0 is counted down with the terminal count of CTC2. When C1CKCEL is set to 0, CTC1 is counted down with the clock set to C1CKCEL. When C1CKCEL is set to 1, CTC1 is counted down with the terminal count of CTC2.

  Symbols C0CLK are associated with bits 4-5 of memory space address 1001h (I / O space address 01h), and symbols C1CLK are associated with bits 5-4 of memory space address 1002h (I / O space address 02h). The symbols C2CLK are associated with bits 4 to 5 of the memory space address 1003h (I / O space address 03h). In C0CLK, C1CLK, and C2CLK, clock division setting of CTC0 to CTC2 is performed. When MLCK = 20 MHz, 00 is set to 10 μsec, 01 is set to 1 μsec, 10 is set to 5 μsec, and 11 is set to 20 μsec. Note that R / W is R / W, and the initial value is 0.

  CTC2 counts down with the clock set to C2CLK.

  Symbols TMCEL0 are associated with bits 3 to 2 of memory space address 1001h (I / O space address 01h), and symbols TMCEL1 are associated with bits 2 to 3 of memory space address 1002h (I / O space address 02h). Thus, the symbol TMCEL2 is associated with bits 2 to 3 of the memory space address 1003h (I / O space address 03h). In TMCEL0, TMCEL1, and TMCEL2, the fixed values of CTC0 to CTC2 are set. Then, 00 is set to 1 msec (timer value = 03E8h), 01 is set to 2 msec (timer value = 07D0h), 10 is set to 4 msec (timer value = 0FA0h), and 11 is set to 1.490 msec (timer value = 05D1h). Note that R / W is R / W, and the initial value is 0.

  The set time of TMCEL0 to 2 is a predetermined time when the MCLK frequency setting (HSYSCLK) of the system setting (HSYSCNT) of the HW parameter is set to the same frequency as the system clock (MCLK).

  Symbol TMMOD0 is associated with bit 1 of memory space address 1001h (I / O space address 01h), and symbol TMMOD1 is associated with bit 1 of memory space address 1002h (I / O space address 02h). Symbol TMMOD2 is associated with bit 1 of address 1003h (I / O space address 03h). In TMMOD0, TMMOD1, and TMMOD2, the operation modes of CTC0 to CTC2 are set. At 0, the one-shot timer mode is set, and at 1, the interval timer mode is set. Note that R / W is R / W, and the initial value is 0.

  Bit 0 of memory space address 1001h (I / O space address 01h) is associated with symbol TMFVM0, and bit 0 of memory space address 1002h (I / O space address 02h) is associated with symbol TMFVM1 and memory space. Bit 1 of address 1003h (I / O space address 03h) is associated with symbol TMFVM2. In TMFVM0, TMFVM1, and TMFVM2, the timer value setting method of CTC0 to CTC2 is set. Then, 0 is set to an arbitrary value, and 1 is set to a fixed value. Note that R / W is R / W, and the initial value is 0.

  When 0 is set in TMFVM0-2, the settings of TMCEL0-2 are invalid. When 1 is set in TMFVM0 to 2, settings of C0CKSEL, C1CKSEL, C0CLK, C1CLK, and C2CLK are invalid. At this time, the timer value of CTC0-2 is set to any one of 03E8h, 07D0h, 0FA0h, 05D1h and the clock frequency is 1 μsec depending on the setting value of TMSEL0-2. Note that the set values of the C0CLK, C1CLK, C2CLK, and CTC data registers (CTC0 to CTC2) are not affected.

[CTC data register]
Next, the CTC control register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 28, in the CTC control register, bits 7 to 0 of the memory space address 1004h (I / O space address 04h) are associated with the symbol CTC0 (lower order), and the memory space address 1005h (I / O space). Symbols CTC0 (upper order) are associated with bits 7-0 of address 05h). In CTC0, the timer value of CTC0 is set. When reading, the count value is read. In the case of writing, the value written to 65,536, 0001h to 1 in 0000h, and 1 to 1 thereafter increases, and 65,535 is written to FFFFh. Note that R / W is R / W, and the initial value is FFFFh.

  Symbols CTC1 (lower order) are associated with bits 7-0 of memory space address 1006h (I / O space address 06h), and symbols CTC1 are assigned to bits 7-0 of memory space address 1007h (I / O space address 07h). (Upper) is associated. In CTC1, the timer value of CTC1 is set. In addition, CTC1 is the same as CTC0.

  Symbols CTC2 (lower order) are associated with bits 7-0 of memory space address 1008h (I / O space address 08h), and symbols CTC2 are assigned to bits 7-0 of memory space address 1009h (I / O space address 09h). (Upper) is associated. In CTC2, the timer value of CTC2 is set. In addition, CTC2 is the same as CTC0.

  As described above, the timer values CTC0 to CTC2 are set in the CTC data register. When 0000h is set, 65,536 is set. When 1 (fixed value) is set in TMFVM0 to 2 of the CTC control registers (TMCNT0 to 2), this register is unnecessary.

  Further, the count values of CTC0 to CTC2 can be read from this register. Even when 1 (fixed value) is set in TMFVM0 to 2 in the CTC control registers (TMCNT0 to 2), the count value can be read. The count value is read after the CTC is activated.

  When the count value is read using a 2-byte read command, the count value being updated is not read. When the high-order and low-order are read separately by a 1-byte read command, the count value may be updated halfway.

[Watchdog timer (WDT)]
The watchdog timer (WDT) can quickly detect an abnormal operation of the program due to noise or the like, and can return to a normal state by generating a WDT reset.

  WDT operates as follows. The WDT can set the time from 0.1 sec to 12.7 sec (when MCLK = 20 MHz) in units of 0.1 μsec by the WDT control register (WDTCNT). If the WDT is not cleared within the set time, a WDT reset occurs and the CPU core and internal functions are reset. If the WDT is not cleared again within the time set from the time when the WDT is cleared, a WDT reset will occur, so it is necessary to continue to clear the WDT.

  If a WDT reset occurs, the cause can be confirmed by an external signal input / reset factor register (PINSTS). WDT is initialized when a system reset occurs.

  WDT is activated when the same value is set twice in succession in the WDT control register (WDTCNT). Once activated, it cannot be stopped and the set value of WDTCNT cannot be changed.

  As shown in FIG. 29, there are a simple clear mode and a cyclic clear mode for clearing WDT. In the simple clear mode, WDT is cleared by setting 18h in the WDT clear register (WDTCLLR0) in addition to the set time. Thereafter, 18h is repeated in WDTCL0 other than the set time. In the cyclic clear mode, the WDT is cleared by setting 60h in the WDT clear register (WDTCLR1) within the first set time. Within the next set time, the WDT clear register (WDTCLR2) is set to 03h to clear the WDT, and within the next set time, the WDT clear register (WDTCLR3) is set to 24h to clear the WDT. Thereafter, this order setting is repeated. If a different order or a different value is set, the WDT is not cleared and does not affect the operation of the WDT.

[WDT control register]
Next, the CTC control register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 30, in the WDT control register, the symbol WDTND is associated with bit 7 of the memory space address 100Ah (I / O space address 0Ah). In WDTND, the clear mode is set. At 0, the simple clear mode is set, and at 1, the circular clear mode is set. Note that R / W is R / W, and the initial value is 0.

  Symbols WDT are associated with bits 6 to 0 of memory space address 100Ah (I / O space address 0Ah). In WDT, timer setting is performed. When MCLK = 20 MHz, WDT can be stopped at 00h, 0.1 μsec can be set as the minimum value at 01h, and 12.7 sec can be set as the maximum value at 7Fh. Note that R / W is R / W, and the initial value is 0.

  When WDTCNT is set, the same value is set twice within 15 μsec (when MCLK = 20 MHz). WDTCNT cannot be changed once set. If 00h is set twice continuously in WDTCNT, WDT will not start. Even if 00h is continuously set twice after starting WDT, WDT cannot be stopped.

[WDT clear register]
Next, the WDT clear register in the internal function register shown in FIG. 24 will be described with reference to FIG.

  As shown in FIG. 31, in the WDT clear register, the symbol WDTCLLR0 is associated with bits 7 to 0 of the memory space address 1008h (I / O space address 08h). In WDTCL0, simple clear mode WDT clear is set. And it is set to 18h. R / W is W.

  The symbol WDTCLR1 is associated with bits 7 to 0 of the memory space address 1009h (I / O space address 09h). In WDTCLR1, setting of WDT clear in the circulation clear mode is performed. And it is set to 60h. R / W is W.

  Symbols WTCLR2 are associated with bits 7 to 0 of the memory space address 100Dh (I / O space address 0Dh). In WDTCLR2, the WDT clear setting in the circulation clear mode is performed. And it is set to 03h. R / W is W.

  Symbols WTCLR2 are associated with bits 7 to 0 of the memory space address 100Eh (I / O space address 0Eh). In WDTCLR3, setting of WDT clear in the circulation clear mode is performed. And it is set to 24h. R / W is W.

  The order of WDT clear (60h → 03h → 24h) in the circulation clear mode is maintained when a WDT reset occurs. It is initialized when a system reset occurs.

[Interrupt controller]
Next, the interrupt controller will be described. FIG. 32 is a block diagram of the interrupt controller.

  As an interrupt operation, first, an interrupt factor and an interrupt are set.

Interrupt factors include the input signal of the interrupt input / general-purpose input terminal (INP) and the terminal count of CTC0 to 2. Interrupts are generated in the following cases.
1. 1. When INP terminal becomes L level 2. When CTC0 reaches the terminal count 3. When CTC1 reaches the terminal count When CTC2 reaches the terminal count

  When the INP terminal is used as an interrupt input signal, 1 (used as an interrupt input terminal) is set in the HW parameter reset period / INP terminal function setting (HPORTTEN) of the INP terminal setting (HRSTCNT).

  The INP terminal can select INT interrupt input or NMI interrupt input by setting the interrupt input terminal (HPORTMD) of HRSTCNT.

  The four interrupt factors can be individually set to enable or disable interrupts by an interrupt enable register (IER). Also, the interrupt priority can be set by the interrupt priority register (IPR).

  Interrupts other than NMI are allowed to accept and forbid interrupt requests independently of the interrupt controller by the interrupt master permission flag (IMF) assigned to the program status word (PSW) of the CPU core. Can be set.

  The IMF is set by an EI (IMF = 1) command and DI (IMF = 0).

  When the CPU core is in the interrupt permission state (IMF = 1), the interrupt controller outputs an interrupt request signal to the CPU core.

  In the case of an NMI interrupt, an interrupt request signal is output to the CPU core regardless of the interrupt enabled / disabled state.

  The interrupt request register (IRR), the interrupt permission register (IER), and the interrupt priority register (IPR) are initialized when a system reset or a WDT reset occurs.

The interrupt process is started in the next step.
1. When an interrupt occurs, the interrupt factor is latched in the interrupt request register (IRR).
2. An interrupt request signal is output to the CPU core according to the setting state of IER, IPR, and IMF.
3. The CPU core determines whether or not there is an interrupt request during the M1 cycle.
4). When there is an interrupt request, the instruction fetched in the M1 cycle is discarded and the program counter (PC) is not updated. Since this PC is pushed onto the stack at “8.” below, the execution of the program is resumed from this PC at the end of the interrupt process. While the LDIR and CPIR instructions are being executed, there are M1 cycles each time the process is repeated. In this case as well, the presence / absence of an interrupt request is similarly determined.
5. M1 and IPEQ0 are simultaneously set to L level, indicating that the CPU core has accepted the interrupt.
6). Clear the bit corresponding to the interrupt factor of IRR to 0.
7). The start address of the interrupt process corresponding to the interrupt factor is read from the interrupt process vector table.
8). Push PSW, PC upper byte (PCH), PC lower byte (PCL) in this order.
9. Clear IMF to 0 and disable interrupts.
10. The address read from the interrupt processing vector table is set in the PC counter.
11. Start interrupt processing.
The above processing is for the case where the interrupt request is an INT interrupt and CTC 0 to 2 interrupts. In the case of an NMI interrupt, an interrupt request signal is output regardless of the settings of IER, IPR, and IMF.

  PSW and PC are automatically saved to the stack during interrupt acceptance processing, but general-purpose registers (W, A, B, C, D, E, H, L, IX, IY) of the CPU core are automatically saved. Not. Evacuate by program if necessary.

  Note that. General-purpose registers can be saved by a PUSH instruction or by switching the general-purpose register banks. For example, in a system in which interrupt processing does not start multiple times, the normal processing uses bank 0 of the general-purpose register, executes the LD, RBS, 1 (RBS = 1) instruction at the top of the interrupt processing n, By switching to 1, the bank 0 register can be saved.

  Since the register bank selector (RBS) is included in the PSW, when the interrupt processing return instruction (RETI or RETN) is executed, the PSW returns from the stack and automatically switches to the bank 0.

  The end of the interrupt process does not require any special measures other than the execution of the return instruction (RETI or RETN). When the return instruction is executed, PSW and PC are returned from the stack, and the process returns to the process before starting the interrupt process. The interrupt controller clears the interrupt factor automatically when an interrupt request is received. Since IMF and RBS are included in PSW, they are automatically returned from the stack by a return instruction. Therefore, there is no need to execute an EI command or RBS switching before the end of the interrupt process.

  Since an interrupt can be accepted as soon as the EI instruction is executed, if an EI instruction and a return instruction are described consecutively, a new interrupt may be accepted when the return instruction is fetched.

FIG. 33 shows an example of an interrupt process procedure when an interrupt process is executed by CTC0. The details of the example of FIG. 33 are as follows.
1. In the main routine, bank 0 (RBS = 0) of general-purpose registers is used.
2. The CTC0 interrupt routine uses bank 1 (RBS = 1) of general purpose registers.
3. The end of the interrupt process is only the execution of RETI.

[Interrupt request register]
Next, the interrupt request register in the internal function register shown in FIG. 24 will be described with reference to FIG. The interrupt request register is a register that latches an interrupt request signal.

  As shown in FIG. 34, in the interrupt request register, symbol IRR3 is associated with bit 7 of memory space address 1023h (I / O space address 23h). In IRR3, a CTC2 interrupt request is set. In the case of reading, the interrupt request is set without 0 when it is 0, and the interrupt request is set when 1. In the case of writing, when it is 0, it is set to clear, and when it is 1, it is set to do nothing. Note that R / W is R / W, and the initial value is 0.

  Bit 6 of memory space address 1023h (I / O space address 23h) is associated with symbol IPR2. In IRR2, a CTC1 interrupt request is set. In other respects, IRR2 is similar to IRR3.

  Bit 5 of memory space address 1023h (I / O space address 23h) is associated with symbol IPR1. In IRR1, a CTC0 interrupt request is set. In other respects, IRR1 is similar to IRR3.

  Bit 4 of memory space address 1023h (I / O space address 23h) is associated with symbol IPR0. In IRR0, an INT / NMI interrupt request is set. In addition, IRR0 is the same as IRR3.

  Bits 3 to 30 of the memory space address 1023h (I / O space address 23h) are unused and are always 0. Note that R / W is R and the initial value is 0.

  When the CPU core accepts an interrupt request, the interrupt controller automatically clears to zero. If 0 is set, it can be cleared, but even if 1 is set, an interrupt request cannot be set.

  Since the IRR is located in the preceding stage of the interrupt permission register (IER), even if the interrupt factor is set to disable interrupt by the IER, it is latched. When ignoring an interrupt request that occurs while interrupts are prohibited, set the IRR to 0 before clearing the interrupts to clear the interrupt request.

[Interrupt enable register]
Next, the interrupt permission register in the internal function register shown in FIG. 24 will be described with reference to FIG. The interrupt permission register is a register that permits an interrupt request signal.

  As shown in FIG. 35, in the interrupt permission register, symbol IER3 is associated with bit 7 of memory space address 1024h (I / O space address 24h). In IER3, CTC2 interrupt permission is set. When it is 0, it is set to disable interrupts, and when it is 1, it is set to enable interrupts. Note that R / W is R / W, and the initial value is 0.

  Bit 6 of memory space address 1024h (I / O space address 24h) is associated with symbol IER2. In IER2, CTC1 interrupt permission is set. Otherwise, IER2 is the same as IER3.

  Bit 5 of memory space address 1024h (I / O space address 24h) is associated with symbol IER1. In IER1, CTC0 interrupt permission is set. In addition, IER1 is the same as IER3.

  Symbol 4 is associated with bit 4 of memory space address 1024h (I / O space address 24h). In IER0, setting of INT interrupt permission is performed. Otherwise, IER0 is the same as IRR3.

  Bits 0 to 3 of the memory space address 1024h (I / O space address 24h) are unused and are always 0. Note that R / W is R and the initial value is 0.

  Note that if an interrupt is permitted with the interrupt request signal latched in the interrupt request register (IER), the interrupt request signal is immediately output to the CPU core.

[Interrupt priority register]
Next, the interrupt permission register in the internal function register shown in FIG. 24 will be described with reference to FIG. The interrupt priority order register is a register for setting the priority order of interrupt factors (INT, CTC0, CTC1, CTC2).

  As shown in FIG. 36, in the interrupt priority register, the symbol IPR3 is associated with bits 7 to 6 of the memory space address 1025h (I / O space address 25h). In IPR3, the CTC2 priority order is set. At 00, the lowest priority level 0 is set. Further, in the case of 01, the level 1 is set to a priority level higher than 00 and lower priority level than 10. When the priority is 10, level 2 is set higher than 01 and lower than 11. In addition, when it is 11, the highest priority level 3 is set. Note that R / W is R / W, and the initial value is 0.

  The symbols IPR2 are associated with bits 5 to 4 of the memory space address 1025h (I / O space address 25h). In IPR2, the CTC1 priority is set. In addition, IPR2 is the same as IPR3.

  Symbols IPR1 are associated with bits 3 to 2 of the memory space address 1025h (I / O space address 25h). In IPR1, the CTC0 priority is set. In addition, IPR1 is the same as IPR3.

  Symbol IPR0 is associated with bits 1 to 0 of memory space address 1025h (I / O space address 25h). In IPR0, the INT priority is set. In addition, IPR0 is the same as IPR3.

  When a plurality of interrupt factors are generated at the same time, an interrupt factor having a higher priority outputs an interrupt request signal to the CPU core. There are four priorities, level 3 is the highest and level 0 is the lowest. If the level is the same, INT, CTC0, CTC1, and CTC2 are in descending order of priority.

[External signal input / reset source register]
Next, the interrupt permission register in the internal function register shown in FIG. 24 will be described with reference to FIG. The external signal input / reset factor register can know the state of the interrupt input / general-purpose input terminal (INP) and the random number external latch 0-2 terminals (EXLATCH0-2) and the reset generation factor.

  As shown in FIG. 37, in the external signal input / reset cause register, symbol WDTRST is associated with bit 7 of memory space address 1026h (I / O space address 26h). In WDTRST, WDT reset generation is set. In the case of reading, it is set that it does not occur when 0, but occurs when 1. In the case of writing, it is set to clear when 0 and do nothing when 1. Note that R / W is R / W, and the initial value is 0.

  Symbol 6 is associated with bit 6 of memory space address 1026h (I / O space address 26h). In IARST, the occurrence of illegal reset is set. Otherwise, IARST is the same as WDTRST.

  Symbol INTRST is associated with bit 5 of memory space address 1026h (I / O space address 26h). In INTRST, the occurrence of a periodic reset is set. In addition, INTST is the same as WDTRST.

  Bit 4 of the memory space address 1026h (I / O space address 26h) is unused and is always 0. Note that R / W is R and the initial value is 0.

  Symbol INPS is associated with bit 3 of memory space address 1026h (I / O space address 26h). In INPS, an INP terminal number is set. When 0, terminal number = L is set, and when 1, terminal number = R is set. R / W becomes R.

  Symbol LTC2 is associated with bit 2 of memory space address 1026h (I / O space address 26h). In LTC2, the EXLATCH2 terminal number is set. In addition, LTC2 is the same as INPS.

  The symbol LTC1 is associated with bit 1 of the memory space address 1026h (I / O space address 26h). In LTC1, the EXLATCH1 terminal number is set. In addition, LTC1 is the same as INPS.

  Symbol LTC0 is associated with bit 0 of memory space address 1026h (I / O space address 26h). In LTC0, the EXLATCH0 terminal number is set. In addition, LTC0 is the same as INPS.

  Note that the status of the corresponding reset factor is set in WDTRST, IARST, and INTRST. WDTRST, IARST, and INTRST are held until a system reset occurs, and are cleared to 0 after the system reset. Set 0 to clear WDTRST, IARST, and INTRST.

  In INPS, LTC2, LTC1, and LTC0, the signal level of the corresponding terminal is set as it is. INPS is set to the signal level of the INP terminal regardless of the setting state of the reset period of the HW parameter / INP terminal function setting (HPORTTEN) of the INP terminal setting (HRSTCNT).

  A noise filter having a CPU clock of 5 clocks is inserted into the INP terminal. A noise filter of 128 clocks with a random number clock is inserted into the EXLATCH 0 to 2 terminals. Accordingly, 0 (or 1) is set when a continuous L level signal (or H level signal) of 5 clocks or 128 clocks is input.

  PINTTS is initialized when a system reset occurs.

[Random number operation]
As the random number circuit, an 8-bit fixed-length random number circuit, a 16-bit fixed-length random number circuit, an 8-bit variable-length random number circuit, and a 16-bit variable-length random number circuit are provided. The start value for the first week after the system reset is updated each time the system is reset. The pattern of the random number sequence is automatically updated. A 16-bit fixed-length random number can transpose the bit sequence. For the 16-bit fixed-length random number, the operation clock can be selected from 1/2 of MCLK or 1/2 of EXCLK. A random number value can be latched by three random number external latch terminals. Equipped with a function to judge abnormality of random number circuit.

  The 8-bit fixed-length random number circuit and the 16-bit fixed-length random number circuit are automatically activated after a system reset or a WDT reset. The 8-bit variable length random number circuit and the 16-bit variable length random number circuit are stopped after a system reset or WDT reset, and are activated when a maximum value is set. The random number circuit is initialized by a system reset or a WDT reset. When a periodic reset or illegal access reset occurs, the operation continues without affecting the random number function.

  The random number circuit updates the random value while taking discrete values using the initial value as a start value, and causes all the values to appear once without overlapping. After all values appear, another value is used as a start value, the appearance pattern of the sequence is changed to another pattern, and all values are updated again while taking discrete values.

  The random value is updated at the rising edge of the random number clock (1/2 of MCLK or 1/2 of EXCLK). The random number value can be latched by a signal input to the random number external latch 0-2 terminals (EXLATCH0-2).

  Holding or updating the latch data register can be set by the external latch signal mode register (RDEXLM). When RDEXLM is set to 0 (hold), a random value is latched in the random number latch data register only when a signal is input to EXLATCH 0 to 2 with the random number latch data register being cleared. When there is latch data in the random number latch data register, a signal is input to EXLATCH 0 to 2, the random number latch data register is not updated, and the latch data up to that point is held. When RDEXLM is set to 1 (update), the latch data is updated each time a signal is input to EXLATCH0-2.

[Periodic reset monitor register]
Next, the periodic reset monitor register in the internal function register shown in FIG. 24 will be described with reference to FIG. The periodic reset monitor can read the value of the periodic reset timer counter.

  As shown in FIG. 38, in the periodic reset monitor register, the symbol ITRMN is associated with bits 7 to 0 of the memory space address 1094h (I / O space address 94h). In ITRMN, a periodic reset monitor is set. And it is set to any one of 00h to FFh. In addition, R / W is R and the initial value is 0.

  The periodic reset is operated by the periodic reset setting (HPRST) of the HW parameter. The periodic reset counter is initialized to 00h by a system reset or a WDT reset, and is up-counted by a periodic reset clock. The periodic reset counter value can be read from the periodic reset monitor register (ITRMN).

[Register configuration]
Next, the register configuration will be described.

[About general-purpose registers]
As shown in FIG. 39, two register banks including bank 0 and bank 1 are provided as register banks. Each register bank includes eight 8-bit general-purpose registers W, A, B, C, D, E, H, and L, and two 16-bit general-purpose registers IX and IY. W, A, B, C, D, E, H, and L are used for 8-bit transfer and calculation. These registers can be combined and used as WA, BC, DE, and HL. WA, BC, DE, HL, IX, and IY can be used for 16-bit transfer and computation. The general-purpose register is initialized to 00h or 0000h at the time of system reset, WDT reset, periodic reset, and illegal access reset.

[Program status word (PSW)]
Next, the PSW shown in FIG. 39 will be described with reference to FIG. The PSW is a register that holds the state of the operation result and execution result of the instruction, and includes eight types of flags. The PSW is cleared to 00h at the time of system reset, WDT reset, periodic reset, and illegal access reset in accordance with the initialization with the CPU core described above.

  As shown in FIG. 40, in PSW, a symbol JF (jump status flag) is associated with bit 7. JF is a flag used in a 1-byte JRS instruction or the like. As shown in the example in the figure, there are cases where a zero flag is set and a carry flag is set depending on an instruction. Also, as shown in the example in the figure, in the case of INC and DEC instructions, the carry flag does not change, but the jump status flag is set under the condition that the carry flag is set.

  Also, ZF (zero flag) is associated with bit 6. ZF is set to 1 when the operation result or transfer data is 00h (for 8 bits) or 0000h (for 16 bits), and cleared to 0 in other cases. In the exchange command (XCH dst, src), it is set when the value stored in dst is 0.

  Also, CF (carry flag) is associated with bit 5. In CF, carry or borrow at the time of calculation is set. In the case of a division instruction, 1 is set when the division by 0 or the division result is 0100h or more. In the case of INC and DEC instructions, even when a carry or a borrow occurs, the carry flag does not change and holds the value.

  In addition, HF (half carry flag) is associated with bit 4. HF is set to carry or borrow to the fourth bit during 8-bit operation.

  Also, SF (sign flag) is associated with bit 3. SF is set to 1 when the MBS of the operation result is 1, and cleared to 0 otherwise.

  Also, VF (overflow flag) is associated with bit 2. VF is set to 1 when an overflow occurs in the operation result, and cleared to 0 at other times.

  Also, RBS (register bank selector) is associated with bit 1. RBS indicates the bank selected by the general-purpose register.

  Also, IMF (interrupt master permission flag) is associated with bit 0. The IMF becomes IMF = 0 by the DI command, and acceptance of maskable interrupts is prohibited. With the EI command, IMF = 1 and acceptance of maskable interrupts is permitted.

[Stack pointer (SP)]
Next, the SP shown in FIG. 39 will be described with reference to FIG. SP is a 16-bit register indicating the top address of the stack.

  As shown in FIG. 41, it is post-decremented when a PUSH instruction, a subroutine call, an interrupt is accepted, and pre-incremented when a POP instruction or a return instruction. At the time of a subroutine call (CALL instruction, CALLV instruction), PUSH is performed in order of higher and lower return addresses. When an interrupt is accepted, the push is performed in the order of program status word, return address upper order, and lower order. The SP is initialized to 01FFh at the time of system reset, WDT reset, periodic reset, and illegal access reset.

[Program counter (PC)]
Next, the PC shown in FIG. 39 will be described. This is a 16-bit register indicating an address where an instruction to be executed next is stored. It is initialized to 8000h by system reset, WDT reset, periodic reset, and illegal access reset. After the system reset, WDT reset, periodic reset, and illegal access reset are released, program execution starts from address 8000h.

[Summary of operation when the microcomputer starts]
In the microcomputer configured as described above, when power is supplied and reset signals are input from the reset circuit 49 and the reset circuit 95, the system is reset.

  By this system reset, each function of the microcomputer performs the operation described as a change in operation due to a reset factor (see FIG. 23). For example, the CPU core is initialized and the PSW is cleared to 00h accordingly. Therefore, IMF becomes 0, and the interrupt prohibited state is set. In addition, initial values are set in internal function registers (CTC control registers, registers related to random number circuits, etc.) in which system reset is defined as an initialization factor (see FIG. 24).

  Further, various functions are set with reference to the HW parameters (see FIG. 14). Here, in the HW parameter, it is determined whether or not a condition that the microcomputer does not start (see FIG. 22) is satisfied. If the condition is satisfied, the microcomputer does not start.

  Thereafter, after the set system reset time has elapsed, the initial setting process shown in FIGS. 5 and 6 is executed according to the user program (the program stored in “program / data” in FIG. 12).

[Modification]
In the above embodiment, the power interruption process is executed in the timer interrupt process (main) shown in FIGS. 8 and 9, but the power interruption process may be executed by an NMI interrupt (non-maskable interrupt).

  In this case, when an interrupt request signal is input, an NMI interrupt is generated regardless of the interrupt enabled / disabled state, and the power interruption process is executed. In the power interruption process, first, the interrupt permission / prohibition state immediately before the power interruption is backed up and set to interrupt prohibition. Next, processing similar to the power interruption processing (main) shown in FIG. 10 is executed. When the microcomputer is started and the initial setting process is executed, the process of Sa17 in FIG. 6 is not performed, and the interrupt enable / disable state is restored based on the interrupt enable / disable state when the power is turned off. Let

  When the power interruption process is executed as described above, if the value set in the vector table shown in FIG. 13 is a value other than 0000h and 8000h to HPRGEND, the microcomputer is used if the start-up condition shown in FIG. 22 is satisfied. Restrict startup of. That is, if the INT / NMI values at the addresses A7A0h to A7A1h in the vector table are values other than 0000h and 8000h to HPRGEND, the microcomputer activation is limited when the non-activation condition shown in FIG. 22 is satisfied. Thereby, it is possible to prevent an unintentional non-maskable interrupt process from being performed.

  In this modification, the timer interrupt processing (main) generation condition is satisfied during a period (for example, 3 cycles) from when the NMI interrupt request signal is input until the NMI interrupt is generated. It is shorter than a period (for example, 4 cycles) from when the timer interrupt occurs. For this reason, a power interruption process can be performed suitably.

  In addition, although this modification gave the example implemented in a power interruption process (main) and an initial setting process, it implemented in the power interruption process (sub) and initial setting process (sub) which the sub control part 91 performs. Also good.

[Effect of the above embodiment]
In the above embodiment, the interrupt is permitted after the timer interrupt is set in the initial setting process, and when the value set in the vector table is a value other than 0000h and 8000h to HPRGEND, the start of the microcomputer is limited ( In this example, the portions shown in FIGS. 5, 6, and 22).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the above embodiment, even if CTC is counting, if TMCNT0-2 is set, it is updated with the setting contents of CTC0-2 and TMCNT0-2, and the timer value being counted is decreased again from the setting value of CTC0-2. Count (in this example, the portion shown in FIGS. 27 and 28).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the above embodiment, when the system reset is performed and the interrupt controller is initialized, initial values are set in the interrupt request register, the interrupt permission register, and the interrupt priority register (in this example, FIG. 23). And the portion shown in FIG. 32).
Therefore, it is possible to prevent the interruption process from being executed with unintended settings in advance.

In the above embodiment, when the function of the program end address is used, when the symbol is HPRGEND, and the setting content is the program end address, when the access to the area of HPRGEND1 to A6FFh is made illegal An access reset occurs. (In this example, the part shown in FIG. 21).
Therefore, execution of an illegal program can be prevented.

In the above embodiment, in the initial setting process, the interrupt is prohibited before the timer interrupt is set (in this example, the process of Sa1 in FIG. 5).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the above embodiment, HEDMD bit 3 = 1 in the random number circuit operation mode setting (related symbol name: HRDMD) or HSYSCNT bit 5 = 1 and HSYSCNT bit 6 in the system setting (related symbol name: HSYSCNT). = 1 and HSYSCNT bit 7 = 1, the activation of the microcomputer is limited (in this example, the portion shown in FIG. 22).
Therefore, unintended settings can be prevented in advance.

In the above embodiment, interrupts are permitted after the random number generation circuit is set in the initial setting process, and when the values set in the vector table are values other than 0000h and 8000h to HPRGEND, the activation of the microcomputer is limited ( In this example, the portions shown in FIGS. 5, 6, and 22).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the above embodiment, when RDEXLM is set to 0 (hold), a random value is latched in the random number latch data register only when a signal is input to EXLATCH 0 to 2 in a state where the random number latch data register is cleared. When 1 (update) is set in RDEXLM, the latch data is updated each time a signal is input to EXLATCH 0 to 2 (in this example, the portion shown in [Random number operation]).
Therefore, it is possible to prevent an unintended random value from being taken in.

In the above embodiment, when the system reset is performed and the random number circuit is initialized, initial values are set in the registers related to the random number circuit (in this example, the portion shown in FIG. 23).
Therefore, it is possible to prevent the numerical data that becomes a random value from being set unintentionally.

In the above embodiment, interrupts are prohibited during the initial setting process, and when the values set in the vector table are values other than 0000h and 8000h to HPRGEND, the activation of the microcomputer is limited (in this example, FIG. 5 and FIG. 5). 6, part shown in FIG.
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the above-described embodiment, any one of initializations 1 to 4 is selected and executed according to the initialization condition (in this example, a portion indicated by “About initialization”).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the above-described embodiment, interrupt prohibition is set before the output port is initialized (in this example, interrupt prohibition is executed before Sm3 in FIG. 10).
Therefore, it is possible to prevent unintended data from being output.

In the above embodiment, the interrupt enable / disable state at the time of power interruption is backed up in the power interruption process and the interrupt enable / disable state at the time of power interruption is restored by the initial setting process, and the value set in the vector table is 0000h, In the case of a value other than 8000h to HPRGEND, the activation of the microcomputer is restricted (in this example, [Modified Example], a portion shown in FIG. 22).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the above embodiment, the microcomputer is restricted from starting when the INT / NMI values at addresses A7A0h to A7A1h in the vector table are values other than 0000h and 8000h to HPRGEND (in this example, [Modification], FIG. 22). Part shown in).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the above embodiment, the period from when the NMI interrupt signal is input until the NMI interrupt is generated is longer than the period from when the timer interrupt processing (main) generation condition is satisfied until the timer interrupt is generated. (In this example, the portion shown in [Modification]).
Therefore, the power interruption process can be suitably executed.

[Other variations]
In the above embodiment, the example in which the present invention is applied to the initial setting process, the timer interrupt process (main), and the power interruption process (main) by the main control unit 41 has been described. ), Timer interruption processing (sub), power interruption processing (sub) may be applied.

  [About gaming machines]

  As described above, in the above embodiment, the slot machine has been described as an example. For example, the configuration described in the above embodiment is applied to a pachinko gaming machine using a game ball, and the claimed invention is applied. Can be realized.

  In the above embodiment, a slot machine that sets wager numbers using medals and credits has been described as an example. However, the present invention is not limited to this, and for example, a game used in a pachinko gaming machine. Claim invention by applying the configuration shown in the above embodiment to a slot machine that uses a ball to set the number of bets or a fully credit type slot machine that uses only credits to set the number of bets Can be realized. When game balls are used as game media, for example, when one medal corresponds to five game balls, and 3 is set as the bet number in the above embodiment, 15 game balls are used. This is equivalent to setting the number of bets using.

  In addition, the gaming machine of the present invention is not limited to one using only one of a plurality of types of gaming values such as medals and gaming balls, but a plurality of types of gaming machines such as medals and gaming balls, for example. The game value may be used together. That is, it is possible to play a game by setting the number of bets using any of a plurality of types of game values such as medals and game balls, and a plurality of types of games such as medals and game balls when a winning occurs. A gaming machine that can pay out any of the utility value is also included in the gaming machine of the present invention.

1 slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 start switch 8L, 8C, 8R stop switch 41 main controller 41a CPU
41b ROM
41c RAM
91 Sub-control unit 91a CPU
91b ROM
91c RAM

Claims (1)

In gaming machines capable of playing games,
Storage means for storing the program;
A microcomputer that executes processing according to a program stored in the storage means,
The program includes an interrupt program that is executed in response to the occurrence of an interrupt,
The microcomputer is
Interrupt setting means for performing an interrupt setting process for setting a time interval at which an interrupt occurs for an interrupt that occurs at a predetermined period;
A timing means for timing the time interval at which the interrupt occurs;
Storage area setting means for setting a storage area in which a user program is stored when the microcomputer is activated;
User program execution means for executing processing according to the user program stored in the storage area set by the storage area setting means;
Abnormality control execution means for executing abnormality control when the user program execution means calls a program stored in an area other than the storage area set by the storage area setting means;
Interrupt permitting means for executing a process for permitting an interrupt after executing the interrupt setting process ;
Interrupt processing execution means for executing processing according to the interrupt program based on the interrupt when the interrupt is permitted;
Address storage means having a storage area capable of storing the address of the interrupt program in the storage means;
Determining means for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
An activation restriction unit for restricting activation of the microcomputer when the determination unit determines that the address of the interrupt program is not within a predetermined range;
The time measuring means starts measuring time from an initial value based on the time interval at which the interrupt is generated by the interrupt setting process,
The gaming machine, wherein the predetermined range includes at least an address of an area where a user program is stored.