JP6827633B2 - 等方性シリコン及びシリコンゲルマニウムの調整可能な選択性を備えたエッチング - Google Patents

等方性シリコン及びシリコンゲルマニウムの調整可能な選択性を備えたエッチング Download PDF

Info

Publication number
JP6827633B2
JP6827633B2 JP2018546013A JP2018546013A JP6827633B2 JP 6827633 B2 JP6827633 B2 JP 6827633B2 JP 2018546013 A JP2018546013 A JP 2018546013A JP 2018546013 A JP2018546013 A JP 2018546013A JP 6827633 B2 JP6827633 B2 JP 6827633B2
Authority
JP
Japan
Prior art keywords
silicon
material layer
substrate
etching
substrate temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018546013A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019507505A5 (enExample
JP2019507505A (ja
Inventor
カル，スバディープ
エヌ．タピリー カンダバラ
エヌ．タピリー カンダバラ
モスデン，エラン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of JP2019507505A publication Critical patent/JP2019507505A/ja
Publication of JP2019507505A5 publication Critical patent/JP2019507505A5/ja
Application granted granted Critical
Publication of JP6827633B2 publication Critical patent/JP6827633B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357—Generation remote from the workpiece, e.g. down-stream
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32715—Workpiece holder
    • H01J37/32724—Temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
JP2018546013A 2016-03-02 2017-03-02 等方性シリコン及びシリコンゲルマニウムの調整可能な選択性を備えたエッチング Active JP6827633B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662302584P 2016-03-02 2016-03-02
US201662302587P 2016-03-02 2016-03-02
US62/302,584 2016-03-02
US62/302,587 2016-03-02
PCT/US2017/020503 WO2017151958A1 (en) 2016-03-02 2017-03-02 Isotropic silicon and silicon-germanium etching with tunable selectivity

Publications (3)

Publication Number Publication Date
JP2019507505A JP2019507505A (ja) 2019-03-14
JP2019507505A5 JP2019507505A5 (enExample) 2020-02-06
JP6827633B2 true JP6827633B2 (ja) 2021-02-10

Family

ID=59744483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018546013A Active JP6827633B2 (ja) 2016-03-02 2017-03-02 等方性シリコン及びシリコンゲルマニウムの調整可能な選択性を備えたエッチング

Country Status (5)

Country Link
US (1) US9984890B2 (enExample)
JP (1) JP6827633B2 (enExample)
KR (1) KR102323389B1 (enExample)
TW (1) TWI625785B (enExample)
WO (1) WO2017151958A1 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6692202B2 (ja) * 2016-04-08 2020-05-13 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US10141189B2 (en) * 2016-12-29 2018-11-27 Asm Ip Holding B.V. Methods for forming semiconductors by diffusion
US10043674B1 (en) * 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10685887B2 (en) * 2017-12-04 2020-06-16 Tokyo Electron Limited Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) device
US10714391B2 (en) * 2017-12-04 2020-07-14 Tokyo Electron Limited Method for controlling transistor delay of nanowire or nanosheet transistor devices
CN112385029B (zh) * 2018-05-08 2025-09-16 朗姆研究公司 包括带有远心透镜的透镜电路、光束折叠组件或多边形扫描仪的原子层蚀刻和沉积处理系统
JP7072440B2 (ja) * 2018-05-16 2022-05-20 東京エレクトロン株式会社 シリコン含有膜のエッチング方法、コンピュータ記憶媒体、及びシリコン含有膜のエッチング装置
KR102894638B1 (ko) * 2018-07-20 2025-12-02 도쿄엘렉트론가부시키가이샤 실리콘-게르마늄 합금의 제어 가능한 에칭 선택도를 가진 기상 에칭
WO2020042254A1 (zh) * 2018-08-28 2020-03-05 中国科学院微电子研究所 一种高精度的刻蚀方法
KR20210055785A (ko) * 2018-10-03 2021-05-17 램 리써치 코포레이션 나노와이어들을 위한 선택적인 에칭
WO2020172208A1 (en) * 2019-02-20 2020-08-27 Tokyo Electron Limited Method for selective etching at an interface between materials
US10892158B2 (en) * 2019-04-01 2021-01-12 Hitachi High-Tech Corporation Manufacturing method of a semiconductor device and a plasma processing apparatus
US11257680B2 (en) 2019-08-28 2022-02-22 Mattson Technology, Inc. Methods for processing a workpiece using fluorine radicals
JP7345334B2 (ja) 2019-09-18 2023-09-15 東京エレクトロン株式会社 エッチング方法及び基板処理システム
JP7257543B2 (ja) * 2019-10-29 2023-04-13 東京エレクトロン株式会社 基板処理方法、基板処理装置及びナノワイヤ又はナノシートのトランジスタの製造方法
WO2021181768A1 (ja) * 2020-03-10 2021-09-16 パナソニックＩｐマネジメント株式会社 電子部品のクリーニング方法および素子チップの製造方法
JP7360979B2 (ja) * 2020-03-19 2023-10-13 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US11424120B2 (en) * 2021-01-22 2022-08-23 Tokyo Electron Limited Plasma etching techniques
US11482423B2 (en) 2021-01-28 2022-10-25 Tokyo Electron Limited Plasma etching techniques
JP7771835B2 (ja) * 2021-05-31 2025-11-18 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JP2022191045A (ja) * 2021-06-15 2022-12-27 東京エレクトロン株式会社 エッチング方法及びエッチング装置
JP7320135B2 (ja) * 2021-06-17 2023-08-02 株式会社日立ハイテク プラズマ処理方法および半導体装置の製造方法
FR3125915A1 (fr) * 2021-10-07 2023-02-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de gravure selective isotrope de silicium
US12272558B2 (en) * 2022-05-09 2025-04-08 Tokyo Electron Limited Selective and isotropic etch of silicon over silicon-germanium alloys and dielectrics; via new chemistry and surface modification
US12261053B2 (en) * 2022-08-10 2025-03-25 Tokyo Electron Limited Substrate processing with selective etching
WO2024058881A1 (en) * 2022-09-15 2024-03-21 Tokyo Electron U.S. Holdings, Inc. Surface modification to achieve selective isotropic etch
US20240321584A1 (en) * 2023-03-22 2024-09-26 Applied Materials, Inc. Selective oxidation processes for gate-all-around transistors
CN116741630B (zh) * 2023-08-14 2023-12-22 北京北方华创微电子装备有限公司 干法刻蚀方法和半导体工艺设备
WO2025128543A1 (en) * 2023-12-15 2025-06-19 Lam Research Corporation Tunable selective lateral etch of silicon using radical species

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858532B2 (en) * 2002-12-10 2005-02-22 International Business Machines Corporation Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling
KR100670782B1 (ko) * 2004-11-09 2007-01-17 한국전자통신연구원 상변화 메모리 소자의 제조방법
JP2007056336A (ja) * 2005-08-25 2007-03-08 Tokyo Electron Ltd 基板処理装置，基板処理装置の基板搬送方法，プログラム，プログラムを記録した記録媒体
JP2007266455A (ja) * 2006-03-29 2007-10-11 Tokyo Electron Ltd 基板処理装置、基板処理方法及び記憶媒体
MY149190A (en) 2006-09-20 2013-07-31 Univ Illinois Release strategies for making transferable semiconductor structures, devices and device components
US20110061810A1 (en) * 2009-09-11 2011-03-17 Applied Materials, Inc. Apparatus and Methods for Cyclical Oxidation and Etching
US20120083127A1 (en) * 2010-09-30 2012-04-05 Tokyo Electron Limited Method for forming a pattern and a semiconductor device manufacturing method
KR101244953B1 (ko) * 2011-07-18 2013-03-18 (재)한국나노기술원 전류 저지층 구조의 수직형 발광다이오드 소자 및 그 제조방법
US8808563B2 (en) * 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US20140273525A1 (en) 2013-03-13 2014-09-18 Intermolecular, Inc. Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films
US9576809B2 (en) * 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9577100B2 (en) 2014-06-16 2017-02-21 Globalfoundries Inc. FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
US9613822B2 (en) * 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement

Also Published As

Publication number Publication date
WO2017151958A1 (en) 2017-09-08
US20170271165A1 (en) 2017-09-21
TWI625785B (zh) 2018-06-01
TW201738955A (zh) 2017-11-01
US9984890B2 (en) 2018-05-29
JP2019507505A (ja) 2019-03-14
KR102323389B1 (ko) 2021-11-05
KR20180112869A (ko) 2018-10-12

Similar Documents

Publication Publication Date Title
JP6827633B2 (ja) 等方性シリコン及びシリコンゲルマニウムの調整可能な選択性を備えたエッチング
TWI579892B (zh) 用以形成具有多膜層的間隔壁之蝕刻方法
KR102204711B1 (ko) 산화물 및 질화물 재료들을 선택적으로 에칭하는 기술들 및 이를 사용하여 형성된 제품들
US11658037B2 (en) Method of atomic layer etching of oxide
JP2019507505A5 (enExample)
JP2004336029A (ja) 電界効果トランジスタのゲート構造の製造方法
CN112956000A (zh) 经硼掺杂的非晶形碳硬掩模及方法
KR102534100B1 (ko) 실리콘의 화학적 에칭을 위한 방법들
CN109427559A (zh) 半导体器件及其形成方法
US11227767B2 (en) Critical dimension trimming method designed to minimize line width roughness and line edge roughness
JP2024505507A (ja) プラズマエッチング技法
US9773649B2 (en) Dry development and image transfer of si-containing self-assembled block copolymers
US12315733B2 (en) Enhanced etch selectivity using halides
US10699911B2 (en) Method of conformal etching selective to other materials
JPWO2021225790A5 (enExample)
TWI630655B (zh) Dry etching method
TW202121527A (zh) 以多色選擇性非等向性蝕刻相鄰線的方法
KR20190097560A (ko) 실리콘의 원자층 에칭 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191218

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191218

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20201117

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20201215

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20201215

R150 Certificate of patent or registration of utility model

Ref document number: 6827633

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250