JP6787367B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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JP6787367B2
JP6787367B2 JP2018117316A JP2018117316A JP6787367B2 JP 6787367 B2 JP6787367 B2 JP 6787367B2 JP 2018117316 A JP2018117316 A JP 2018117316A JP 2018117316 A JP2018117316 A JP 2018117316A JP 6787367 B2 JP6787367 B2 JP 6787367B2
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layer
gate
channel
semiconductor device
conductive type
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Japanese (ja)
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JP2019029651A5 (OSRAM
JP2019029651A (ja
Inventor
河野 憲司
憲司 河野
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Denso Corp
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Denso Corp
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Priority to PCT/JP2018/028142 priority Critical patent/WO2019022205A1/ja
Priority to CN201880048878.9A priority patent/CN110945633B/zh
Publication of JP2019029651A publication Critical patent/JP2019029651A/ja
Publication of JP2019029651A5 publication Critical patent/JP2019029651A5/ja
Priority to US16/695,753 priority patent/US11355589B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H10D30/0512—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates
    • H10D30/0515—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates of vertical FETs having PN homojunction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H10D30/831—Vertical FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/328—Channel regions of field-effect devices of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3408—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates

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  • Junction Field-Effect Transistors (AREA)
JP2018117316A 2017-07-26 2018-06-20 半導体装置 Active JP6787367B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2018/028142 WO2019022205A1 (ja) 2017-07-26 2018-07-26 半導体装置
CN201880048878.9A CN110945633B (zh) 2017-07-26 2018-07-26 半导体装置
US16/695,753 US11355589B2 (en) 2017-07-26 2019-11-26 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017144726 2017-07-26
JP2017144726 2017-07-26

Publications (3)

Publication Number Publication Date
JP2019029651A JP2019029651A (ja) 2019-02-21
JP2019029651A5 JP2019029651A5 (OSRAM) 2019-11-07
JP6787367B2 true JP6787367B2 (ja) 2020-11-18

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JP2018117316A Active JP6787367B2 (ja) 2017-07-26 2018-06-20 半導体装置

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US (1) US11355589B2 (OSRAM)
JP (1) JP6787367B2 (OSRAM)
CN (1) CN110945633B (OSRAM)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6973422B2 (ja) 2019-01-21 2021-11-24 株式会社デンソー 半導体装置の製造方法
JP7211393B2 (ja) 2020-04-22 2023-01-24 株式会社デンソー 半導体装置
US12408360B2 (en) * 2022-05-13 2025-09-02 Wolfspeed, Inc. Vertical power devices having mesas and etched trenches therebetween

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5945701A (en) 1997-12-19 1999-08-31 Northrop Grumman Corporation Static induction transistor
CA2689613A1 (en) 1999-12-21 2001-06-28 Sumitomo Electric Industries, Ltd. Horizontal junction field-effect transistor
CA2395608C (en) 1999-12-24 2010-06-22 Sumitomo Electric Industries, Ltd. Junction field effect transistor and method of manufacturing the same
JP2005005385A (ja) * 2003-06-10 2005-01-06 Toshiba Corp 半導体装置
US7187021B2 (en) 2003-12-10 2007-03-06 General Electric Company Static induction transistor
US7279368B2 (en) 2005-03-04 2007-10-09 Cree, Inc. Method of manufacturing a vertical junction field effect transistor having an epitaxial gate
JP4935160B2 (ja) 2006-04-11 2012-05-23 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP2007294716A (ja) 2006-04-26 2007-11-08 Hitachi Ltd 半導体装置
US7977713B2 (en) 2008-05-08 2011-07-12 Semisouth Laboratories, Inc. Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making
US7994548B2 (en) 2008-05-08 2011-08-09 Semisouth Laboratories, Inc. Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making
JP5326405B2 (ja) * 2008-07-30 2013-10-30 株式会社デンソー ワイドバンドギャップ半導体装置
JP5906914B2 (ja) 2012-04-19 2016-04-20 株式会社豊田中央研究所 トランジスタの駆動回路
US9209318B2 (en) 2013-02-20 2015-12-08 Infineon Technologies Austria Ag Vertical JFET with body diode and device regions disposed in a single compound epitaxial layer
JP6160216B2 (ja) * 2013-05-09 2017-07-12 富士電機株式会社 半導体装置
JP6148070B2 (ja) 2013-05-27 2017-06-14 ルネサスエレクトロニクス株式会社 縦チャネル型ジャンクションSiCパワーFETおよびその製造方法
US10325988B2 (en) * 2013-12-13 2019-06-18 Power Integrations, Inc. Vertical transistor device structure with cylindrically-shaped field plates
US9711660B2 (en) * 2014-03-13 2017-07-18 Infineon Technologies Ag JFET and method of manufacturing thereof
JP2017063079A (ja) * 2015-09-24 2017-03-30 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP6565815B2 (ja) * 2016-07-21 2019-08-28 株式会社デンソー 半導体装置

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Publication number Publication date
US20200098935A1 (en) 2020-03-26
JP2019029651A (ja) 2019-02-21
CN110945633B (zh) 2023-08-11
CN110945633A (zh) 2020-03-31
US11355589B2 (en) 2022-06-07

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