JP6784148B2 - 半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法 - Google Patents

半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法 Download PDF

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JP6784148B2
JP6784148B2 JP2016219845A JP2016219845A JP6784148B2 JP 6784148 B2 JP6784148 B2 JP 6784148B2 JP 2016219845 A JP2016219845 A JP 2016219845A JP 2016219845 A JP2016219845 A JP 2016219845A JP 6784148 B2 JP6784148 B2 JP 6784148B2
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JP2018078216A5 (enExample
JP2018078216A (ja
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鈴木　健司
健司 鈴木
徹雄 高橋
徹雄 高橋
充 金田
充 金田
龍 上馬場
龍 上馬場
康一 西
康一 西
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Mitsubishi Electric Corp
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Priority to DE102017219159.7A priority patent/DE102017219159A1/de
Priority to CN201711107493.9A priority patent/CN108074977A/zh
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H01L21/26—Bombardment with radiation
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JP2016219845A 2016-11-10 2016-11-10 半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法 Active JP6784148B2 (ja)

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JP2016219845A JP6784148B2 (ja) 2016-11-10 2016-11-10 半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法
US15/648,062 US10347715B2 (en) 2016-11-10 2017-07-12 Semiconductor device having improved safe operating areas and manufacturing method therefor
DE102017219159.7A DE102017219159A1 (de) 2016-11-10 2017-10-25 Halbleitervorrichtung und Fertigungsverfahren dafür
CN201711107493.9A CN108074977A (zh) 2016-11-10 2017-11-10 半导体装置及其制造方法

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JP6964566B2 (ja) * 2018-08-17 2021-11-10 三菱電機株式会社 半導体装置およびその製造方法
JP7268743B2 (ja) 2019-08-09 2023-05-08 富士電機株式会社 半導体装置
CN113767477B (zh) 2019-10-17 2025-03-11 富士电机株式会社 半导体装置和半导体装置的制造方法
JP6981582B2 (ja) * 2019-12-17 2021-12-15 富士電機株式会社 半導体装置
JP7361634B2 (ja) * 2020-03-02 2023-10-16 三菱電機株式会社 半導体装置及び半導体装置の製造方法
DE112020007265T5 (de) * 2020-05-29 2023-03-09 Mitsubishi Electric Corporation Halbleitereinheit und Leistungsvorrichtung
JP7374054B2 (ja) * 2020-08-20 2023-11-06 三菱電機株式会社 半導体装置
JP7567932B2 (ja) * 2020-11-17 2024-10-16 富士電機株式会社 半導体装置の製造方法
JP7415913B2 (ja) * 2020-12-28 2024-01-17 三菱電機株式会社 半導体装置及びその製造方法
CN113054010A (zh) * 2021-02-07 2021-06-29 华为技术有限公司 半导体器件及相关模块、电路、制备方法

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JP4156717B2 (ja) * 1998-01-13 2008-09-24 三菱電機株式会社 半導体装置
WO2007085387A1 (de) * 2006-01-20 2007-08-02 Infineon Technologies Austria Ag Verfahren zur behandlung eines sauerstoff enthaltenden halbleiterwafers und halbleiterbauelement
US7989888B2 (en) * 2006-08-31 2011-08-02 Infineon Technologies Autria AG Semiconductor device with a field stop zone and process of producing the same
JP5150953B2 (ja) 2008-01-23 2013-02-27 三菱電機株式会社 半導体装置
KR101752640B1 (ko) 2009-03-27 2017-06-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치
CN102687277B (zh) * 2009-11-02 2016-01-20 富士电机株式会社 半导体器件以及用于制造半导体器件的方法
JP5609087B2 (ja) 2009-12-04 2014-10-22 富士電機株式会社 内燃機関点火装置用半導体装置
IT1401754B1 (it) * 2010-08-30 2013-08-02 St Microelectronics Srl Dispositivo elettronico integrato e relativo metodo di fabbricazione.
WO2013005304A1 (ja) * 2011-07-05 2013-01-10 三菱電機株式会社 半導体装置
JP5735077B2 (ja) 2013-10-09 2015-06-17 株式会社東芝 半導体装置の製造方法
WO2015114748A1 (ja) * 2014-01-29 2015-08-06 三菱電機株式会社 電力用半導体装置
JP6269858B2 (ja) * 2014-11-17 2018-01-31 富士電機株式会社 炭化珪素半導体装置の製造方法
WO2016147264A1 (ja) * 2015-03-13 2016-09-22 三菱電機株式会社 半導体装置及びその製造方法

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JP2018078216A (ja) 2018-05-17
US20180130875A1 (en) 2018-05-10
US10347715B2 (en) 2019-07-09
CN108074977A (zh) 2018-05-25

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