JP6784148B2 - 半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法 - Google Patents

半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法 Download PDF

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JP6784148B2
JP6784148B2 JP2016219845A JP2016219845A JP6784148B2 JP 6784148 B2 JP6784148 B2 JP 6784148B2 JP 2016219845 A JP2016219845 A JP 2016219845A JP 2016219845 A JP2016219845 A JP 2016219845A JP 6784148 B2 JP6784148 B2 JP 6784148B2
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JP2018078216A5 (enExample
JP2018078216A (ja
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鈴木　健司
健司 鈴木
徹雄 高橋
徹雄 高橋
充 金田
充 金田
龍 上馬場
龍 上馬場
康一 西
康一 西
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to DE102017219159.7A priority patent/DE102017219159B4/de
Priority to CN201711107493.9A priority patent/CN108074977A/zh
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
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    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P30/218—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the implantation in a compound semiconductor of both electrically active and inactive species in the same semiconductor region to be doped n-type or p-type
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    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
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    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
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  • Electrodes Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thyristors (AREA)
JP2016219845A 2016-11-10 2016-11-10 半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法 Active JP6784148B2 (ja)

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JP2016219845A JP6784148B2 (ja) 2016-11-10 2016-11-10 半導体装置、絶縁ゲート型バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタの製造方法
US15/648,062 US10347715B2 (en) 2016-11-10 2017-07-12 Semiconductor device having improved safe operating areas and manufacturing method therefor
DE102017219159.7A DE102017219159B4 (de) 2016-11-10 2017-10-25 Halbleitervorrichtung und Fertigungsverfahren dafür
CN201711107493.9A CN108074977A (zh) 2016-11-10 2017-11-10 半导体装置及其制造方法

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JP6964566B2 (ja) * 2018-08-17 2021-11-10 三菱電機株式会社 半導体装置およびその製造方法
WO2021029285A1 (ja) 2019-08-09 2021-02-18 富士電機株式会社 半導体装置
WO2021075330A1 (ja) 2019-10-17 2021-04-22 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2021125140A1 (ja) 2019-12-17 2021-06-24 富士電機株式会社 半導体装置
JP7361634B2 (ja) * 2020-03-02 2023-10-16 三菱電機株式会社 半導体装置及び半導体装置の製造方法
JP7325627B2 (ja) * 2020-05-29 2023-08-14 三菱電機株式会社 半導体装置および電力機器
WO2022014624A1 (ja) 2020-07-14 2022-01-20 富士電機株式会社 半導体装置
JP7374054B2 (ja) * 2020-08-20 2023-11-06 三菱電機株式会社 半導体装置
WO2022107368A1 (ja) * 2020-11-17 2022-05-27 富士電機株式会社 半導体装置の製造方法および半導体装置
JP7415913B2 (ja) * 2020-12-28 2024-01-17 三菱電機株式会社 半導体装置及びその製造方法
CN116978937A (zh) 2021-02-07 2023-10-31 华为技术有限公司 半导体器件及相关模块、电路、制备方法
JP7875428B2 (ja) 2022-03-16 2026-06-18 富士電機株式会社 半導体装置
JP2024014333A (ja) 2022-07-22 2024-02-01 富士電機株式会社 半導体装置および半導体装置の製造方法
JP7838511B2 (ja) * 2023-04-07 2026-04-01 三菱電機株式会社 半導体装置および半導体装置の製造方法

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JP4156717B2 (ja) * 1998-01-13 2008-09-24 三菱電機株式会社 半導体装置
DE10330571B8 (de) 2003-07-07 2007-03-08 Infineon Technologies Ag Vertikale Leistungshalbleiterbauelemente mit Injektionsdämpfungsmittel im Rand bereich und Herstellungsverfahren dafür
JP5358189B2 (ja) * 2006-01-20 2013-12-04 インフィネオン テクノロジーズ オーストリア アクチエンゲゼルシャフト 酸素含有半導体ウェハの処理方法
US7989888B2 (en) * 2006-08-31 2011-08-02 Infineon Technologies Autria AG Semiconductor device with a field stop zone and process of producing the same
JP2009176772A (ja) 2008-01-21 2009-08-06 Denso Corp 半導体装置
JP5150953B2 (ja) 2008-01-23 2013-02-27 三菱電機株式会社 半導体装置
KR101752640B1 (ko) 2009-03-27 2017-06-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치
JP5569532B2 (ja) * 2009-11-02 2014-08-13 富士電機株式会社 半導体装置および半導体装置の製造方法
JP5609087B2 (ja) 2009-12-04 2014-10-22 富士電機株式会社 内燃機関点火装置用半導体装置
IT1401754B1 (it) * 2010-08-30 2013-08-02 St Microelectronics Srl Dispositivo elettronico integrato e relativo metodo di fabbricazione.
CN103650147B (zh) * 2011-07-05 2016-07-06 三菱电机株式会社 半导体装置
JP5817686B2 (ja) 2011-11-30 2015-11-18 株式会社デンソー 半導体装置
JP5735077B2 (ja) 2013-10-09 2015-06-17 株式会社東芝 半導体装置の製造方法
JP6311723B2 (ja) 2013-12-16 2018-04-18 富士電機株式会社 半導体装置および半導体装置の製造方法
KR101917486B1 (ko) * 2014-01-29 2018-11-09 미쓰비시덴키 가부시키가이샤 전력용 반도체 장치
CN106463528B (zh) * 2014-11-17 2019-10-11 富士电机株式会社 碳化硅半导体装置的制造方法
DE112015006307B4 (de) * 2015-03-13 2026-01-15 Mitsubishi Electric Corporation Verfahren einer Fertigung einer Halbleitervorrichtung

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US10347715B2 (en) 2019-07-09
DE102017219159B4 (de) 2026-03-26
JP2018078216A (ja) 2018-05-17
US20180130875A1 (en) 2018-05-10
DE102017219159A1 (de) 2018-05-17
CN108074977A (zh) 2018-05-25

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