JP6728363B2 - 改良された補剛材を有する積層シリコンパッケージアセンブリ - Google Patents
改良された補剛材を有する積層シリコンパッケージアセンブリ Download PDFInfo
- Publication number
- JP6728363B2 JP6728363B2 JP2018535415A JP2018535415A JP6728363B2 JP 6728363 B2 JP6728363 B2 JP 6728363B2 JP 2018535415 A JP2018535415 A JP 2018535415A JP 2018535415 A JP2018535415 A JP 2018535415A JP 6728363 B2 JP6728363 B2 JP 6728363B2
- Authority
- JP
- Japan
- Prior art keywords
- package substrate
- stiffener
- chip package
- package
- package assembly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003351 stiffener Substances 0.000 title claims description 210
- 239000000758 substrate Substances 0.000 claims description 222
- 229910000679 solder Inorganic materials 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 description 38
- 230000000712 assembly Effects 0.000 description 23
- 238000000429 assembly Methods 0.000 description 23
- 239000000853 adhesive Substances 0.000 description 17
- 230000001070 adhesive effect Effects 0.000 description 17
- FZFUUSROAHKTTF-UHFFFAOYSA-N 2,2',3,3',6,6'-hexachlorobiphenyl Chemical compound ClC1=CC=C(Cl)C(C=2C(=C(Cl)C=CC=2Cl)Cl)=C1Cl FZFUUSROAHKTTF-UHFFFAOYSA-N 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 230000008901 benefit Effects 0.000 description 9
- 239000004593 Epoxy Substances 0.000 description 7
- 238000005452 bending Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006664 bond formation reaction Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4817—Conductive parts for containers, e.g. caps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/145—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
- H01L2924/35121—Peeling or delaminating
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
タブレット、コンピュータ、コピー機、デジタルカメラ、スマートフォン、制御システム、および現金自動支払機等の電子機器は特に、高機能化および部品の高密度化のためにチップパッケージアセンブリを活用する電子部品を使用することが多い。従来のチップパッケージング方式は、多くの場合シリコン貫通ビア(through-silicon-via:TSV)インターポーザとともにパッケージ基板を使用することにより、複数の集積回路(IC)ダイを単一のパッケージ基板に搭載できるようにすることが多い。このICダイは、メモリ、ロジックまたはその他のICデバイスを含み得る。
チップパッケージアセンブリおよびその製造方法が提供される。これは、補剛材を利用して面外変形の防止のためにパッケージ基板を改良する。一例において提供されるチップパッケージアセンブリは、パッケージ基板と、少なくとも1つの集積回路(IC)ダイと、補剛材とを備える。パッケージ基板は、側壁によって結合された第1の面と第2の面とを有する。少なくとも1つのICダイはパッケージ基板の第1の面に配置されている。補剛材は、少なくとも1つのICダイの外側に配置されている。補剛材は、パッケージ基板の側壁の外側に配置されこの側壁に接合された第1の面を有する。補剛材は、パッケージ基板の第1および第2の面のうちの少なくとも一方に接合された第2の面を有する。
改良された補剛材を利用するチップパッケージアセンブリおよびその製造方法が提供される。本明細書に記載のチップパッケージアセンブリは、パッケージ基板上に配置された少なくとも1つの集積回路(IC)ダイと補剛材とを含む。補剛材は、チップパッケージアセンブリの製造および使用中の面外変形に対するパッケージ基板の耐性を高めるように構成される。好都合には、チップパッケージアセンブリのスチフネスを高めることにより、信頼性および性能を改善する。本明細書に記載のさまざまな例において、1つ以上の利点を実現し得る。それは、いくつかある利点の中でも特に、パッケージ基板が水平および鉛直軸双方において補剛されること、接着剤で装着する面積の増大による層状剥離の低減、チップキャパシタ等の表面実装回路要素のための空間の増大、パッケージ厚みの縮小、およびボールグリッドアレイ(BGA)のスタンドオフ高さの制御を含む。
Claims (14)
- チップパッケージアセンブリであって、
側壁によって結合された第1の面と第2の面とを有するパッケージ基板と、
前記パッケージ基板の前記第1の面上に配置された少なくとも1つの集積回路(IC)ダイと、
前記パッケージ基板の前記側壁の外側に配置され前記側壁に接合された第1の面を有する補剛材とを備え、前記補剛材は、前記パッケージ基板の前記第1の面および前記第2の面のうちの少なくとも一方に接合された第2の面と、前記補剛材の前記第1の面に対向すするとともに平行な第3の面とを有し、前記補剛材は前記ICダイを囲んでおり、
前記補剛材とは別個の、前記補剛材に結合された少なくとも1つの装着面を含むアダプタを備え、
前記アダプタは、前記補剛材の前記第3の面に揃えられた外壁を含む、チップパッケージアセンブリ。 - 前記補剛材は、前記パッケージ基板の前記側壁と前記第1の面とに接合されている、または、前記補剛材は前記パッケージ基板の前記側壁と前記第2の面とに接合されている、請求項1に記載のチップパッケージアセンブリ。
- 前記補剛材は、前記パッケージ基板の前記第2の面よりも下に突出するスタンドオフ部分をさらに含む、請求項1に記載のチップパッケージアセンブリ。
- 前記パッケージ基板の前記第2の面に配置された複数のはんだボールをさらに備え、前記はんだボールは、前記パッケージ基板の前記第2の面から前記スタンドオフ部分を超える距離だけ延在している、請求項3に記載のチップパッケージアセンブリ。
- 前記アダプタに結合され前記ICダイ全体にわたって延在する蓋をさらに備える、請求項1に記載のチップパッケージアセンブリ。
- 前記補剛材は前記パッケージ基板の前記第1の面と前記蓋とに接合されている、または、前記補剛材は前記パッケージ基板の前記第2の面と前記蓋とに接合されている、請求項5に記載のチップパッケージアセンブリ。
- 前記補剛材は、前記パッケージ基板の前記第2の面よりも下に突出するスタンドオフ部分をさらに含み、前記チップパッケージアセンブリは、前記パッケージ基板の前記第2の面に配置された複数のはんだボールをさらに備え、前記はんだボールは、前記パッケージ基板の前記第2の面から前記スタンドオフ部分を超える距離だけ延在している、請求項5に記載のチップパッケージアセンブリ。
- 前記補剛材の前記第2の面は、
前記パッケージ基板の第1の角を覆う第1の部分と、
前記パッケージ基板の第2の角を覆う第2の部分とをさらに含み、
前記補剛材の前記第2の面は、前記第1の部分と前記第2の部分との間において連続していない、請求項1に記載のチップパッケージアセンブリ。 - 前記補剛材の前記第2の面は、前記パッケージ基板の前記第1の面または前記第2の面のうちの一部分のみを覆う、請求項1に記載のチップパッケージアセンブリ。
- 前記補剛材の前記第1の面は、前記パッケージ基板の前記側壁の一部分のみを覆う、請求項1に記載のチップパッケージアセンブリ。
- 前記補剛材は前記アダプタと前記パッケージ基板の前記第1の面とに接合されている、または、前記補剛材は前記アダプタと前記パッケージ基板の前記第2の面とに接合されている、請求項1に記載のチップパッケージアセンブリ。
- 前記補剛材は、前記パッケージ基板の前記第2の面よりも下に突出するスタンドオフ部分をさらに含み、前記チップパッケージアセンブリは、前記パッケージ基板の前記第2の面に配置された複数のはんだボールをさらに備え、前記はんだボールは、前記パッケージ基板の前記第2の面から前記スタンドオフ部分を超える距離だけ延在している、請求項1に記載のチップパッケージアセンブリ。
- 前記アダプタに結合され前記ICダイ全体にわたって延在する蓋をさらに備える、請求項1に記載のチップパッケージアセンブリ。
- 前記補剛材は複数の別々の補剛材セグメントを含み、各セグメントは前記パッケージ基板の異なる部分に接合されている、請求項1に記載のチップパッケージアセンブリ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201614990560A | 2016-01-07 | 2016-01-07 | |
US14/990,560 | 2016-01-07 | ||
PCT/US2016/058788 WO2017119937A1 (en) | 2016-01-07 | 2016-10-26 | Stacked silicon package assembly having enhanced stiffener |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019501534A JP2019501534A (ja) | 2019-01-17 |
JP6728363B2 true JP6728363B2 (ja) | 2020-07-22 |
Family
ID=57286830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018535415A Active JP6728363B2 (ja) | 2016-01-07 | 2016-10-26 | 改良された補剛材を有する積層シリコンパッケージアセンブリ |
Country Status (6)
Country | Link |
---|---|
US (1) | US10840192B1 (ja) |
EP (1) | EP3357085A1 (ja) |
JP (1) | JP6728363B2 (ja) |
KR (1) | KR102542735B1 (ja) |
CN (1) | CN108431946B (ja) |
WO (1) | WO2017119937A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102018204764A1 (de) * | 2018-03-28 | 2019-10-02 | Infineon Technologies Ag | Halbleiter- packagesystem |
US10764996B1 (en) | 2018-06-19 | 2020-09-01 | Xilinx, Inc. | Chip package assembly with composite stiffener |
KR20200113581A (ko) * | 2019-03-26 | 2020-10-07 | 삼성전자주식회사 | 반도체 패키지 |
TWI768294B (zh) | 2019-12-31 | 2022-06-21 | 力成科技股份有限公司 | 封裝結構及其製造方法 |
KR102596757B1 (ko) | 2020-03-27 | 2023-11-02 | 삼성전자주식회사 | 스티프너를 갖는 반도체 패키지 |
US11721641B2 (en) * | 2020-05-19 | 2023-08-08 | Google Llc | Weight optimized stiffener and sealing structure for direct liquid cooled modules |
CN114513893A (zh) * | 2020-11-16 | 2022-05-17 | 华为技术有限公司 | 一种加强结构及电子设备 |
US11830746B2 (en) * | 2021-01-05 | 2023-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
US20220230969A1 (en) * | 2021-01-15 | 2022-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of fabricating the same |
US20230063295A1 (en) * | 2021-08-27 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure with stiffener ring having slant sidewall |
US20230064277A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and formation method of chip package with reinforcing structures |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4092697A (en) | 1976-12-06 | 1978-05-30 | International Business Machines Corporation | Heat transfer mechanism for integrated circuit package |
US4265775A (en) | 1979-08-16 | 1981-05-05 | International Business Machines Corporation | Non-bleeding thixotropic thermally conductive material |
US5028984A (en) | 1988-11-04 | 1991-07-02 | International Business Machines Corporation | Epoxy composition and use thereof |
US5471027A (en) | 1994-07-22 | 1995-11-28 | International Business Machines Corporation | Method for forming chip carrier with a single protective encapsulant |
JP3004578B2 (ja) | 1995-05-12 | 2000-01-31 | 財団法人工業技術研究院 | 熱放散増強のための多熱導伝路とパッケージ統合性及び信頼性向上のための縁の周りを囲むキャップからなる集積回路パッケージ |
US5956576A (en) | 1996-09-13 | 1999-09-21 | International Business Machines Corporation | Enhanced protection of semiconductors with dual surface seal |
US6218730B1 (en) | 1999-01-06 | 2001-04-17 | International Business Machines Corporation | Apparatus for controlling thermal interface gap distance |
JP4214640B2 (ja) * | 1999-11-02 | 2009-01-28 | ソニー株式会社 | 多層プリント配線板 |
JP3900768B2 (ja) | 2000-01-06 | 2007-04-04 | 三菱電機株式会社 | パワーモジュール |
JP3400427B2 (ja) * | 2000-11-28 | 2003-04-28 | 株式会社東芝 | 電子部品ユニット及び電子部品ユニットを実装した印刷配線板装置 |
KR100394809B1 (ko) * | 2001-08-09 | 2003-08-14 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
JP2003100924A (ja) * | 2001-09-21 | 2003-04-04 | Kyocera Corp | 半導体装置 |
US6646356B1 (en) | 2002-05-09 | 2003-11-11 | Bae Systems, Information And Electronic Systems Integration Inc. | Apparatus for providing mechanical support to a column grid array package |
US6903271B2 (en) | 2003-09-30 | 2005-06-07 | Intel Corporation | Electronic assembly with thermally separated support |
JP2005159136A (ja) * | 2003-11-27 | 2005-06-16 | Nikon Corp | Cob実装用の枠体、パッケージ実装用の枠体、及び半導体装置 |
JP2006196857A (ja) * | 2004-12-16 | 2006-07-27 | Murata Mfg Co Ltd | ケース付き複合回路基板及びその製造方法 |
TWI257135B (en) * | 2005-03-29 | 2006-06-21 | Advanced Semiconductor Eng | Thermally enhanced three dimension package and method for manufacturing the same |
TWI311366B (en) * | 2006-06-30 | 2009-06-21 | Advanced Semiconductor Eng | A flip-chip package structure with stiffener |
TWI309879B (en) | 2006-08-21 | 2009-05-11 | Advanced Semiconductor Eng | Reinforced package and the stiffener thereof |
US7808100B2 (en) * | 2008-04-21 | 2010-10-05 | Infineon Technologies Ag | Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element |
US20090321925A1 (en) * | 2008-06-30 | 2009-12-31 | Gealer Charles A | Injection molded metal ic package stiffener and package-to-package interconnect frame |
JP2010192653A (ja) * | 2009-02-18 | 2010-09-02 | Panasonic Corp | 半導体装置 |
JP2011124413A (ja) * | 2009-12-11 | 2011-06-23 | Murata Mfg Co Ltd | 電子部品モジュールの製造方法及び電子部品モジュール |
US8679900B2 (en) * | 2011-12-14 | 2014-03-25 | Stats Chippac Ltd. | Integrated circuit packaging system with heat conduction and method of manufacture thereof |
US20140091461A1 (en) * | 2012-09-30 | 2014-04-03 | Yuci Shen | Die cap for use with flip chip package |
US20140167243A1 (en) | 2012-12-13 | 2014-06-19 | Yuci Shen | Semiconductor packages using a chip constraint means |
US10032696B2 (en) * | 2012-12-21 | 2018-07-24 | Nvidia Corporation | Chip package using interposer substrate with through-silicon vias |
US9978660B2 (en) * | 2014-03-14 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company | Package with embedded heat dissipation features |
-
2016
- 2016-10-26 KR KR1020187022118A patent/KR102542735B1/ko active IP Right Grant
- 2016-10-26 JP JP2018535415A patent/JP6728363B2/ja active Active
- 2016-10-26 CN CN201680077521.4A patent/CN108431946B/zh active Active
- 2016-10-26 WO PCT/US2016/058788 patent/WO2017119937A1/en active Application Filing
- 2016-10-26 EP EP16794822.3A patent/EP3357085A1/en active Pending
-
2017
- 2017-04-06 US US15/481,275 patent/US10840192B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
WO2017119937A1 (en) | 2017-07-13 |
CN108431946A (zh) | 2018-08-21 |
US10840192B1 (en) | 2020-11-17 |
EP3357085A1 (en) | 2018-08-08 |
JP2019501534A (ja) | 2019-01-17 |
KR20180100603A (ko) | 2018-09-11 |
CN108431946B (zh) | 2021-12-07 |
KR102542735B1 (ko) | 2023-06-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6728363B2 (ja) | 改良された補剛材を有する積層シリコンパッケージアセンブリ | |
US10236229B2 (en) | Stacked silicon package assembly having conformal lid | |
US7679178B2 (en) | Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof | |
US20100109138A1 (en) | Wafer-level chip-on-chip package, package on package, and methods of manufacturing the same | |
JP2005045251A (ja) | スタック半導体チップbgaパッケージ及びその製造方法 | |
US11869829B2 (en) | Semiconductor device with through-mold via | |
TW201810566A (zh) | 半導體裝置之製造方法 | |
KR20020061812A (ko) | 볼 그리드 어레이형 멀티 칩 패키지와 적층 패키지 | |
US7660130B2 (en) | Semiconductor device | |
JP2006156797A (ja) | 半導体装置 | |
KR101450761B1 (ko) | 반도체 패키지, 적층형 반도체 패키지 및 반도체 패키지의 제조방법 | |
US8796834B2 (en) | Stack type semiconductor package | |
JP5547703B2 (ja) | 半導体装置の製造方法 | |
US20110304038A1 (en) | Semiconductor chip designed to dissipate heat effectively, semiconductor package including the same, and stack package using the same | |
TWI676266B (zh) | 半導體裝置及其製造方法 | |
US8519522B2 (en) | Semiconductor package | |
TWI423405B (zh) | 具載板之封裝結構 | |
TW201330220A (zh) | 具凹槽之封裝結構及其製造方法 | |
KR20160112345A (ko) | 반도체 칩 | |
KR20080067891A (ko) | 멀티 칩 패키지 | |
JP2007067234A (ja) | 半導体装置及びその製造方法 | |
KR20080074654A (ko) | 적층 반도체 패키지 | |
CN112447690B (zh) | 天线置顶的半导体封装结构 | |
US20200381400A1 (en) | Semiconductor package and semiconductor device including the same | |
KR20150056406A (ko) | 반도체 플립칩 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A529 | Written submission of copy of amendment under article 34 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A529 Effective date: 20180905 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20191024 |
|
A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20191024 |
|
A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20191106 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200128 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200402 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200602 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200701 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6728363 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |