JP6726215B2 - フラッシュランプおよびマスクを使用して複数のチップをはんだ付けするための装置および方法 - Google Patents
フラッシュランプおよびマスクを使用して複数のチップをはんだ付けするための装置および方法 Download PDFInfo
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- JP6726215B2 JP6726215B2 JP2017556661A JP2017556661A JP6726215B2 JP 6726215 B2 JP6726215 B2 JP 6726215B2 JP 2017556661 A JP2017556661 A JP 2017556661A JP 2017556661 A JP2017556661 A JP 2017556661A JP 6726215 B2 JP6726215 B2 JP 6726215B2
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0145—Polyester, e.g. polyethylene terephthalate [PET], polyethylene naphthalate [PEN]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
1b チップ
2 はんだ材料
3 基板
4 基板ハンドラ
5 光源、フラッシュランプ
6 光パルス
6a 光、部分、エリア
7 マスキングデバイス
7a マスクパターン
7b マスクパターン
7c マスクパターン
8 チップキャリア
9 はんだ供給ユニット
10 トラック塗布ユニット
11 チップ位置特定デバイス
12 チップセンサ
15 コントローラ
C1 加熱特性
C2 加熱特性
Ia 光強度
Ib 光強度
Ca 第1の熱容量
Cb 第2の熱容量
Ta 第1の透過係数
Tb 第2の透過係数
Tc 第3の透過係数
7p ピクセル
Claims (15)
- 基板(3)にチップ(1a、1b)をはんだ付けするための方法であって、
基板(3)と、異なる加熱特性(C1、C2)を有する2つ以上の異なるチップ(1a、1b)とを用意するステップであって、はんだ材料(2)が、前記チップ(1a、1B)と前記基板(3)との間に配設される、ステップと、
前記チップ(1a、1b)を加熱するために光パルス(6)を発生させるフラッシュランプ(5)を用意するステップであって、前記はんだ材料(2)は、前記加熱されたチップ(1a、1b)と接触することにより少なくとも部分的に溶融される、ステップと
を含み、
マスキングデバイス(7)が、前記フラッシュランプ(5)と前記チップ(1a、1b)との間に配設されて、前記マスキングデバイス(7)を通過する前記光パルス(6)の別々のエリアに異なる光強度(Ia、Ib)を引き起こさせることにより、前記異なる加熱特性(C1、C2)を少なくとも部分的に相殺するように異なる光強度(Ia、Ib)で前記チップ(1a、1b)を加熱することによって、前記光パルス(6)による前記加熱の結果としての前記チップ間の温度の差異を低減させる、方法。 - 前記マスキングデバイス(7)は、前記チップ(1a、1b)に前記光パルス(6)を選択的に伝達するように構成されたマスクパターン(7a、7b、7c)を含み、前記マスクパターン(7a、7b、7c)は、第1のチップ(1a)と前記基板(3)との間ではんだ材料(2)を溶融するために前記第1のチップ(1a)に第1の光強度(Ia)を有する前記光パルス(6)の光(6a)を伝達するように構成された第1の透過係数(Ta)を有する第1のフィルタ領域(7a)と、第2のチップ(1b)と前記基板(3)との間ではんだ材料(2)を溶融するために前記第2のチップ(1b)に第2の光強度(Ib)を有する前記光パルス(6)の光(6b)を伝達するように構成された第2の透過係数(Tb)を有する第2のフィルタ領域(7b)とを備え、異なる光強度(Ia、Ib)で前記チップ(1a、1b)を同時に照射するために、前記第1の透過係数(Ta)は前記第2の透過係数(Tb)とは異なる、請求項1に記載の方法。
- 前記光パルス(6)の前記伝達された光(6a、6b)は、前記チップ(1a、1b)が間に前記はんだ材料(2)が位置する状態において前記基板(3)上に位置決めされる間に、前記チップ(1a、1b)上に投影されることにより、前記チップ(1a、1b)を加熱し、前記加熱されたチップ(1a、1b)は、前記基板(3)に前記チップ(1a、1b)を装着するために前記はんだ材料(2)の前記少なくとも部分的な溶融を引き起こす、請求項2に記載の方法。
- 前記チップ(1a、1b)を取外し可能に搬送するように構成されたチップキャリア(8)を用意するステップを含み、前記チップキャリア(8)は、前記フラッシュランプ(5)と前記基板(3)との間に配設され、前記チップ(1a、1b)は、前記基板(3)上に位置決めされる前に前記基板(3)の上方で前記チップキャリア(8)により搬送され、前記マスキングデバイス(7)により伝達される前記光パルス(6)の光(6a、6b)は、前記チップキャリア(8)により保持された前記チップ(1a、1b)上に投影されることにより前記チップ(1a、1b)を加熱し、前記チップ(1a、1b)は、前記加熱により前記チップキャリア(8)から取り外され、前記基板(3)に移送され、前記加熱されたチップ(1a、1b)は、前記基板(3)に前記チップ(1a、1b)を装着するために前記チップ(1a、1b)と前記基板(3)との間の前記はんだ材料(2)の前記少なくとも部分的な溶融を引き起こさせる、請求項1から3のいずれか一項に記載の方法。
- 前記光パルス(6)の前記伝達された光(6a、6b)は、前記チップキャリア(8)と前記チップ(1a、1b)との間の材料の分解を引き起こすことにより前記チップキャリア(8)から前記チップ(1a、1b)を取り外し、前記光パルス(6)の前記伝達された光(6a、6b)は、前記チップ(1a、1b)が前記チップキャリア(8)と前記基板(3)との間の距離を通過する間に前記チップ(1a、1b)を照射し続け、前記光パルス(6)の前記伝達された光(6a、6b)は、前記チップ(1a、1b)が間に前記はんだ材料(2)が位置する状態において前記基板(3)上に位置決めされるときに前記チップ(1a、1b)を照射し続ける、請求項4に記載の方法。
- 前記基板(3)は、可撓性フォイルを含み、基板ハンドラ(4)が、前記可撓性フォイルを取り扱うためのロールを含む、請求項1から5のいずれか一項に記載の方法。
- 基板(3)に異なる加熱特性(C1、C2)を有する異なるチップ(1a、1b)をはんだ付けするための装置であって、
前記基板(3)の位置を決定するように構成された基板ハンドラ(4)と、
前記基板(3)に対して前記チップ(1a、1b)の位置を決定するように構成されたチップ位置特定デバイス(11)と、
前記チップ(1a、1b)を加熱するために前記チップ(1a、1b)に光パルス(6)を送達するように構成されたフラッシュランプ(5)と、
前記フラッシュランプ(5)と前記チップ(1a、1b)との間に配設されたマスキングデバイス(7)であって、異なる加熱特性(C1、C2)を有する前記チップ(1a、1b)を異なる光強度(Ia、Ib)で加熱するために、前記マスキングデバイス(7)を通過する前記光パルス(6)の別々のエリアに異なる光強度(Ia、Ib)を引き起こすように構成された、マスキングデバイス(7)と
を備える、装置。 - 前記マスキングデバイス(7)は、前記チップ(1a、1b)に前記光パルス(6)を選択的に伝達するように構成されたマスクパターン(7a、7b、7c)を含み、前記マスクパターン(7a、7b、7c)は、
第1のチップ(1a)と前記基板(3)との間のはんだ材料(2)を溶融するために前記第1のチップ(1a)に第1の光強度(Ia)を有する前記光パルス(6)の光(6a)を伝達するように構成された第1の透過係数(Ta)を有する第1のフィルタ領域(7a)と、
第2のチップ(1b)と前記基板(3)との間のはんだ材料(2)を溶融するために前記第2のチップ(1b)に第2の光強度(Ib)を有する前記光パルス(6)の光(6b)を伝達するように構成された第2の透過係数(Tb)を有する第2のフィルタ領域(7b)であって、異なる光強度(Ia、Ib)で前記チップ(1a、1b)を同時に照射するために、前記第1の透過係数(Ta)は前記第2の透過係数(Tb)とは異なる、第2のフィルタ領域(7b)と
を含む、請求項7に記載の装置。 - 前記チップ(1a、1b)のそれぞれの大きさに依拠して前記光強度(Ia、Ib)を可変的に調整するように構成されたコントローラ(15)を含む、請求項7または8に記載の装置。
- 前記チップ位置特定デバイス(11)、マスキングデバイス(7)、および/または基板ハンドラ(4)を制御するように構成され、および前記光パルス(6)の前記別々のエリアの異なる光強度(Ia、Ib)を前記異なるチップ(1a、1b)の位置と位置合わせするようにプログラムされたコントローラ(15)を含む、請求項7から9のいずれか一項に記載の装置。
- 前記チップの比較的低い照射面積当たりの熱容量(C1)を有するチップ(1b)に対して意図された前記光パルス(6)の部分(6b)のための比較的低い光強度(Ib)と、前記チップの比較的高い照射面積当たりの熱容量(C2)を有するチップ(1a)に対して意図された前記光パルス(6)の部分(6a)のための比較的高い光強度(Ib)とを設定するようにプログラムされたコントローラ(15)を含む、請求項7から10のいずれか一項に記載の装置。
- 前記チップ(1a、1b)を取外し可能に搬送するように構成されたチップキャリア(8)を含み、前記チップキャリア(8)は、前記フラッシュランプ(5)と前記基板(3)との間に配設され、前記チップ(1a、1b)は、前記基板(3)上に位置決めされる前に前記基板(3)の上方で前記チップキャリア(8)により搬送され、使用時に、前記マスキングデバイス(7)により伝達される前記光パルス(6)の光(6a、6b)は、前記チップ(1a、1b)を加熱するために前記チップキャリア(8)により保持された前記チップ(1a、1b)上に投影され、前記チップ(1a、1b)は、前記加熱により前記チップキャリア(8)から取り外され、前記基板(3)に移送され、前記加熱されたチップ(1a、1b)は、前記基板(3)に前記チップ(1a、1b)を装着するために前記チップ(1a、1b)と前記基板(3)との間の前記はんだ材料(2)の溶融を引き起こす、請求項7から11のいずれか一項に記載の装置。
- 前記マスキングデバイス(7)および前記チップキャリア(8)は、単一片として一体化される、請求項12に記載の装置。
- 前記マスキングデバイス(7)は、前記基板(3)に一体化される、請求項7から11のいずれか一項に記載の装置。
- 前記マスクパターン(7a、7b、7c)は、前記光パルス(6)の一部を遮断するように、または前記第1の光強度(Ia)および前記第2の光強度(Ib)とは異なる第3の光強度(Ic)を有する前記光パルス(6)の光(6c)を伝達するように構成された、第3の透過係数(Tc)を有する第3のフィルタ領域(7c)を含む、請求項8に記載の装置。
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PCT/NL2016/050295 WO2016175653A2 (en) | 2015-04-28 | 2016-04-26 | Apparatus and method for soldering chips |
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US20210043597A1 (en) * | 2019-08-05 | 2021-02-11 | Apple Inc. | Selective Soldering with Photonic Soldering Technology |
KR102369108B1 (ko) * | 2020-04-22 | 2022-03-02 | 주식회사 아큐레이저 | 기판에 배치된 디바이스 모듈 처리 장치 |
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US10304797B2 (en) | 2019-05-28 |
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CN107690697A (zh) | 2018-02-13 |
WO2016175653A2 (en) | 2016-11-03 |
KR102485392B1 (ko) | 2023-01-05 |
KR20180005198A (ko) | 2018-01-15 |
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