JP6670749B2 - 構成可能なピンを備える三次元フラッシュnorメモリシステム - Google Patents
構成可能なピンを備える三次元フラッシュnorメモリシステム Download PDFInfo
- Publication number
- JP6670749B2 JP6670749B2 JP2016536215A JP2016536215A JP6670749B2 JP 6670749 B2 JP6670749 B2 JP 6670749B2 JP 2016536215 A JP2016536215 A JP 2016536215A JP 2016536215 A JP2016536215 A JP 2016536215A JP 6670749 B2 JP6670749 B2 JP 6670749B2
- Authority
- JP
- Japan
- Prior art keywords
- die
- interface
- memory
- pins
- tsv
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/094,595 US20150155039A1 (en) | 2013-12-02 | 2013-12-02 | Three-Dimensional Flash NOR Memory System With Configurable Pins |
| US14/094,595 | 2013-12-02 | ||
| PCT/US2014/064381 WO2015084534A1 (en) | 2013-12-02 | 2014-11-06 | Three-dimensional flash nor memory system with configurable pins |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017502444A JP2017502444A (ja) | 2017-01-19 |
| JP2017502444A5 JP2017502444A5 (enExample) | 2017-09-28 |
| JP6670749B2 true JP6670749B2 (ja) | 2020-03-25 |
Family
ID=52001074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016536215A Active JP6670749B2 (ja) | 2013-12-02 | 2014-11-06 | 構成可能なピンを備える三次元フラッシュnorメモリシステム |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US20150155039A1 (enExample) |
| EP (1) | EP3078028A1 (enExample) |
| JP (1) | JP6670749B2 (enExample) |
| KR (1) | KR101931419B1 (enExample) |
| CN (1) | CN105793928B (enExample) |
| TW (1) | TWI550926B (enExample) |
| WO (1) | WO2015084534A1 (enExample) |
Families Citing this family (25)
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| US9361995B1 (en) | 2015-01-21 | 2016-06-07 | Silicon Storage Technology, Inc. | Flash memory system using complementary voltage supplies |
| KR102290020B1 (ko) * | 2015-06-05 | 2021-08-19 | 삼성전자주식회사 | 스택드 칩 구조에서 소프트 데이터 페일 분석 및 구제 기능을 제공하는 반도체 메모리 장치 |
| KR20170030307A (ko) * | 2015-09-09 | 2017-03-17 | 삼성전자주식회사 | 분리 배치된 커패시터를 갖는 메모리 장치 |
| CN108292641A (zh) * | 2015-12-26 | 2018-07-17 | 英特尔公司 | 垂直嵌入的无源组件 |
| WO2017136305A1 (en) * | 2016-02-01 | 2017-08-10 | Octavo Systems Llc | Systems and methods for manufacturing electronic devices |
| WO2017210305A1 (en) | 2016-06-01 | 2017-12-07 | Cpi Card Group - Colorado, Inc. | Ic chip card with integrated biometric sensor pads |
| US10446200B2 (en) * | 2018-03-19 | 2019-10-15 | Micron Technology, Inc. | Memory device with configurable input/output interface |
| US10580491B2 (en) * | 2018-03-23 | 2020-03-03 | Silicon Storage Technology, Inc. | System and method for managing peak power demand and noise in non-volatile memory array |
| US10923462B2 (en) | 2018-05-01 | 2021-02-16 | Western Digital Technologies, Inc. | Bifurcated memory die module semiconductor device |
| US10522489B1 (en) | 2018-06-28 | 2019-12-31 | Western Digital Technologies, Inc. | Manufacturing process for separating logic and memory array |
| US10579425B1 (en) | 2018-10-04 | 2020-03-03 | International Business Machines Corporation | Power aware scheduling of requests in 3D chip stack |
| US11222884B2 (en) * | 2018-11-28 | 2022-01-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Layout design methodology for stacked devices |
| JP2021048230A (ja) | 2019-09-18 | 2021-03-25 | キオクシア株式会社 | 半導体記憶装置 |
| US11239203B2 (en) * | 2019-11-01 | 2022-02-01 | Xilinx, Inc. | Multi-chip stacked devices |
| KR20220106991A (ko) | 2019-11-11 | 2022-08-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 정보 처리 장치 및 정보 처리 장치의 동작 방법 |
| US12475948B2 (en) | 2019-11-22 | 2025-11-18 | Semiconductor Energy Laboratory Co., Ltd. | Computer system using 3D OS NAND |
| US11435811B2 (en) * | 2019-12-09 | 2022-09-06 | Micron Technology, Inc. | Memory device sensors |
| US11726721B2 (en) | 2020-09-09 | 2023-08-15 | Samsung Electronics Co., Ltd. | Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system |
| KR102837298B1 (ko) | 2020-12-22 | 2025-07-23 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
| CN112752097B (zh) * | 2020-12-30 | 2023-05-26 | 长春长光辰芯微电子股份有限公司 | 一种cmos图像传感器的测试方法和系统 |
| US11856114B2 (en) * | 2021-02-12 | 2023-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device signature based on trim and redundancy information |
| US11557572B2 (en) * | 2021-05-13 | 2023-01-17 | Nanya Technology Corporation | Semiconductor device with stacked dies and method for fabricating the same |
| US12210777B2 (en) | 2022-09-05 | 2025-01-28 | Samsung Electronics Co., Ltd. | Memory device, operating method of the memory device, and memory system including the same |
| US12100468B2 (en) * | 2022-09-06 | 2024-09-24 | Micron Technology, Inc. | Standalone mode |
| US20240389363A1 (en) * | 2023-05-16 | 2024-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method for forming the same |
Family Cites Families (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6085500A (ja) * | 1983-10-18 | 1985-05-14 | Fujitsu Ltd | 高集積回路素子内蔵メモリの試験方式 |
| US5619461A (en) * | 1995-07-28 | 1997-04-08 | Micron Quantum Devices, Inc. | Memory system having internal state monitoring circuit |
| JP3710931B2 (ja) * | 1998-03-26 | 2005-10-26 | 三洋電機株式会社 | マイクロコンピュータ |
| US6651196B1 (en) * | 1999-02-16 | 2003-11-18 | Fujitsu Limited | Semiconductor device having test mode entry circuit |
| WO2001059571A2 (en) * | 2000-02-11 | 2001-08-16 | Advanced Micro Devices, Inc. | Command-driven test modes |
| ITVA20010034A1 (it) * | 2001-10-12 | 2003-04-12 | St Microelectronics Srl | Dispositivo di memoria non volatile a doppia modalita' di funzionamento parallela e seriale con protocollo di comunicazione selezionabile. |
| KR100462877B1 (ko) * | 2002-02-04 | 2004-12-17 | 삼성전자주식회사 | 반도체 메모리 장치, 및 이 장치의 불량 셀 어드레스프로그램 회로 및 방법 |
| US6788595B2 (en) | 2002-08-05 | 2004-09-07 | Silicon Storage Technology, Inc. | Embedded recall apparatus and method in nonvolatile memory |
| EP1424635B1 (en) * | 2002-11-28 | 2008-10-29 | STMicroelectronics S.r.l. | Non volatile memory device architecture, for instance a flash kind, having a serial communication interface |
| CN1523367A (zh) * | 2003-02-17 | 2004-08-25 | 上海华园微电子技术有限公司 | 一种测试电可擦除电可编程存储器的性能及其故障的方法 |
| US7233024B2 (en) * | 2003-03-31 | 2007-06-19 | Sandisk 3D Llc | Three-dimensional memory device incorporating segmented bit line memory array |
| EP1480224A1 (en) * | 2003-05-22 | 2004-11-24 | STMicroelectronics S.r.l. | A semiconductor memory with a multiprotocol serial communication interface |
| US7558900B2 (en) * | 2004-09-27 | 2009-07-07 | Winbound Electronics Corporation | Serial flash semiconductor memory |
| JP4565966B2 (ja) * | 2004-10-29 | 2010-10-20 | 三洋電機株式会社 | メモリ素子 |
| US7652922B2 (en) * | 2005-09-30 | 2010-01-26 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
| KR20080026725A (ko) * | 2006-09-21 | 2008-03-26 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 내부신호 모니터장치 및 모니터방법 |
| US7613049B2 (en) * | 2007-01-08 | 2009-11-03 | Macronix International Co., Ltd | Method and system for a serial peripheral interface |
| US20090039410A1 (en) | 2007-08-06 | 2009-02-12 | Xian Liu | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
| JP4510072B2 (ja) | 2007-12-20 | 2010-07-21 | 力晶半導体股▲ふん▼有限公司 | 不揮発性半導体記憶装置とその書き込み方法 |
| US8341330B2 (en) * | 2008-01-07 | 2012-12-25 | Macronix International Co., Ltd. | Method and system for enhanced read performance in serial peripheral interface |
| US8289760B2 (en) * | 2008-07-02 | 2012-10-16 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
| KR20100004770A (ko) * | 2008-07-04 | 2010-01-13 | 삼성전자주식회사 | 메모리 반도체 장치 |
| US8250287B1 (en) * | 2008-12-31 | 2012-08-21 | Micron Technology, Inc. | Enhanced throughput for serial flash memory, including streaming mode operations |
| US7894230B2 (en) * | 2009-02-24 | 2011-02-22 | Mosaid Technologies Incorporated | Stacked semiconductor devices including a master device |
| US8018752B2 (en) * | 2009-03-23 | 2011-09-13 | Micron Technology, Inc. | Configurable bandwidth memory devices and methods |
| US8378715B2 (en) * | 2009-04-14 | 2013-02-19 | Monolithic 3D Inc. | Method to construct systems |
| US8604593B2 (en) * | 2009-10-19 | 2013-12-10 | Mosaid Technologies Incorporated | Reconfiguring through silicon vias in stacked multi-die packages |
| US9219023B2 (en) * | 2010-01-19 | 2015-12-22 | Globalfoundries Inc. | 3D chip stack having encapsulated chip-in-chip |
| KR101710658B1 (ko) * | 2010-06-18 | 2017-02-27 | 삼성전자 주식회사 | 관통 전극을 갖는 3차원 적층 구조의 반도체 장치 및 그 반도체 장치의 시그널링 방법 |
| US20120043664A1 (en) * | 2010-08-23 | 2012-02-23 | International Business Machines Corporation | Implementing multiple different types of dies for memory stacking |
| WO2012036751A2 (en) * | 2010-09-17 | 2012-03-22 | Aplus Flash Technology, Inc. | Different types of memory integrated in one chip by using a novel protocol |
| KR20120056018A (ko) * | 2010-11-24 | 2012-06-01 | 삼성전자주식회사 | 범프들과 테스트 패드들이 십자 모양으로 배열되는 반도체 장치 |
| US9336834B2 (en) * | 2011-02-09 | 2016-05-10 | Rambus Inc. | Offsetting clock package pins in a clamshell topology to improve signal integrity |
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| JP2013134794A (ja) * | 2011-12-26 | 2013-07-08 | Elpida Memory Inc | 半導体装置 |
| US9172241B2 (en) * | 2012-03-30 | 2015-10-27 | Nvidia Corporation | Electrostatic discharge protection circuit having high allowable power-up slew rate |
| US9472284B2 (en) * | 2012-11-19 | 2016-10-18 | Silicon Storage Technology, Inc. | Three-dimensional flash memory system |
-
2013
- 2013-12-02 US US14/094,595 patent/US20150155039A1/en not_active Abandoned
-
2014
- 2014-11-06 KR KR1020167017759A patent/KR101931419B1/ko active Active
- 2014-11-06 JP JP2016536215A patent/JP6670749B2/ja active Active
- 2014-11-06 EP EP14805727.6A patent/EP3078028A1/en not_active Withdrawn
- 2014-11-06 WO PCT/US2014/064381 patent/WO2015084534A1/en not_active Ceased
- 2014-11-06 CN CN201480065987.3A patent/CN105793928B/zh active Active
- 2014-11-13 TW TW103139403A patent/TWI550926B/zh active
-
2017
- 2017-07-26 US US15/660,552 patent/US10373686B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP3078028A1 (en) | 2016-10-12 |
| WO2015084534A1 (en) | 2015-06-11 |
| KR101931419B1 (ko) | 2018-12-20 |
| CN105793928B (zh) | 2020-12-25 |
| TW201532326A (zh) | 2015-08-16 |
| CN105793928A (zh) | 2016-07-20 |
| KR20160094423A (ko) | 2016-08-09 |
| US20150155039A1 (en) | 2015-06-04 |
| TWI550926B (zh) | 2016-09-21 |
| US20170323682A1 (en) | 2017-11-09 |
| JP2017502444A (ja) | 2017-01-19 |
| US10373686B2 (en) | 2019-08-06 |
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