JP6669586B2 - 半導体装置、半導体装置の製造方法 - Google Patents

半導体装置、半導体装置の製造方法 Download PDF

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Publication number
JP6669586B2
JP6669586B2 JP2016105602A JP2016105602A JP6669586B2 JP 6669586 B2 JP6669586 B2 JP 6669586B2 JP 2016105602 A JP2016105602 A JP 2016105602A JP 2016105602 A JP2016105602 A JP 2016105602A JP 6669586 B2 JP6669586 B2 JP 6669586B2
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radiator
semiconductor element
sealing resin
heat radiator
heat
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JP2017212376A5 (enExample
JP2017212376A (ja
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健 宮入
健 宮入
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2016105602A priority Critical patent/JP6669586B2/ja
Priority to US15/600,010 priority patent/US9922902B2/en
Publication of JP2017212376A publication Critical patent/JP2017212376A/ja
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
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    • H01L21/4882—Assembly of heatsink parts
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08245—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2016105602A 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法 Active JP6669586B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016105602A JP6669586B2 (ja) 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法
US15/600,010 US9922902B2 (en) 2016-05-26 2017-05-19 Semiconductor device and semiconductor package

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JP2016105602A JP6669586B2 (ja) 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法

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JP2017212376A5 JP2017212376A5 (enExample) 2019-01-24
JP6669586B2 true JP6669586B2 (ja) 2020-03-18

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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2017056727A1 (ja) * 2015-09-29 2018-02-22 日立オートモティブシステムズ株式会社 電子制御装置
CN107993991B (zh) * 2017-12-20 2024-10-01 合肥矽迈微电子科技有限公司 一种芯片封装结构及其制造方法
US11682599B2 (en) * 2018-06-27 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
WO2020017582A1 (ja) * 2018-07-20 2020-01-23 株式会社村田製作所 モジュール
SG10201809987YA (en) * 2018-11-09 2020-06-29 Delta Electronics Int’L Singapore Pte Ltd Package structure and packaging process
JP7098574B2 (ja) * 2019-05-28 2022-07-11 矢崎総業株式会社 放熱構造
KR20210017271A (ko) * 2019-08-07 2021-02-17 삼성전기주식회사 반도체 패키지
CN110504231B (zh) * 2019-09-18 2021-03-02 北京大学东莞光电研究院 一种半导体功率器件的制备方法
US10861766B1 (en) * 2019-09-18 2020-12-08 Delta Electronics, Inc. Package structures
US11296005B2 (en) * 2019-09-24 2022-04-05 Analog Devices, Inc. Integrated device package including thermally conductive element and method of manufacturing same
JP7107295B2 (ja) * 2019-09-27 2022-07-27 株式会社デンソー 電子装置
US11557525B2 (en) * 2021-05-25 2023-01-17 Nxp Usa, Inc. Semiconductor package thermal spreader having integrated RF/EMI shielding and antenna elements
US12315776B2 (en) 2021-11-08 2025-05-27 Analog Devices, Inc. Integrated device package with an integrated heat sink
DE112023003909T5 (de) * 2022-10-21 2025-07-03 Rohm Co., Ltd. Kühlstruktur für halbleitervorrichtung
US12249554B2 (en) * 2023-02-01 2025-03-11 Toyota Motor Engineering & Manufacturing North America, Inc. Power electronic device assemblies having an electrically insulating S-cell
US20240306287A1 (en) * 2023-03-08 2024-09-12 Mellanox Technologies, Ltd. Efficient thermal management for vertical power delivery

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03180054A (ja) * 1989-12-08 1991-08-06 Matsushita Electron Corp 樹脂封止型半導体装置
JPH05259330A (ja) * 1992-03-11 1993-10-08 Hitachi Ltd 半導体装置およびその製造方法
JPH06268111A (ja) * 1993-03-15 1994-09-22 Hitachi Ltd 半導体装置
US7119434B1 (en) * 2005-07-05 2006-10-10 Delphi Technologies, Inc. Efficiency CPU cooling arrangement
JP2007165486A (ja) 2005-12-12 2007-06-28 Shinko Electric Ind Co Ltd 放熱板及び半導体装置
JP5224845B2 (ja) 2008-02-18 2013-07-03 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
JP2010263080A (ja) * 2009-05-07 2010-11-18 Denso Corp 半導体装置
JP5574170B2 (ja) * 2010-06-17 2014-08-20 株式会社デンソー 半導体モジュール実装構造
JP5891616B2 (ja) * 2011-06-28 2016-03-23 日産自動車株式会社 半導体装置
JP5898919B2 (ja) * 2011-10-31 2016-04-06 新光電気工業株式会社 半導体装置
US20130119529A1 (en) * 2011-11-15 2013-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having lid structure and method of making same
JP6048238B2 (ja) * 2012-06-04 2016-12-21 株式会社デンソー 電子装置
JP2016225413A (ja) * 2015-05-28 2016-12-28 株式会社ジェイテクト 半導体モジュール

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