JP6651894B2 - 化合物半導体装置およびその製造方法 - Google Patents

化合物半導体装置およびその製造方法 Download PDF

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JP6651894B2
JP6651894B2 JP2016032292A JP2016032292A JP6651894B2 JP 6651894 B2 JP6651894 B2 JP 6651894B2 JP 2016032292 A JP2016032292 A JP 2016032292A JP 2016032292 A JP2016032292 A JP 2016032292A JP 6651894 B2 JP6651894 B2 JP 6651894B2
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JP2017152489A5 (enExample
JP2017152489A (ja
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竹内　有一
有一 竹内
敦也 秋葉
敦也 秋葉
鈴木　克己
克己 鈴木
佐智子 青井
佐智子 青井
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Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
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Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
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Priority to DE112017000947.2T priority patent/DE112017000947T5/de
Priority to US16/070,061 priority patent/US10643851B2/en
Priority to PCT/JP2017/000799 priority patent/WO2017145548A1/ja
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    • H—ELECTRICITY
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
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    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
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JP2016032292A 2016-02-23 2016-02-23 化合物半導体装置およびその製造方法 Expired - Fee Related JP6651894B2 (ja)

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JP2016032292A JP6651894B2 (ja) 2016-02-23 2016-02-23 化合物半導体装置およびその製造方法
DE112017000947.2T DE112017000947T5 (de) 2016-02-23 2017-01-12 Verbindungshalbleitervorrichtung und herstellungsverfahren für dieverbindungshalbleitervorrichtung
US16/070,061 US10643851B2 (en) 2016-02-23 2017-01-12 Compound semiconductor device and production method for the same
PCT/JP2017/000799 WO2017145548A1 (ja) 2016-02-23 2017-01-12 化合物半導体装置およびその製造方法

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JP2016032292A JP6651894B2 (ja) 2016-02-23 2016-02-23 化合物半導体装置およびその製造方法

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JP2017152489A5 JP2017152489A5 (enExample) 2018-06-21
JP6651894B2 true JP6651894B2 (ja) 2020-02-19

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Publication number Priority date Publication date Assignee Title
US10937874B2 (en) * 2016-08-10 2021-03-02 Nissan Motor Co., Ltd. Semiconductor device
JP6673232B2 (ja) * 2017-01-17 2020-03-25 株式会社デンソー 炭化珪素半導体装置
JP7379880B2 (ja) * 2019-06-21 2023-11-15 富士電機株式会社 半導体装置
JP7354029B2 (ja) * 2020-03-13 2023-10-02 株式会社東芝 半導体装置、半導体装置の製造方法、電源回路、及び、コンピュータ
CN113921394A (zh) * 2020-07-08 2022-01-11 上海贝岭股份有限公司 超级势垒整流器的制备方法以及超级势垒整流器
WO2022202936A1 (ja) * 2021-03-24 2022-09-29 株式会社デンソー 炭化珪素半導体装置およびそれを用いたインバータ回路、炭化珪素半導体装置の製造方法
JP7807629B2 (ja) * 2022-03-25 2026-01-28 株式会社Flosfia 半導体装置
JP7694816B2 (ja) * 2022-04-14 2025-06-18 株式会社デンソー 半導体装置とその製造方法
EP4391065A1 (en) * 2022-12-22 2024-06-26 Imec VZW Shielding structure for a vertical iii-nitride semiconductor device
JP2025129940A (ja) * 2024-02-26 2025-09-05 ミネベアパワーデバイス株式会社 半導体装置

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JP4453671B2 (ja) * 2006-03-08 2010-04-21 トヨタ自動車株式会社 絶縁ゲート型半導体装置およびその製造方法
JP4683075B2 (ja) * 2008-06-10 2011-05-11 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP5482745B2 (ja) * 2011-08-10 2014-05-07 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP5582112B2 (ja) * 2011-08-24 2014-09-03 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP2013145770A (ja) * 2012-01-13 2013-07-25 Sumitomo Electric Ind Ltd 半導体装置およびその製造方法
JP5884617B2 (ja) * 2012-04-19 2016-03-15 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP5751213B2 (ja) * 2012-06-14 2015-07-22 株式会社デンソー 炭化珪素半導体装置およびその製造方法
US9318600B2 (en) * 2013-04-16 2016-04-19 Panasonic Intellectual Property Management Co., Ltd. Silicon carbide semiconductor device and method for manufacturing same
JP6048317B2 (ja) 2013-06-05 2016-12-21 株式会社デンソー 炭化珪素半導体装置
JP6341074B2 (ja) * 2014-01-24 2018-06-13 株式会社デンソー 半導体装置の製造方法
EP2977989B1 (en) 2014-07-25 2019-05-08 IMEC vzw Sample-and-hold circuit for an interleaved analog-to-digital converter
US9768284B2 (en) * 2015-03-05 2017-09-19 Infineon Technologies Americas Corp. Bipolar semiconductor device having a charge-balanced inter-trench structure

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DE112017000947T5 (de) 2018-10-31
US10643851B2 (en) 2020-05-05
JP2017152489A (ja) 2017-08-31
US20190019680A1 (en) 2019-01-17
WO2017145548A1 (ja) 2017-08-31

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