JP2013222855A - 炭化珪素半導体装置の製造方法 - Google Patents
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000137 annealing Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 110
- 239000000758 substrate Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 19
- 230000004913 activation Effects 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 15
- 239000012535 impurity Substances 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000013459 approach Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Abstract
【解決手段】第2ゲート領域8が備えられるトレンチ6の両先端部においてJFET構造が形成されないように凹部13を形成する構造とする。そして、このような構造において、アニール処理時に凹部13の底面と側面との境界部となる角部に形成されるn型層16を除去する。これにより、n型層16が残されている場合のように、異なる導電型であるn型層16とp+型の第1ゲート領域3もしくは第2ゲート領域8との間に形成されていた高濃度接合が形成されないようにできる。したがって、ドレイン電位が第1ゲート領域3上に表出して、ゲート−ドレイン間耐圧を低下させてしまうことを防止でき、高濃度接合リーク(ゲートリークやドレインリーク)が発生することを防止することができる。
【選択図】図6
Description
本発明の第1実施形態にかかるJFETを備えたSiC半導体装置について説明する。図1〜図4に示すJFETを備えたSiC半導体装置は、n+型SiC基板1を用いて構成されている。n+型SiC基板1としては、例えばオフ基板を用いることができるが、n+型SiC基板1に形成されるJFETのセルのレイアウトとオフ方向については無関係であり、JFETのセルのレイアウトをオフ方向に合わせる必要はない。
上記各実施形態では、n-型チャネル層7にチャネル領域が設定されるnチャネルタイプのJFETを例に挙げて説明したが、各構成要素の導電型を逆にしたpチャネルタイプのJFETに対しても本発明を適用することができる。
2 n-型ドリフト層
3 第1ゲート領域
4 n+型ソース領域
5 半導体基板
6 トレンチ
7 n-型チャネル層
8 第2ゲート領域
9 ゲート電極
11 ソース電極
12 ドレイン電極
13、14 凹部(第1、第2凹部)
16、17 n型層
Claims (4)
- 炭化珪素からなる第1導電型基板(1)と、前記第1導電型基板上にエピタキシャル成長によって形成された第1導電型のドリフト層(2)と、前記ドリフト層上にエピタキシャル成長によって形成された第2導電型の第1ゲート領域(3)と、前記第1ゲート領域上にエピタキシャル成長もしくはイオン注入により形成された第1導電型のソース領域(4)とを有する半導体基板(5)を用意する工程と、
前記ソース領域および前記第1ゲート領域を貫通して前記ドリフト層まで達し、一方向を長手方向とした短冊状のトレンチ(6)を形成する工程と、
前記トレンチの内壁上にエピタキシャル成長によって第1導電型のチャネル層(7)を形成する工程と、
前記チャネル層の上に形成された第2導電型の第2ゲート領域(8)を形成する工程と、
前記チャネル層および前記第2ゲート領域を前記ソース領域が露出するまで平坦化する工程と、
前記平坦化の後に、選択エッチングを行うことで少なくとも前記トレンチの両先端部の前記ソース領域と前記チャネル層および前記第2ゲート領域を除去し、前記トレンチの両先端部に前記ソース領域の厚みよりも深い第1凹部(13)を形成する工程と、
前記第1凹部の形成後に、不活性ガス雰囲気において1300℃以上の活性化アニール処理を行う工程と、
前記アニール処理によって前記第1凹部の底面と側面との境界部となる角部を覆うように形成される第1導電型層(16)を除去する工程と、を含むことを特徴とするJFETを備える炭化珪素半導体装置の製造方法。 - 前記第1導電型層(16)を除去する工程は、前記第1凹部の内部を含む前記半導体基板の表面全面を前記第1導電型層(16)の膜厚以上の深さエッチングしつつ、前記第1凹部の底面において前記第1ゲート領域が除去されてなくならない深さエッチングを行う表面エッチング工程であることを特徴とする請求項1に記載のJFETを備える炭化珪素半導体装置の製造方法。
- 前記第1導電型層(16)を除去する工程を行った後、前記第1凹部内を含めて層間絶縁膜(10)を形成する工程を含んでいることを特徴とする請求項1または2に記載のJFETを備える炭化珪素半導体装置の製造方法。
- 前記JFETのセルが形成されたセル領域を囲む外周領域に、前記第1ゲート領域よりも深く前記ドリフト層に達する第2凹部(14)を形成する工程と、
前記第2凹部の側面から底面に至るように前記ドリフト層内に第2導電型のリサーフ層(15)を形成する工程とを含み、
前記リサーフ層を形成する工程の後に、前記活性化アニール処理を行うと共に、該活性化アニール処理の後に前記第1導電型層(16)を除去する際に、前記活性化アニール処理によって前記第2凹部の底面と側面との境界となる角部を覆うように形成される第1導電型層(17)についても除去することを特徴とする請求項1ないし3のいずれか1つに記載のJFETを備える炭化珪素半導体装置の製造方法。
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JP2012094110A JP5692145B2 (ja) | 2012-04-17 | 2012-04-17 | 炭化珪素半導体装置の製造方法 |
PCT/JP2013/002434 WO2013157225A1 (ja) | 2012-04-17 | 2013-04-10 | 炭化珪素半導体装置の製造方法 |
EP13778761.0A EP2840595A4 (en) | 2012-04-17 | 2013-04-10 | METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR ELEMENT |
US14/394,115 US9450068B2 (en) | 2012-04-17 | 2013-04-10 | Method for manufacturing silicon carbide semiconductor device |
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US6855970B2 (en) | 2002-03-25 | 2005-02-15 | Kabushiki Kaisha Toshiba | High-breakdown-voltage semiconductor device |
JP4153811B2 (ja) * | 2002-03-25 | 2008-09-24 | 株式会社東芝 | 高耐圧半導体装置及びその製造方法 |
JP4206803B2 (ja) * | 2003-04-07 | 2009-01-14 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
SE527205C2 (sv) | 2004-04-14 | 2006-01-17 | Denso Corp | Förfarande för tillverkning av halvledaranordning med kanal i halvledarsubstrat av kiselkarbid |
JP5044117B2 (ja) * | 2005-12-14 | 2012-10-10 | 関西電力株式会社 | 炭化珪素バイポーラ型半導体装置 |
JP5326405B2 (ja) * | 2008-07-30 | 2013-10-30 | 株式会社デンソー | ワイドバンドギャップ半導体装置 |
JP5170074B2 (ja) * | 2009-12-25 | 2013-03-27 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP5607947B2 (ja) | 2010-02-17 | 2014-10-15 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5582112B2 (ja) | 2011-08-24 | 2014-09-03 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
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EP2840595A1 (en) | 2015-02-25 |
US20150072486A1 (en) | 2015-03-12 |
JP5692145B2 (ja) | 2015-04-01 |
WO2013157225A1 (ja) | 2013-10-24 |
US9450068B2 (en) | 2016-09-20 |
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