JP6620656B2 - 集積回路 - Google Patents
集積回路 Download PDFInfo
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- JP6620656B2 JP6620656B2 JP2016084659A JP2016084659A JP6620656B2 JP 6620656 B2 JP6620656 B2 JP 6620656B2 JP 2016084659 A JP2016084659 A JP 2016084659A JP 2016084659 A JP2016084659 A JP 2016084659A JP 6620656 B2 JP6620656 B2 JP 6620656B2
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Description
図1および図2は、本発明の実施の形態1に係る集積回路の平面図である。図1に示すように、本実施の形態に係る集積回路100は、入力パッド32を備える。入力パッド32は、第1増幅段40aの入力と接続される。第1増幅段40aの入力は、第1入力整合回路28aの入力と接続される。第1入力整合回路28aの出力は、増幅素子である第1トランジスタ12aに入力される。第1トランジスタ12aの出力は、第1出力整合回路36aと接続される。第1出力整合回路36aとの出力は、第1増幅段40aの出力と接続される。第1増幅段40aの出力は、第1信号線路42aと接続される。
図22Aは、本発明の実施の形態2に係る集積回路の平面図である。本実施の形態に係る集積回路500は、グランドプレーン間がグランドラインの代わりにスパイラルインダクタによって接続される。第1増幅段40aには第1グランドプレーン520aが接続される。第2増幅段40bには第2グランドプレーン520bが接続される。第3増幅段40cには第3グランドプレーン520cが接続される。第1グランドプレーン520aと第2グランドプレーン520bの間は第1スパイラルインダクタ46aによって接続される。第2グランドプレーン520bと第3グランドプレーン520cの間は第2スパイラルインダクタ46bによって接続される。
図23Aは、本発明の実施の形態3に係る集積回路の平面図である。図23Bは、本発明の実施の形態3に係る集積回路の等価回路図である。本実施の形態に係る集積回路600は、グランドラインが信号線路と重なるように配置される。第1グランドライン630aは、第1信号線路42aと重なるように配置される。第2グランドライン630bは、第2信号線路42bと重なるように配置される。
図25Aは、本発明の実施の形態4に係る集積回路の平面図である。本実施の形態では、グランドラインの代わりに、グランドプレーン間が抵抗素子で接続される。第1グランドプレーン720aと第2グランドプレーン720bの間は第1抵抗素子730aによって接続される。第2グランドプレーン720bと第3グランドプレーン720cの間は第2抵抗素子730bによって接続される。
Claims (7)
- 第1増幅段と、
第2増幅段と、
前記第1増幅段の出力と前記第2増幅段の入力を接続する第1信号線路と、
前記第1増幅段と平面視で重なり、前記第1増幅段に接続された第1グランドプレーンと、
前記第2増幅段と平面視で重なり、前記第2増幅段に接続された第2グランドプレーンと、
前記第1グランドプレーンと前記第2グランドプレーンの平面視で互いに対向する辺を接続する1つまたは複数のグランドラインと、
を備え、
前記グランドラインは中心線の長さが10μm以上1mm以下であり、前記1つまたは複数のグランドラインの幅の和である幅の総和は前記第1グランドプレーンの幅の3分の1以下であり、前記中心線の長さを前記幅の総和で除した値であるパターン比は1以上であり、
前記第1グランドプレーンの幅は、前記グランドラインの取り出し方向に対して垂直方向の最大寸法であることを特徴とする集積回路。 - 前記第1増幅段および前記第2増幅段は、単相入力および単相出力であることを特徴とする請求項1に記載の集積回路。
- 前記第1増幅段、前記第2増幅段および前記第1信号線路が前記第1グランドプレーンおよび第2グランドプレーンと対向する表面に配置された半導体基板と、
前記第1増幅段、前記第2増幅段および前記第1信号線路と、前記第1グランドプレーンおよび前記第2グランドプレーンとの間に配置された誘電体膜と、
前記誘電体膜を貫通して前記第1増幅段と前記第1グランドプレーンを接続する第1接続構造と、前記誘電体膜を貫通して前記第2増幅段と前記第2グランドプレーンを接続する第2接続構造と、
を備えることを特徴とする請求項1または2に記載の集積回路。 - 前記誘電体膜上に、前記第1グランドプレーンと前記第2グランドプレーンが、前記第1増幅段及び前記第2増幅段とを覆うように、前記半導体基板に対して最表面側に配置されたことを特徴とする請求項3に記載の集積回路。
- 前記グランドラインは、前記第1信号線路に重なるように配置され、
前記グランドラインと前記第1信号線路の間には誘電体膜が配置され、
前記グランドライン、前記誘電体膜および前記第1信号線路は第1マイクロストリップ線路を形成することを特徴とする請求項1〜4の何れか1項に記載の集積回路。 - 前記グランドラインは、第1スパイラルインダクタを備えることを特徴とする請求項1〜4の何れか1項に記載の集積回路。
- 前記グランドラインは、抵抗値が10Ω以上である第1抵抗素子を備えることを特徴とする請求項1〜4の何れか1項に記載の集積回路。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016084659A JP6620656B2 (ja) | 2016-04-20 | 2016-04-20 | 集積回路 |
US15/387,755 US10027282B2 (en) | 2016-04-20 | 2016-12-22 | Integrated circuit |
DE102017204654.6A DE102017204654B4 (de) | 2016-04-20 | 2017-03-21 | Integrierte schaltung |
KR1020170050169A KR101909815B1 (ko) | 2016-04-20 | 2017-04-19 | 집적 회로 |
CN201710263586.4A CN107305880B (zh) | 2016-04-20 | 2017-04-20 | 集成电路 |
Applications Claiming Priority (1)
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US5010588A (en) * | 1988-03-10 | 1991-04-23 | Bell Communications Research, Inc. | Ultrawide-bandwidth low-noise optical receiver |
JPH11284401A (ja) * | 1998-03-30 | 1999-10-15 | Matsushita Electric Ind Co Ltd | 高周波回路装置 |
JP2001156242A (ja) | 1999-11-25 | 2001-06-08 | Mitsubishi Electric Corp | 多段増幅装置 |
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US9300260B2 (en) * | 2013-03-15 | 2016-03-29 | Rf Micro Devices, Inc. | Transformer-based power amplifier stabilization and reference distortion reduction |
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