JP6350513B2 - 配線基板、半導体装置、プリント基板及び配線基板の製造方法 - Google Patents
配線基板、半導体装置、プリント基板及び配線基板の製造方法 Download PDFInfo
- Publication number
- JP6350513B2 JP6350513B2 JP2015502760A JP2015502760A JP6350513B2 JP 6350513 B2 JP6350513 B2 JP 6350513B2 JP 2015502760 A JP2015502760 A JP 2015502760A JP 2015502760 A JP2015502760 A JP 2015502760A JP 6350513 B2 JP6350513 B2 JP 6350513B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- thin film
- magnetic thin
- wiring board
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0233—Filters, inductors or a magnetic substance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/08—Magnetic details
- H05K2201/083—Magnetic materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/08—Magnetic details
- H05K2201/083—Magnetic materials
- H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
第1の実施形態に係るインターポーザ基板31においては、電源配線13を被覆するように磁性薄膜17を設けている。
第2の実施形態に係るインターポーザ基板31においては、グランド配線14を被覆するように磁性薄膜17を設けている点で第1の実施形態と異なる。
第3の実施形態に係るインターポーザ基板31においては、電源配線13及びグランド配線14を被覆するように磁性薄膜17を設けている。
実施例1では、図9Bに示すように、電源配線13及びグランド配線14の上に磁性薄膜17として厚さ3μmのフェライト膜をめっき法により形成した例を示す。
実施例2では、図9Bに示すように、電源配線13及びグランド配線14の上に磁性薄膜17として厚さ30μmの樹脂磁性体複合膜をスクリーン印刷法により形成した例を示す。
比較例は、図9Aに示すように、電源配線13及びグランド配線14の上に磁性薄膜17を形成しない場合である。比較例では、電源配線13及びグランド配線14上に磁性薄膜17を設けていないため、伝導ノイズの抑制対策を行っていない場合を示している。
図10には、実施例1、2及び比較例のインターポーザ基板表面における電源−グランド配線間の透過特性を示した。
12 信号配線
13 電源配線
14 グランド配線
17 磁性薄膜
19 ボンディング用パッド
32 LSIチップ
35 ボンディングワイヤ
30 プリント基板
31 インターポーザ基板
37 はんだボール
33 プリント配線板
41 LSI側パターン
43 LSI側配線
45 ボンディング用パッド
47 ビア
51 プリント配線板側パターン
53 プリント配線板側配線
55 はんだボール用パッド
100 プリント基板
101 プリント配線板
102 電源プレーン
103 グランドプレーン
104 EBG構造
105 高インピーダンス面
106 ビア
107 LSIパッケージ
Claims (10)
- 集積回路を含む電子部品をプリント配線板に実装する際に介在させる配線基板であって、
前記電子部品からの信号を伝送する信号配線と、
前記電子部品へ電源電圧を供給する電源配線と、を有し、
前記電源配線を磁性薄膜で直接被覆し、前記信号配線には前記磁性薄膜を設けないことにより、前記磁性薄膜は、前記信号配線と一定の間隔をあけて配置されることを特徴とする配線基板。 - 前記信号配線と前記磁性薄膜との最近接箇所が特定の距離以上離れていることを特徴とする請求項1に記載の配線基板。
- 前記磁性薄膜は、前記信号配線に沿って一定の距離となるように形成されていることを特徴とする請求項1または2に記載の配線基板。
- 前記信号配線と前記磁性薄膜とは、少なくとも前記信号配線の幅の長さの半分以上の間隔をあけていることを特徴とする請求項1乃至3のいずれか一項に記載の配線基板。
- 前記磁性薄膜は、フェライトを含む材料からなることを特徴とする請求項1乃至4のいずれか一項に記載の配線基板。
- 前記磁性薄膜は、樹脂中に磁性粒子を分散させた樹脂磁性体複合膜であることを特徴とする請求項1乃至4のいずれか一項に記載の配線基板。
- 請求項1乃至6のいずれかに記載の配線基板に前記電子部品を実装したことを特徴とする半導体装置。
- 請求項1乃至6のいずれかに記載の配線基板を介在させて、前記電子部品を前記プリント配線板に実装したことを特徴とするプリント基板。
- 集積回路を含む電子部品をプリント配線板上に実装する際に介在させる配線基板の製造方法であって、
前記電子部品からの信号を伝送する信号配線と、前記電子部品へ電源電圧を供給する電源配線と、を形成する工程と、
磁性薄膜と前記信号配線とが一定の間隔をあけて配置されるように、前記電源配線を前記磁性薄膜で直接被覆する工程と、を有することを特徴とする配線基板の製造方法。 - 前記磁性薄膜の形成工程において、前記信号配線に沿って一定の距離となるように、前記電源配線を前記磁性薄膜で直接被覆することを特徴とする請求項9に記載の配線基板の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013036938 | 2013-02-27 | ||
JP2013036938 | 2013-02-27 | ||
PCT/JP2014/000948 WO2014132610A1 (ja) | 2013-02-27 | 2014-02-24 | 配線基板、半導体装置、プリント基板及び配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2014132610A1 JPWO2014132610A1 (ja) | 2017-02-02 |
JP6350513B2 true JP6350513B2 (ja) | 2018-07-04 |
Family
ID=51427889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015502760A Active JP6350513B2 (ja) | 2013-02-27 | 2014-02-24 | 配線基板、半導体装置、プリント基板及び配線基板の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20160029477A1 (ja) |
JP (1) | JP6350513B2 (ja) |
WO (1) | WO2014132610A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6662102B2 (ja) * | 2016-02-29 | 2020-03-11 | 富士ゼロックス株式会社 | 光学装置の製造方法、基板装置、光学装置及び光学装置の製造装置 |
JP2019039870A (ja) * | 2017-08-28 | 2019-03-14 | ファナック株式会社 | 検出装置 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03126099U (ja) * | 1990-04-02 | 1991-12-19 | ||
JPH04352498A (ja) * | 1991-05-30 | 1992-12-07 | Mitsui Toatsu Chem Inc | 高透磁率を有する電磁シールド用絶縁ペースト |
US5729047A (en) * | 1996-03-25 | 1998-03-17 | Micron Technology, Inc. | Method and structure for providing signal isolation and decoupling in an integrated circuit device |
JP3055488B2 (ja) * | 1997-03-03 | 2000-06-26 | 日本電気株式会社 | 多層プリント基板及びその製造方法 |
JPH1154861A (ja) * | 1997-08-04 | 1999-02-26 | Sony Corp | 配線基板 |
JPH1197810A (ja) * | 1997-09-17 | 1999-04-09 | Toshiba Corp | 回路基板 |
JP3214472B2 (ja) * | 1998-12-04 | 2001-10-02 | 日本電気株式会社 | 多層プリント回路基板 |
JP2001135900A (ja) * | 1999-11-05 | 2001-05-18 | Tdk Corp | プリント回路基板 |
SG100666A1 (en) * | 2000-04-04 | 2003-12-26 | Nec Tokin Corp | Wiring board comprising granular magnetic film |
KR100533097B1 (ko) * | 2000-04-27 | 2005-12-02 | 티디케이가부시기가이샤 | 복합자성재료와 이것을 이용한 자성성형재료, 압분 자성분말성형재료, 자성도료, 복합 유전체재료와 이것을이용한 성형재료, 압분성형 분말재료, 도료, 프리프레그및 기판, 전자부품 |
US7235457B2 (en) * | 2002-03-13 | 2007-06-26 | Micron Technology, Inc. | High permeability layered films to reduce noise in high speed interconnects |
US6846738B2 (en) * | 2002-03-13 | 2005-01-25 | Micron Technology, Inc. | High permeability composite films to reduce noise in high speed interconnects |
US6970053B2 (en) * | 2003-05-22 | 2005-11-29 | Micron Technology, Inc. | Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection |
TWI295102B (en) * | 2006-01-13 | 2008-03-21 | Ind Tech Res Inst | Multi-functional substrate structure |
US7843302B2 (en) * | 2006-05-08 | 2010-11-30 | Ibiden Co., Ltd. | Inductor and electric power supply using it |
US8134084B2 (en) * | 2006-06-30 | 2012-03-13 | Shin-Etsu Polymer Co., Ltd. | Noise-suppressing wiring-member and printed wiring board |
JP5429630B2 (ja) * | 2007-03-16 | 2014-02-26 | 日本電気株式会社 | 伝送線路フィルタ |
JP5103088B2 (ja) * | 2007-08-02 | 2012-12-19 | 信越ポリマー株式会社 | 伝導ノイズ抑制構造体および配線回路基板 |
TWI379621B (en) * | 2007-08-02 | 2012-12-11 | Shinetsu Polymer Co | Conductive noise suppressing structure and wiring circuit substrate |
JP5082060B2 (ja) * | 2008-05-22 | 2012-11-28 | 学校法人明星学苑 | 低特性インピーダンス電源・グランドペア線路構造 |
JP5131861B2 (ja) * | 2009-08-25 | 2013-01-30 | Necトーキン株式会社 | リードフレーム及びインターポーザ |
JP5872801B2 (ja) * | 2011-06-22 | 2016-03-01 | Necトーキン株式会社 | インターポーザ |
JP2015192555A (ja) * | 2014-03-28 | 2015-11-02 | 株式会社東芝 | 半導体装置 |
JP6497649B2 (ja) * | 2015-01-30 | 2019-04-10 | 国立大学法人 岡山大学 | 印刷配線板およびその製造方法 |
-
2014
- 2014-02-24 JP JP2015502760A patent/JP6350513B2/ja active Active
- 2014-02-24 US US14/766,898 patent/US20160029477A1/en not_active Abandoned
- 2014-02-24 WO PCT/JP2014/000948 patent/WO2014132610A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2014132610A1 (ja) | 2014-09-04 |
US20160029477A1 (en) | 2016-01-28 |
JPWO2014132610A1 (ja) | 2017-02-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI634639B (zh) | 電子電路封裝 | |
US10170431B2 (en) | Electronic circuit package | |
US9966343B2 (en) | Electronic circuit package | |
US10269726B2 (en) | Electronic circuit package | |
US9768154B2 (en) | Semiconductor package and manufacturing method therefor | |
TWI606472B (zh) | 使用複合磁性密封材料之電子電路封裝 | |
US10879142B2 (en) | Electronic component | |
US20130215587A1 (en) | Multilayer wiring board and electronic device | |
JP2017199896A (ja) | 電子回路パッケージ | |
TW201616632A (zh) | 半導體封裝元件 | |
US9713259B2 (en) | Communication module | |
US20150123251A1 (en) | Semiconductor package | |
JPWO2009050843A1 (ja) | 電子デバイス | |
TW201515530A (zh) | 電路板高頻信號連接墊的抗衰減結構 | |
JP6350513B2 (ja) | 配線基板、半導体装置、プリント基板及び配線基板の製造方法 | |
JP2018019057A (ja) | 電子回路パッケージ | |
US10149417B2 (en) | Magnetism suppressing sheet and manufacturing method thereof | |
US20140339688A1 (en) | Techniques for the cancellation of chip scale packaging parasitic losses | |
JP4309433B2 (ja) | 半導体装置 | |
KR101607065B1 (ko) | 공통 모드 필터 및 그 제조 방법 | |
JP6318761B2 (ja) | 半導体モジュール | |
JP2008159752A (ja) | 半導体装置 | |
TWM467555U (zh) | 可抗電磁波之積層結構 | |
JP6269233B2 (ja) | 半導体モジュール | |
KR20150083340A (ko) | 공통 모드 필터 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170116 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20171219 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180129 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180508 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180521 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6350513 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |