JP6324738B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6324738B2 JP6324738B2 JP2014012155A JP2014012155A JP6324738B2 JP 6324738 B2 JP6324738 B2 JP 6324738B2 JP 2014012155 A JP2014012155 A JP 2014012155A JP 2014012155 A JP2014012155 A JP 2014012155A JP 6324738 B2 JP6324738 B2 JP 6324738B2
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
図1は本実施の形態の半導体装置の斜視図、図2は、図1に示す半導体装置の下面図である。また、図3は、図1に示す放熱板を取り除いた状態で配線基板上の半導体装置の内部構造を示す透視平面図である。また、図4は図1のA−A線に沿った断面図である。なお、図1〜図4では、見易さのため、端子数を少なくして示している。また、図4では、見易さのため、図2に示す例よりも半田ボール4の数を少なくして示している。図示は省略するが、端子(ボンディングパッド2PD、ランド2LD、半田ボール4)の数は、図1〜図4に示す態様以外にも種々の変形例が適用できる。
まず、本実施の形態の半導体装置1の概要構成について、図1〜図4を用いて説明する。本実施の形態の半導体装置1は、配線基板2、および配線基板2上に搭載された半導体チップ3(図4参照)を備えている。
次に、図1〜図4に示す配線基板2のうち、信号伝送経路の配線構造について説明する。図5は、ストリップラインの配線構造例を示す拡大断面図である。また図6は、マイクロストリップラインの配線構造例を示す拡大断面図である。また、図7は、本実施の形態の電磁波吸収体である導体パターンの平面形状の例を示す拡大平面図である。また、図8は、図7に点線で示す配線の延在方向に沿った拡大断面図である。
次に、図7および図8を用いて説明した電磁波吸収体である導体パターンMP1を配置する位置について説明する。図9は、図8とは異なる位置における拡大断面図である。また、図10は、図9に示す拡大断面における導体パターンの要部構造を示す拡大斜視図である。また、図11は、図9に対する変形例を示す拡大断面図である。
次に、図1〜図4に示す半導体装置1の製造方法(組立工程)について、図15に示すフロー図を用いて説明する。図15は、図1〜図4に示す半導体装置の組立工程のフローを示す説明図である。なお、以下の製造方法の説明においては、予め製品サイズに形成された配線基板2を準備して、一つの半導体装置1を製造する方法について説明する。しかし、変形例としては、複数の製品形成領域に区画された、所謂、多数個取り基板を準備して、複数の製品形成領域のそれぞれについて組立を行ったあと、製品形成領域毎に分割して複数の半導体装置を取得する、多数個取り方式にも適用できる。このため、図15では、多数個取り方式の時に適用する個片化工程について、括弧書きで記載している。
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。上記実施の形態では、既にいくつかの変形例について説明したが、以下では上記実施の形態に対する代表的な変形例を挙げて説明する。
(a)チップ搭載面、前記チップ搭載面の反対側に位置する実装面、前記チップ搭載面に配置される複数の第1端子、前記実装面に配置される複数の第2端子、および前記複数の第1端子と前記複数の第2端子を電気的に接続する複数層の配線層を有する配線基板を準備する工程、
(b)複数の電極パッドが形成された表面、および前記表面の反対側に位置する裏面を有する半導体チップを前記配線基板の前記チップ搭載面に搭載し、前記半導体チップの前記複数の電極パッドと前記配線基板の前記複数の第1端子とをそれぞれ電気的に接続する工程、
を含み、
前記複数層の配線層は、第1信号が伝送される第1配線が形成された第1配線層と、前記第1配線層の上層または下層に隣接して設けられた第2配線層と、を含み、
前記第2配線層には、前記第1配線の一部と厚さ方向に重なる位置に第1開口部を有する第1導体板、および前記第1導体板の前記第1開口部内に配置された第1導体パターンが形成され、
前記第1開口部は、前記第1導体板を厚さ方向に貫通するように形成され、
前記第1導体パターンは、前記第1導体板と離間するメッシュパターン部、および前記メッシュパターン部と前記第1導体板とを連結する複数の連結部を有する、半導体装置の製造方法。
2、2A、2B、2D、2E、2F、2G 配線基板
2a 上面(第1面、チップ搭載面)
2b 下面(第2面、実装面)
2Ca 上面
2Cb 下面
2CR 絶縁層(コア層、コア材、コア絶縁層)
2d、2d1、2d2、2d3、2d4 配線
2e 絶縁層(ビルドアップ層)
2LD ランド(端子、外部端子、電極、外部電極)
2PD ボンディングパッド(端子、半導体チップ接続用端子)
2PL 導体プレーン(導体板)
2s 側面
2TL スルーホールランド
2TW スルーホール配線
2V ビア配線
3 半導体チップ
3a 表面(主面、上面)
3b 裏面(主面、下面)
3BP 突起電極
3PD パッド(ボンディングパッド)
3s 側面
4 半田ボール(半田材、端子、外部端子、電極、外部電極)
5 アンダフィル樹脂(絶縁性樹脂)
LS 長辺
MP1 導体パターン(金属パターン)
MPh 開口部
MPj、MPjs、MPjx、MPjy 連結部
MPm 本体部(メッシュパターン部)
MSK マスク
PLh 開口部
SS 短辺
VLx、VLy 仮想線
WL、WL1、WL2、WL3、WL4、WL5、WL6、WL7、WL8、WL9、WL10 配線層
Claims (16)
- 複数の電極パッドが形成された表面、および前記表面の反対側に位置する裏面を有する半導体チップと、
前記半導体チップが搭載されたチップ搭載面、前記チップ搭載面の反対側に位置する実装面、前記チップ搭載面に配置され、前記半導体チップの前記複数の電極パッドと電気的に接続される複数の第1端子、前記実装面に配置される複数の第2端子、および前記複数の第1端子と前記複数の第2端子を電気的に接続する複数層の配線層を有する配線基板と、
を有し、
前記配線基板は、
前記配線基板の前記チップ搭載面側に位置する第1面、および前記第1面の反対側の第2面を有するコア層と、
前記コア層の前記第1面および前記第2面のうち、一方から他方までを貫通するスルーホール配線と、
前記第1面において、前記スルーホール配線に接続される第1スルーホールランドと、
を有し、
前記複数層の配線層は、第1信号が伝送される第1配線を備える第1配線層と、基準電位が供給される第1導体板を備え、かつ、前記第1配線層の上層に隣接して設けられた第2配線層と、前記第1配線に接続される前記第1スルーホールランドを備え、かつ、前記第1配線層の下層に隣接して設けられた第3配線層と、を含み、
前記第2配線層の前記第1導体板は、平面視において前記第1スルーホールランドおよび前記第1配線の一部と重なる位置に、前記第1導体板を厚さ方向に貫通するように形成された第1開口部を備え、
前記第1導体板の前記第1開口部内に配置された第1導体パターンは、前記第1導体板と離間するメッシュパターン部、および前記メッシュパターン部と前記第1導体板とを連結する複数の連結部を有し、
平面視において、前記第1配線は、前記第1導体板の前記メッシュパターン部、および前記第1導体板の前記第1開口部が形成されていない領域、のそれぞれと重なり、
平面視において、前記第1導体板の前記メッシュパターン部は、前記第1スルーホールランドと重なる、半導体装置。 - 請求項1において、
前記複数の連結部は、
平面視において、第1方向に沿って前記第1開口部の中心を通る第1仮想線に沿って前記メッシュパターン部を挟むように配置される二個の第1連結部と、
平面視において、前記第1方向と直交する第2方向に沿って前記第1開口部の中心を通る第2仮想線に沿って前記メッシュパターン部を挟むように配置される二個の第2連結部と、
を含む、半導体装置。 - 請求項2において、
前記複数の連結部は、
平面視において、前記二個の第1連結部および前記二個の第2連結部のうち、隣り合う第1連結部と第2連結部のそれぞれの間に配置される複数の第3連結部をさらに含む、半導体装置。 - 請求項3において、
前記複数の第3連結部のそれぞれは、前記第1方向および前記第2方向に対して、45度の方向に延びる、半導体装置。 - 請求項4において、
前記第1配線は、平面視において、複数の屈曲部を有し、前記複数の屈曲部の角度は、それぞれ45度の倍数になっている、半導体装置。 - 請求項3において、
前記第1、第2および第3連結部は、互いの離間距離が揃うように配置される、半導体装置。 - 請求項1において、
前記第1導体パターンの平面形状は、前記第1開口部の中心に対して点対称である、半導体装置。 - 請求項1において、
前記第1導体パターンの平面形状は、前記第1開口部の中心を通る中心線に対して線対称である、半導体装置。 - 請求項1において、
前記第1配線は、平面視において、前記複数の連結部のうちの一つに沿って延びる、半導体装置。 - 請求項1において、
前記第1配線は、平面視において、前記複数の連結部のうちの一つと重なる、半導体装置。 - 請求項1において、
前記複数層の配線層は、前記第2配線層に隣接し、かつ前記第1配線層とは異なる第4配線層をさらに含み、
前記第4配線層には、前記第1信号とは異なる第2信号が伝送される第2配線が形成され、
平面視において、前記第2配線の一部は、前記第1導体パターンと重なる、半導体装置。 - 請求項1において、
前記第1導体パターンの前記メッシュパターン部は、長方形の開口形状である複数の第2開口部が規則的に配置される、半導体装置。 - 請求項12において、
前記複数の第2開口部は、前記長方形の短辺が、前記短辺の延在方向に対して一列に並ばないように千鳥格子状に配列されている、半導体装置。 - 請求項1において、
前記第1配線層は、前記複数の第2端子が形成された第4配線層と前記第2配線層の間に形成され、
平面視において、前記第1導体パターンは、前記複数の第2端子のうちの一つと重なる、半導体装置。 - 請求項14において、
前記第1配線は、前記第1導体パターンと厚さ方向に重なる位置でビア配線を介して前記複数の第2端子のうちの一つと電気的に接続される、半導体装置。 - 請求項1において、
前記配線基板の前記コア層は、プリプレグ材から成り、
前記配線基板は、
前記第2面において、前記スルーホール配線に接続される第2スルーホールランド、を更に有し、
前記第1導体パターンは、前記第1スルーホールランドの上方、および前記第2スルーホールランドの下方に、それぞれ形成され、
平面視において、前記第1導体パターンの前記メッシュパターン部は、前記第1および第2スルーホールランドのそれぞれと重なる、半導体装置。
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US14/590,291 US9312216B2 (en) | 2014-01-27 | 2015-01-06 | Semiconductor device with semiconductor chip and wiring layers |
CN201510040725.8A CN104810346B (zh) | 2014-01-27 | 2015-01-27 | 半导体器件 |
HK15111570.8A HK1210874A1 (en) | 2014-01-27 | 2015-11-24 | Semiconductor device |
US15/059,948 US9620447B2 (en) | 2014-01-27 | 2016-03-03 | Semiconductor device |
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CN104010797A (zh) * | 2011-12-22 | 2014-08-27 | 帝人株式会社 | 用于制造成形制品的方法以及成形制品 |
JP6324738B2 (ja) * | 2014-01-27 | 2018-05-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6666200B2 (ja) * | 2016-05-25 | 2020-03-13 | 京セラ株式会社 | 配線基板および電子装置 |
CN107204325B (zh) * | 2017-05-25 | 2023-06-02 | 成都线易科技有限责任公司 | 电容器阵列及制造方法 |
JP2019114675A (ja) * | 2017-12-25 | 2019-07-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP7025948B2 (ja) * | 2018-02-13 | 2022-02-25 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
US11387187B2 (en) * | 2018-06-28 | 2022-07-12 | Intel Corporation | Embedded very high density (VHD) layer |
JP2020043219A (ja) * | 2018-09-11 | 2020-03-19 | ソニーセミコンダクタソリューションズ株式会社 | 回路基板、半導体装置、および、電子機器 |
JP7163205B2 (ja) * | 2019-01-18 | 2022-10-31 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US11605581B2 (en) * | 2021-01-08 | 2023-03-14 | Renesas Electronics Corporation | Semiconductor device having conductive patterns with mesh pattern and differential signal wirings |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994018812A1 (en) * | 1993-02-02 | 1994-08-18 | Ast Research, Inc. | A circuit board arrangement including shielding grids, and constructing thereof |
JPH07235741A (ja) * | 1993-12-27 | 1995-09-05 | Ngk Spark Plug Co Ltd | 多層配線基板 |
JP3307597B2 (ja) * | 1998-09-30 | 2002-07-24 | 株式会社 アドテック | 印刷配線装置 |
JP4204150B2 (ja) * | 1998-10-16 | 2009-01-07 | パナソニック株式会社 | 多層回路基板 |
US6184477B1 (en) * | 1998-12-02 | 2001-02-06 | Kyocera Corporation | Multi-layer circuit substrate having orthogonal grid ground and power planes |
KR100917081B1 (ko) * | 2001-03-14 | 2009-09-15 | 이비덴 가부시키가이샤 | 다층 프린트 배선판 |
US6977345B2 (en) * | 2002-01-08 | 2005-12-20 | International Business Machines Corporation | Vents with signal image for signal return path |
US6630628B2 (en) * | 2002-02-07 | 2003-10-07 | Agilent Technologies, Inc. | High-performance laminate for integrated circuit interconnection |
JP2004253947A (ja) | 2003-02-19 | 2004-09-09 | Nippon Telegr & Teleph Corp <Ntt> | インピーダンス変換回路 |
WO2005076683A1 (ja) * | 2004-02-04 | 2005-08-18 | Ibiden Co., Ltd. | 多層プリント配線板 |
DE102004060962A1 (de) * | 2004-12-17 | 2006-07-13 | Advanced Micro Devices, Inc., Sunnyvale | Mehrlagige gedruckte Schaltung mit einer Durchkontaktierung für Hochfrequenzanwendungen |
US7504904B1 (en) * | 2006-04-04 | 2009-03-17 | Unisys Corporation | Printed-circuit impedance control using skewed reference mesh |
CN101594732A (zh) * | 2008-05-27 | 2009-12-02 | 鸿富锦精密工业(深圳)有限公司 | 电路板 |
US8058954B2 (en) * | 2009-03-05 | 2011-11-15 | Apple Inc. | Transmission line with a cross-hatched ground plane that is either filled with conductive paint or covered by a conductive foil |
CN102473993B (zh) * | 2009-07-13 | 2014-01-22 | 株式会社村田制作所 | 信号线路及电路基板 |
US8704104B2 (en) * | 2010-07-19 | 2014-04-22 | Asml Netherlands B.V. | Electrical connector, electrical connection system and lithographic apparatus |
JP2012094646A (ja) * | 2010-10-26 | 2012-05-17 | Daisho Denshi Co Ltd | 特性インピーダンスコントロール対応プリント配線基板 |
JP6324738B2 (ja) * | 2014-01-27 | 2018-05-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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US20160190049A1 (en) | 2016-06-30 |
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